JPS5870497A - Checking system for abnormal state of memory - Google Patents

Abstract

PURPOSE:To check an existing ROM, by providing an ROM having the same contents as the existing ROM, comparing the information of both ROMs corresponding to a read-out address of a processor, and generating an alarm in case of dissidence. CONSTITUTION:When a read-out address is outputted, an ROM3 and an ROM3' are accessed respectively, and is outputted to a data bus 4 and a comparing circuit 5, respectively. Also, the comparing circuit 5 is connected to the data bus 4, too, and information from the ROM3 is also inputted to the comparing circuit 5. The comparing circuit 5 compares exclusive OR of information read out from the ROM3 and the ROM3', and in case of dissidence, an alarm signal is outputted from an external alarm output terminal 6.

Description

[Detailed Description of the Invention] In recent years, microcomputers have been using microcomputers. Due to the introduction of the read-only memory (hereinafter referred to as FsROM), the microcomputer of Tonto has an ambiguous +f!r d (area of 1 history) month δt.This ROM The memory disk (memorized 1'#4) r was fixed and the memory disk was used as a starting point, and the memory disk has extremely good reproducibility and was made with great dedication.However, this P( The abnormal sound check force type when an abnormality is stopped in the OM memory disk is not enough to use the f separation XL, so due to the change in the ROM memory disk, there will be no operational dissonance even if the ROM memory disk is in summer. Until it came to light, there was a risk that J4K's injuries would lead to serious accidents.

This first ROM is used separately from the first ROM to remove the above-mentioned mermaid.
A second I (OM) having a memory disk of 1 iJ- is provided in parallel, and a first S and a second ROM corresponding to the address code of the microprocessor are output. The purpose of this method is to provide a method of checking whether there is an abnormality in the memory of the first ROM by setting an alarm on the first ROM that indicates a mismatch.

After that, I looked up the 8p1 drawing of Kazumi Motoaki's JM Reli and decided to give it to 6+ Oda.

Fig. 1 is a diagram showing one implementation of VU money, and Fig. 2 is a time chart of the center j mountain and U shown in 5th first kyo. In FIG. 1, when the microprocessor 1 outputs the VCme address 1 on the address bus 2, the first memory MOM 3 and the second memory ROM 3 are accessed, respectively. Then, the f# information corresponding to the address number 16 is outputted onto the data bus 4 and the ROM 3 and the comparator circuit 5. Further, the comparator circuit 5 is connected to the data bus 5, and m@i from 1'tOM 3 is also input to the comparator circuit 5 via the data bus 5. This comparison episode 45
corresponds to the starting address 1g, the first memory 1 (0M3) and the second memory 0M3 d and 'lNm. exclusive of
During the game against the Philippines on April 4th, if Taniya's 1W signal showed a discrepancy, the external signal output terminal 6 would output an external signal. Is the second figure? To explain with reference to the microprocessor 1 address number (see Figure 2),
a)) is the output az sea and this opening address No. 15 (
Corresponding to a), the first memory, ROji 13, is sent an acknowledgment on the data bus 4 (see Figure 2). Extracted 1
-1t 4 (b) vJ, human input to comparison circuit. f
In addition, ROM 3' corresponds to this address number 1g.
1. The human power is also transferred to the comparison circuit 5 (Fig. 42 (C)). By this comparison circuit 5, the ROM
What is the comparison between 1 Kenbori (t') and 1 (OM 3' sword, read awn, and awn (C) table), which were published from 3 to 4, and people's 1 * Bara (su, (C) is inconsistent and Meshin/Agedai 4 outside 8B-Hotato Itako 6 to outside a pregnant woman number (2nd)
(d)) is output 06.

Based on the above, 4+1. Memory record 1. In order to scold and scold the user for checking the button in the month of May, the microcomputer's operation is extremely difficult.
Meri J Shiru. Therefore, there is a risk of an accident due to malfunction.1. C Utani 1 Satoyama C11 m I see the advantage of applying it to fairy tales as well.

(3)

[Brief explanation of drawings]

Figure 1 is a block diagram showing the execution of Kuri's work, Figure 2 is
・In Figure 1, there are 1g and 3 of each of the tubes that appear.
This is a time chart. ■...Microprocessor, 2...Address bus,
d, 3... Read only memory (ROM), 4
・・Door bus, 5・・Comparison circuit, 6・・External 11
Information output terminal. Representative Patent Attorney Li, Shui (Li 6, 1 person) (4) Figure 1 Figure 2

Claims (1)

[Claims] U) The 12th and 2nd memory metals marked with the same r#m are provided and output from the microprocessor. In response to the butt-out address signal, the first memory sword) is removed from the data bus. The information is compared by the τ north-I9 means, and if the previous tracks do not match, an external d information signal is output from the previous V-pi comparison means to the Q lifting platform. .