JPS5869112A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To obtain the linearity of conversion, by obtaining a lower-order bit, through the input of reference voltages of an odd number order to a terminal of a voltage divider, reference voltages of an even number order to another terminal of the voltage divider and the voltage division of the potential difference, and the comparison of an analog input voltage with the other reference voltages to be produced. CONSTITUTION:An analog input signal Vin is sample-held 11 and inputted to comparators 12a, 12b and 12c. In the comparators, a comparison voltage Vref of a specified level with a reference voltage generator 13 outputs reference voltages V11, V10, V01, V00 via resistors 13a-13d. An upper-order 2-bit of the output of the comparators 12a-12d is encoded 15 via parallel exclusive OR circuits 14a-14d. Switching circuits 16a-16d selectively pick up reference voltages of an odd and an even number order nearest the analog input voltage and give the voltages to a voltage divider. The output of the voltage divider 17 is given to comparators 18a-18d and a lower-order 2-bit is outputted from an encoder 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly practical analog-to-digital converter with excellent linearity.

As an analog-to-digital converter (A/D converter) that performs high-speed analog-to-digital conversion, a parallel-serial type configured as shown in FIG. 111 is known. This A
/D conversion Wi#d is a 4-bit type of 2 bits plus 2 pits, and is composed of a front-stage conversion section, a rear-stage conversion section, and K.

In other words, the analog signal sampled and bolded in the sample circuit 1 is sent to the comparator 2 installed in parallel in the previous stage conversion section.
Resistors JatJb and je are commonly input to a r 2 b g 2 e and connected in series.

The level of each voltage is compared with a plurality of comparison reference voltages obtained by driving 3d with a constant current source 3. These comparators! 'a
, job, and 2o are input to the encoder 4, and the upper 2 pits of digital data are obtained by roughly discriminating the analog signal levels of the previous 8 analog signals. The output of the encoder 4 is input to a local D/A converter 5 to obtain a reproduced analog signal corresponding to the digital data, and this is input to a subtractor 6 to determine the difference from the input analog signal. This analog signal difference consists of signal components below the minimum discrimination level that were not converted by the digital conversion process before the upper P. Therefore, the output of this differentiator 6 is transferred to an extremely parallel comparator 7a17.
A resistor J connected in series, led in common to b + 7 c
ia, #b.

The level of Jlc+JId is compared with a second comparison reference voltage which is driven by a constant current source 8. This comparator 7 *
The comparison results of +7b and 7e are provided to the encoder 9 to obtain digital data of the lower two pits. Note that the comparison reference voltage difference of the first-stage conversion section is set to 2n times the comparison reference voltage difference of the second-stage conversion section (where n is the number of lower bits). As a result, a total of 4-bit digital signal consisting of the upper 2 bits, bits, and lower 2 bits is obtained as the output of the encoders 4 and 9.

According to the A/D converter configured in this way, high-speed and high-precision analog-to-digital conversion can be achieved by parallel level comparison and level comparison in which reference levels corresponding to conversion accuracy are set in multiple stages. can be processed. However, in this A/D converter, the local D/A converter 5 obtains the analog voltage indicated by the digital data of the upper two pits.
Analog processing is required to calculate the difference from the input analog voltage and use it to convert the lower bits. This local D/A
The converter 5 is, for example, as shown in Figure 2 (,).
It is composed of a current switch consisting of four transistors and a ladder resistor whose current is switched by these t-optical switches. For this reason, errors are likely to occur in the converted analog voltage due to the above-mentioned variations in the internal resistance and fluctuations in the current. That is, the local D/A converter Fi shown in Figure (a) K is shown in terms of value as shown in Figure (b), and the resistors Rc, R
, and the base-to-emitter voltage V of the transistor TR
Depending on the variation in IIH, its output voltage ■. The following errors occur. That is, the error is Δ■, ΔRc1ΔR
When expressed as E and ΔVIE, the following errors occur. However, V and - are resistance R.

, and lc is the collector voltage of the transistor TR. Therefore, the pairwise error of the resistor Rc + RE generally exists on the order of ±0.5-, and the variation in η1 exists on the order of ±1 mV. Therefore, even if Rc and RE are strong, in the worst case, a one difference ΔvO/v of the output voltage v0 will occur. It is necessary to suppress the A/D conversion error caused by this error to less than the above-mentioned output voltage error 1k1asn, which requires a highly accurate local D/A converter. -If the error in the pussy cannot be suppressed,
As shown in the third LJ, a next-side connection error occurs at the bit data change point of the upper bit, and as a result, it becomes impossible to perform analog-to-digital conversion with good roughness and high precision.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to eliminate the occurrence of connection differences caused by errors in local D/A converters, and to
It is an object of the present invention to provide a highly practical analog-to-f4 digital converter capable of performing accurate analog-to-digital conversion at four speeds with good directivity.

The outline of the present invention is as follows: Compare the analog input 'salmon pressure' with a plurality of reference voltages using comparators with good imaginary numbers in parallel. From the comparison results, obtain the digital data of the upper bits, and according to the comparison results, Selectively extract the odd-order reference voltage and the even-order reference voltage that are closest to the analog voltage voltage, input the odd-order reference voltage to one end of a voltage divider, and divide the even-order reference voltage into the above-mentioned voltage divider. A secondary reference voltage is generated by inputting it to the other end of the voltage converter and dividing the potential difference, and comparing the levels of this secondary reference voltage and the analog input voltage, and converting the comparison result into bits according to the comparison result of the upper bit. By inverting and obtaining digital data of lower bits, the above-mentioned purpose is effectively achieved.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a schematic configuration diagram of an A/D converter according to an embodiment, and ζ indicates a 2-bit glass 2-bit 04-bit converting type. An analog input signal is sampled and held by a sampling circuit 11, and three comparators 12m are arranged in parallel.

12b and l1lc respectively. These comparators Jffia, Iffb, and fje are each supplied with a comparison reference voltage of a predetermined level generated by the standard voltage generation bI3, and the analog inputs are compared. The reference voltage generator 13#i has one end at a predetermined potential V. Four resistors 13m, 11 connected in series fixed at f
A constant current is supplied to b, 13c, and 13d by a constant current source 13m, and each resistor 13a.

A reference voltage of a predetermined level is generated from terminals 13b, 13c, and 13d. Therefore, each reference voltage is
For example, Vref + Vtt + Vto, VOl
＋Vo.

@Sho・Vref and V・
・Is the level difference between the analog input voltage and the dyna? It is set up in a way that screams “Tsukurenji”. and the comparators 12m, 12
b, 12c are the Vth reference voltages IVlo
, VOl are input and compared with the analog input voltage level Via.For example, vl2. vl. , vo
When Vin is null, a signal of logic 11 is output, and in other cases, a signal of logic 101 is output as the comparison result -C.

Therefore, the outputs of these comparators 12h+12b, 12q are connected to four exclusive OR circuits (E
X-OR) l1IK of 14*, 14b, 14e, 14d
It is given to each of the two that touch each other. EX-OR1
4&li logic 11' signal and the output of the comparator 121 are inputted, EX-OR14b ti each output of the comparators 12m and 12b is inputted, and EX-OR14c is the comparator 11b.

Each output of the comparator 12c is manually inputted, and the EX-OR 14d receives the output of the comparator 12c and the logic 101 signal and performs logical processing on each. These i:XX-0R14,14
The logic outputs of b, 14c, and 14d are input to the encoder 15 and encoded, and the comparison reference potential V1t is applied to this ζ.
Analog input voltage Wi discriminated by lV1・IV@1
Dinotal data of the top two pits for n is obtained.

On the other hand, the reference voltages Vr@f, Vtt, V, . . . VOl, Y@ll generated and outputted by the reference voltage generator 13 are selectively conduction-controlled by the outputs of the EX-ORs 14m, 14b, 14c, and 14d. switch circuit 16a.

16b, 16c, and 16d, respectively. These switch circuits 16m, 16b, I6a, 16d are connected to the comparison reference voltage vr@f*vttlvl,l
Among Vllll r v@IQ', select odd-numbered reference voltages and even-numbered reference voltages that are also close to the level VC@ of the analog input voltage Vin, and connect the upper MI2 odd-numbered reference voltages to resistors connected in series. 17a+17b, I
re.

17d is supplied to one end of the voltage divider 17, and the other end is supplied with an even-numbered reference voltage.

That is, the switch circuits 16m, 16b, 16a, and 16d isometrically select the one closest to the analog input voltage VinK among the odd-numbered reference voltages vr*f*vto+VOO to one end of the divider 17. The other end of the voltage divider I7 is supplied with an even-order reference voltage v11 +
It is configured to select and supply the one of the VOIs that is closest to the analog input voltage Vin. However, the E unit 17 supplied with the reference ta= selected in this way divides the potential difference into an equal dividing pressure 17, 'l
'tt, vt.

Three secondary reference voltages νo1 are generated and supplied to the subsequent comparators 18 & r18b*18c, respectively. The potential difference between the secondary reference voltages υtt and t'to + t'ot generated by the voltage dividers 18m, 18b, and 18c is determined by the conversion minimum bit value, that is, tlilBK. Such a secondary reference voltage map 11
Comparator 18 m that inputs + '18 + '<11
, 1 a b r18・are these reference voltage ma
Town・,嘗. 1 and the analog input voltage Vit+ are compared in level. And these comparators 1
11m.

The comparison results obtained by the signals 11b and 18c are applied to the encoder 20 via the switch 1 path 19, and are outputted as the 1st and 2nd bits or the digital signal. This switch circuit 19 is switched and controlled by an OR circuit 21 that performs an OR process on the outputs of the EX-OR 14m+14g.
As a result, the comparator I Ji a T 1 g b
The comparison result of +18c is given to the encoder 20 after the pit order is inverted. Specifically, the outputs of the comparators IJi & +IJIe are exchanged and supplied to the encoder 20 in accordance with the comparison results of the preceding stage comparators 1:la+11b and 11e. The switch circuit 19 exhibiting such a function is composed of a plurality of current switch transistors forming a differential pair, for example, as shown in FIG. The transistors 22 and 23 are selectively made conductive by the output of the OR circuit 21, and the output of one of the comparators 18h and 11lb is selected and outputted to the encoder 20. In this bit position inversion process by the switch circuit 19, the level of the reference voltage applied to the voltage divider 17 is inverted depending on the level of the analog input voltage Vin, and the secondary reference voltages v, 1 . Since the output relationship with respect to C101''·1 is reversed, this is corrected.

Thus, according to the A/D converter configured in this way, the analog input voltage ■in is the reference voltage ■11 r V@
. , ■, and 1, and the top two digital data are obtained from the comparison results. Also, according to the above comparison results, the reference voltage Vr@f l Vl
l + vto + vot l veo is selected and voltage divider 17. is applied to generate a secondary reference voltage.

This secondary reference pressure is set as shown in FIG. That is, assuming the LSB voltage is V, the analog input voltage V
When the level of in is higher than the reference voltage Vtt, ψ11:':Vll+τ ya1(1=Vl+2 ν ν.1=V11+31. Also, when vl<Vits<Vts, then vtt=Vll+a"t'to = Vll + 2ν νas = vt.+ν, and when Vat < Vln < Vto, ν
tt"v・1+ν tli field = VH+ 2 v ν.1=V.1+3v Furthermore, when vo.<Vit><Vat, lt
IE: Vll + 3 M νKame·=V,, +211 V·1=V···+ν, respectively. Then, the comparators 18m and jab compare these set secondary reference voltages Y, 91·, ν·1 and the analog input voltage Vit&.

xseK is used to compare the levels and obtain information on the lower two bits.

At this time, as is clear from the level relationship of the secondary reference voltages, K, reference voltage ν11, and x1 are the reference voltage VH of the analog input voltage Vin.

■,. The relationship is reversed depending on the magnitude relationship of the level with respect to tVat. Therefore, if the comparison result with this reversed relationship is used as it is, the level relationship will be reversed, so the comparator 18 &.

The outputs of comparator 18a are mixed and extracted, thereby
The level relationship of the secondary reference voltages set to m, 18b, and 18e is kept isometrically constant. Therefore, 5 the secondary comparison reference voltage t'tt + vt thus set.

+t'ot and the analog input voltage Vin, and by asking the encoder 20 for the results of comparing the levels, it is possible to effectively obtain the signal data of the lower two bits.

Thus, according to this A/D converter, the pre-stage comparator 12
A reference voltage is selected according to the level region of the analog input voltage vthn whose level has been determined by the voltage dividers 11, 12b, and 12c, and is applied to the voltage divider 11 to generate a secondary reference voltage that subdivides the level region. Comparator Z#a, 18b, 18e
Since the level of the analog input voltage Vim is directly determined and the f4 digital data consisting of the upper 2 bits, bits, and lower 2 bits is obtained, the linearity of the set comparison reference voltage can be made good. . Moreover, unlike conventional analog processing such as reproducing analog voltage using a local D/A converter, analog input voltage Vtn
Since the levels are directly compared in the front and rear stages, there is no connection error that occurs in the conventional method, and it is therefore possible to obtain conversion characteristics with extremely good linearity.

Moreover, since analog processing as in the prior art is not required, the configuration can be greatly simplified. Since the reference voltages for generating the secondary reference voltages are respectively extracted corresponding to the terminals of the voltage divider 11, the switch circuits 16m, 16
b, 14t@, 16d, and the switch circuit 19 can be easily configured. Since the voltage is selected from the standpoint of circuit design and practical application, it is possible to stabilize the base S voltage level. It also has the effect of gaining guilt. This is due to the fact that the current switch transistor circuit board that constitutes the slave circuits 16m, 16b, 16e, and 16d can be constructed in a simple manner. Therefore, stable and highly reliable analog/7-', 1-notal conversion is possible, and its effects are tremendous.

By the way, the switch circuits 16m and 16b mentioned above.

16c and 16rl can be easily realized by a current transistor circuit as shown in FIG. 7, for example.

That is, the reference voltage Vr@f generated by the reference voltage generator I3
l yll vto l vot -v00 wo sore -t'tt Transistors such that the current is extracted via the emitter follower transistor A and applied to both terminals of the voltage divider I7 via the current switch transistor B in a MF manner. Configure the circuit. The conduction of these current switch transistors B is controlled by the transistor C, which is controlled to be conductive in response to the outputs of the comparators 12m, 12b, and 12a. good.

The switch circuits configured in this manner are the switch circuits 16m, 16b, and 16c shown in FIG. 4 above.

16d and EX-OR14m, 14b, 14c, and 14d play a critical function, and when transistor C is turned on, the current supplied to the current switch and transistor B is sucked, and as a result, the selection of the reference voltage is blocked. .

And the current switch in the ON operation state, Chitrannosta B
Of the reference voltages obtained through It is possible to realize a switch and a child circuit by reducing the number of sub-circuits.In addition, when selecting the reference voltage in this way and generating the secondary reference voltage, the above reference voltage is the emitter follower transistor A and the current switch. , Chitrannosta B undergoes level shifting by two stages of transistors. Therefore, in this case, the analog input voltage Vin is also
) After applying the same level shift through the level shift circuit as shown in (b), the subsequent comparator 18m+l1
K is good enough to supply lb +18eVc. w46
The one shown in the figure (-) performs level shifting using two stages of transistors connected as Darlington transistors, and the one shown in the same figure performs level shifting using emitter follower transistors configured in two stages of Φ)Fi. Using the circuit [7], by applying a similar level shift to the analog input voltage Vin and the selected reference voltage,
The relative accuracy of the comparison level can be ensured, and the conversion accuracy and its linearity can be sufficiently improved.

9th diagram above switch circuit? i, MOS) This shows an example configured using a runnostar. As is well known, K
MO8) Rannostar number, 1, that /. , the F characteristics are very good, so it can be used as a switch as is. Further, here, the voltage divider 17 is constituted by capacitors 1 to C connected in a single line, but even in this case, highly stable voltage division of the reference voltage difference by capacitance division can be performed.

As described above, according to the present invention, it is possible to easily ensure the linearity of the conversion characteristic, and to suppress the occurrence of connection errors.

Moreover, it can be easily configured without using a local D/A converter for analog processing, and is excellent in practicality. Since analog processing is not particularly required, operational reliability can be dramatically improved.

3. The present invention is not limited to the above-mentioned implementation.
In IP II, the number of conversion pits and the allocation of the number of conversion pits in the front and rear stages may be determined according to the specifications.Also, when the current switch is configured with MOB transistors as described above, the offset error of the In order to prevent this from occurring, it is preferable to configure the voltage divider XV with a capacitor.

Further, the level shift processing of the analog voltage may be performed in accordance with the means of selection processing of the reference voltage. In short, the present invention can be implemented with various modifications without departing from its scope.

[Brief explanation of the drawing]

Figure 1 shows an example of a conventional A/D converter, and Figure 2 (
a) (b) is a diagram showing the configuration of the local D/A converter and its value circuit; Figure 3 is a diagram showing the conventional distortion error; Figure 4
The figure is a schematic configuration diagram of a converter showing one embodiment of the present invention. Figure 5 is a diagram showing an example of the configuration of the switch circuit 19 in the same embodiment. Figure 6 is a diagram showing the reference voltage and voltage difference in the same embodiment. A diagram showing the relationship with the next reference voltage, FIG.
A diagram showing an example of the configuration of an X-OR and a switch circuit, FIG.
9A and 9B are diagrams each showing a configuration example of a level shift circuit, and FIG. 9 is a diagram showing a configuration array of MOB transistors of a switch circuit. 11-・Sample circuit, 12m, 12b*12@-・
- Comparator, 13...Reference [EE generator, 14&+14
b to 14d... Exclusive OR circuit, 15... Encoder, 16 Hatake, 16b, 16c, 16d... Switch circuit, 17... Voltage divider, 18h, 18b, 18c...
・Comparator, I9... True A, Chi circuit, 20... Encoder, 2I... OR circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 4 (MSBII) (LSBq) Figure 5 Figure 6 Figure 7v! J Figure 8 (a) (b) Figure 9 completed?

Claims (2)

[Claims] (1) A plurality of comparators that respectively compare a plurality of reference voltages with different levels and an analog input voltage level, and obtain an upper bit side digital signal value that matches the analog input voltage level from the comparison results of these comparators. means for selecting an odd-numbered reference potential closest to the analog input voltage source according to the comparison result of the comparator and supplying it to one terminal of the voltage divider; means for selecting an even-ordered reference voltage closest to the input voltage level and applying it to the other terminal of said voltage divider; and a plurality of secondary references generated in the voltage divider to which said selected reference voltages are applied. a plurality of secondary comparators that respectively compare the voltage and the previous 14 analog input voltage levels; the comparison results of these secondary comparators are subjected to bit order inversion processing according to the comparison results of the comparators, and the lower An analog/r4 notal converter characterized in that it is equipped with means for obtaining a bi- and g-side disotal value. (2) A voltage divider consists of resistor circuits connected in series, one terminal of which inputs the selected odd-numbered reference voltage, and the other terminal inputted the selected even-numbered reference voltage. An analog-to-digital converter according to claim 1.