JPS5868959A - Film carrier - Google Patents
Film carrierInfo
- Publication number
- JPS5868959A JPS5868959A JP16745881A JP16745881A JPS5868959A JP S5868959 A JPS5868959 A JP S5868959A JP 16745881 A JP16745881 A JP 16745881A JP 16745881 A JP16745881 A JP 16745881A JP S5868959 A JPS5868959 A JP S5868959A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- lead
- film carrier
- wiring pattern
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＩＣ，ＬＳＩ等を搭載するフィルムキャリアに
関し、特に配線パターンを改良したフィルムキャリアに
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a film carrier on which ICs, LSIs, etc. are mounted, and particularly to a film carrier with an improved wiring pattern.
従来用いられているフィルムキャリアの一例としては、
第１図に示す如く、ポリイミド樹脂等からなるフィルム
ｌに１個のデバイス穴２を挾んで２個のカッティング穴
３が穿設され、デバイス穴２とカッティング穴３間には
複数の配線パターン４が設けられ たものがある。フィ
ルムキャリアはこれらの一連のデバイス穴２、カッティ
ング穴３、及び配線パターン４を等しいピッチで繰返し
有している。５はフィルム１を送るスプロケットに係合
する穴である。An example of a conventionally used film carrier is
As shown in FIG. 1, two cutting holes 3 are made in a film l made of polyimide resin or the like, sandwiching one device hole 2, and a plurality of wiring patterns 4 are formed between the device hole 2 and the cutting hole 3. Some have a The film carrier has a series of device holes 2, cutting holes 3, and wiring patterns 4 repeated at equal pitches. 5 is a hole that engages with a sprocket for feeding the film 1.
このようなフィルムキャリアを使用するには、デバイス
穴２部分に、ＩＣ，ＬＳＩその他の素子を搭載して、そ
れらの素子のボンディングバットとデバイス穴２内に突
出した配線パターン４（この部分の配線パターン４を以
下インナーリード６と称す）の端部とを接続した後、図
の破線７に沿って切断し、カッティング穴３に突出した
配線パターン４（この部分の配線パターン４を以下アウ
ターリード８と称す）の端部を時計、電子卓上計算機、
サーマルヘッドなどの端子あるいは配線パターンに接続
する。To use such a film carrier, IC, LSI, and other elements are mounted in the device hole 2, and the bonding butts of those elements and the wiring pattern 4 protruding into the device hole 2 (the wiring in this part) are After connecting the pattern 4 to the end of the wiring pattern 4 (hereinafter referred to as the inner lead 6), the wiring pattern 4 is cut along the broken line 7 in the figure and protrudes into the cutting hole 3 (this portion of the wiring pattern 4 is hereinafter referred to as the outer lead 8). (referred to as)) can be used for watches, electronic desktop calculators, etc.
Connect to the terminal or wiring pattern of a thermal head, etc.
第１図に示した従来のフィルムキャリアでは、各インナ
ーリード６の長さが等しく、かつ各アウターリード８の
長さも等しい。したがって、インナーリード６の先端部
はディバス穴２の一方の辺（図では縦の辺）に平行に配
列され、かつアウタ−リード８の端部もカッティング穴
３の一方の辺（糾の辺）ｌこ平行に配列されることにな
る。デバイス穴２、カッティング穴３．１線パターン４
の形状の異なる他の従来例にお・いても、インナーリー
ド、及びアウターリードの長さ、あるいはそれらの先端
部配列状態は第１図に示すものと同様である。In the conventional film carrier shown in FIG. 1, each inner lead 6 has the same length, and each outer lead 8 has the same length. Therefore, the tip of the inner lead 6 is arranged parallel to one side (the vertical side in the figure) of the diversion hole 2, and the end of the outer lead 8 is also arranged parallel to one side (the vertical side in the figure) of the cutting hole 3. They will be arranged in parallel. Device hole 2, cutting hole 3.1 line pattern 4
In other conventional examples having different shapes, the lengths of the inner leads and outer leads or the arrangement of their tips are the same as those shown in FIG.
このようなフィルムキャリアにおいては、例えばＩＣ等
の素子の実装に際し、素子のボンディングバットとイン
ナーリード端部間の接続で形成されるバンブがデバイス
穴２の一辺に平行に配列することになるので、隣接ボン
ディングバット間の１７１隔をあまり小さくできず、し
たがって実装密度を大きくできない問題がある。また、
フィルムキャリアを時計等に実装するに際しても、アウ
ター、リード゛と時計等の端子等とめ接続部分の隣接す
るものとの間隔をあまり小さくできず、したがもてこの
点からもＩＣ等の実装密度を大きくできない［１＋ｉ題
がある。In such a film carrier, when mounting an element such as an IC, for example, the bumps formed by the connection between the bonding butt of the element and the end of the inner lead are arranged parallel to one side of the device hole 2. There is a problem in that the distance 171 between adjacent bonding butts cannot be made very small, and therefore the packaging density cannot be increased. Also,
When mounting a film carrier on a watch, etc., it is difficult to make the distance between the outer lead and the terminals of the watch, etc., adjacent to each other, and therefore the mounting density of ICs, etc. cannot be made larger [1+i problems exist.
本発明は上記問題に鑑み、ＩＣ等の素子の実装にはイン
ナーリードと素子とのボンディング、あるいはアウター
リードと時計等の装置とのボンディングの工程の歩留り
整向上することを目的とするものである。In view of the above problems, the present invention aims to improve the yield of the process of bonding between inner leads and elements, or bonding between outer leads and devices such as watches when mounting elements such as ICs. .
以下、一実施例を示す図面を参照して本発明の詳細な説
明する◇
第２−は本発明の一実施例を示す図で、第１図に示した
従来例と同形状のデバイス穴２及びカッティング穴３を
有するフィルムキャリアについて示しである。本実施例
は配線パターン４のインナーリード１１及びアウターリ
ード１２の長さを変化させ、インナーリード１１の先端
の配列、及びアウターリード１その先端の配列がともに
デバイ 。Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment.◇ 2nd- is a diagram showing one embodiment of the present invention, in which a device hole 2 having the same shape as the conventional example shown in FIG. and a film carrier having cutting holes 3. In this embodiment, the lengths of the inner leads 11 and outer leads 12 of the wiring pattern 4 are changed, and both the arrangement of the tips of the inner leads 11 and the arrangement of the tips of the outer leads 1 are Debye.
ス穴２あるいはカッティング穴３の一辺（縦の辺）に斜
めの線上にくるようにし、た点に特徴を有する。The cutting hole 2 or the cutting hole 3 is characterized by being placed on a diagonal line on one side (vertical side).
第３図に本ｉ施例のテープキャリアを用いて、ＩＣを装
置に実装した例を示す。すなわち、第２図ノテハイス穴
２部分に１ｃ１３を搭載してインナーリード１１と１ｃ
１３のバット部とを接続した俵、フィルム１を破線７に
沿って切断して部分１′を切り取り、次にアウターリー
ド１２を時計等のテ：装置の基板１４の配線パターン１
５に接続したものである。FIG. 3 shows an example in which an IC is mounted on a device using the tape carrier of Example I. In other words, 1c13 is mounted in the 2 parts of the high speed hole in Fig. 2, and the inner lead 11 and 1c are connected.
Cut the bale and film 1 connected to the butt part of No. 13 along the broken line 7 to cut out the portion 1', and then connect the outer lead 12 to the wiring pattern 1 of the circuit board 14 of the device.
5.
卵３図において、１６はｉｃｌ ３のバット部とインナ
ーリード１１の先端との接続により形成されたバンブで
、デバイス穴２の一辺（縦の辺）に対して斜め方向に配
列されている。１７はアウターリード１２と配線パター
ン１５どの接続により形成されたボンディング部で、切
断されたフィルム１′の縦の辺（第２図のカッティング
穴３の縦の辺）に対して斜め方向に配列されている。In Figure 3, numeral 16 denotes bumps formed by connecting the butt part of the ICL 3 and the tip of the inner lead 11, and are arranged diagonally with respect to one side (vertical side) of the device hole 2. 17 is a bonding portion formed by connecting the outer lead 12 and the wiring pattern 15, and is arranged diagonally with respect to the vertical side of the cut film 1' (the vertical side of the cutting hole 3 in FIG. 2). ing.
本実施例において、いまバンブ１６の配列とデバイス穴
１２の縦の辺とのなす角質を４５変とすると、隣接バン
ブ（間の間隔は、従来例の如くバンブ１６がデバイス穴
１２の縦の辺に平行に配列される場合に比べて３倍にな
る。その結果、隣接バンブ間の間隔を従来ｌ′ｆ＃□り
に採つ場合には、バンブ１６の配列の密■、すなわちＩ
Ｃ１３の実装密度は１倍になる。逆にバンブ１６の配列
密度を従来例と同じに保つ場合には、隣接パン１間の間
隔が広がることによりｉｃｌ３のバット部とインナーリ
ード１１とのボンディング工程の歩留りが向上する。In this embodiment, if the distance between the arrangement of the bumps 16 and the vertical side of the device hole 12 is 45 degrees, then the distance between the adjacent bumps (the spacing between the bumps 16 and the vertical side of the device hole 12 is the same as in the conventional example). As a result, when the spacing between adjacent bumps is conventionally l'f#□, the denseness of the arrangement of bumps 16, that is, I
The packaging density of C13 is doubled. On the other hand, when the arrangement density of the bumps 16 is kept the same as in the conventional example, the interval between adjacent pans 1 is widened, so that the yield of the bonding process between the butt part of the ICL 3 and the inner lead 11 is improved.
また、ボンディング部１７の配列とカッティング穴の縦
の辺とのなす角変も仮に４５変とすると、上記と全く同
様にして、従来例と比べて実装密度が３倍になり、ある
いは実装密度を従来例と等しく保った場合にはアウター
リード１２と配線パターン１５との゛ボンデイング工程
の歩留りが向上する。Furthermore, if the angle between the arrangement of the bonding portions 17 and the vertical side of the cutting hole is also 45 degrees, then in exactly the same way as above, the mounting density will be tripled compared to the conventional example, or the mounting density will be increased. If it is kept equal to the conventional example, the yield of the bonding process between the outer lead 12 and the wiring pattern 15 will be improved.
第２図に示した実施例では、インナーリード１１の先端
とアウターリード１２の先端をともに穴の一辺（縦の辺
）に対して斜め方向に配列するように長さを調整してい
るが、本発明はインナーリード１１とアウターリード１
２のいずれか一方の先端配列のみが穴の一辺に対し斜め
方向にされ、他方の先端が穴の一辺に平行である構成を
も包含するものである。それらの構成は、穴の一辺に斜
め方向の先端配列を有するインナーリード又はアウター
リードにおいて本発明の効果を発揮する。In the embodiment shown in FIG. 2, the lengths are adjusted such that both the tips of the inner leads 11 and the tips of the outer leads 12 are arranged diagonally with respect to one side (vertical side) of the hole. The present invention has an inner lead 11 and an outer lead 1.
The present invention also includes a configuration in which only one of the tips of No. 2 is arranged obliquely with respect to one side of the hole, and the other tip is arranged parallel to one side of the hole. These configurations exhibit the effects of the present invention in inner leads or outer leads having an oblique tip arrangement on one side of the hole.
インナーリード１１あるいはアウターリード１２の先端
の配列は第２図以外の種々の変形か可能である。例えば
インナーリード１１に関しては、第′４１シ１の如く２
本単位で長さが変化していてもよい。The arrangement of the tips of the inner leads 11 or outer leads 12 can be modified in various ways other than those shown in FIG. For example, regarding the inner lead 11, 2
The length may vary from book to book.
長さの等しい隣接インナーリード１１間では効果はない
が、長さの異なる隣接インナルリード１１ 聞において
本発明の目的を達成することができる。Although there is no effect between adjacent inner leads 11 having the same length, the object of the present invention can be achieved between adjacent inner leads 11 having different lengths.
また、第５Ｍに示す如く、長いインナーリードと短゛か
いインナーリードと交互に繰返して配列しても本発明の
目的を達成することができる。Further, as shown in No. 5M, the object of the present invention can also be achieved by alternately arranging long inner leads and short inner leads.
本発盟において、インナーリード１１の先端位■ハを変
化させる場合には、ＩＣ等のバット部の形成位ｉｄもそ
れに対応して変化させなければならない力？、ＩＣ等の
バット部の形成位置は自由に設定できるのみでなく、Ｉ
Ｃ等の一辺に対し平行にバット部を配列する従来例に比
べて、本発明に適応させたバット部は隣接するものとの
間隔が広くなるためバット部の密度を高めることができ
、あるする場合にはバット部形成工程の歩留りが向上す
る。In the present invention, when changing the tip position of the inner lead 11, the force required to change the formation position ID of the butt part of the IC, etc. accordingly? Not only can the formation position of the butt part of IC etc. be set freely, but also the I
Compared to conventional examples in which the butt parts are arranged parallel to one side such as C, the density of the butt parts can be increased because the spacing between the butt parts adapted to the present invention is wider, and the density of the butt parts can be increased. In some cases, the yield of the butt part forming process is improved.
以上詳述した如く、本発明はインナー“リード及びアウ
ターリードの少なくとも一方の先端位置を不揃いにした
ので、隣接するボンディング部等の間隔を従来のものよ
り広くすることができ、したがってＩＣ等の素子の実装
室間を高めることができる他、ボウディング等の工程の
尖細りを向上させることができる。As detailed above, in the present invention, since the tip positions of at least one of the inner lead and the outer lead are made uneven, the distance between adjacent bonding parts, etc. can be made wider than in the conventional case. In addition to increasing the distance between mounting chambers, it is also possible to improve the sharpness of processes such as bowing.
第１図は従来のフィルムキャリアの一例を示す平−面図
、第２ｖｌｌは本発明の一実施例を示す平面図、均１□
３図は、第２図の実施例にＩＣを実装した状態を示す平
面図、東、４図及び第５図はそれぞわ他の実施例を示す
平面図である。
１、・・・フィルム、２・・・デバイス穴、３・・・カ
ッティ、フグ穴、４・・・配線パターン、６．１１・・
・インナーリード、８．１２・・・アウターリード、１
３・・・ＩＣ。
１６・・・バンブ、１７・・・ボンディング部。
第ｉｓ
第２図
第３図
第４図 第５図FIG. 1 is a plan view showing an example of a conventional film carrier, and 2nd vll is a plan view showing an embodiment of the present invention.
3 is a plan view showing the embodiment shown in FIG. 2 with an IC mounted thereon, and FIGS. 4 and 5 are plan views showing other embodiments, respectively. 1. Film, 2. Device hole, 3. Cutty, puffer hole, 4. Wiring pattern, 6.11.
・Inner lead, 8.12...Outer lead, 1
3...IC. 16... Bump, 17... Bonding part. Fig. 2 Fig. 3 Fig. 4 Fig. 5
Claims (1)
とカッティング穴とを有するフィルムキャリアにおいて
、上記デバイス穴とカッティング穴の少なくとも一方に
おいて上記配線パターンの先端位置が不揃いであること
を特徴とするフィルムキャリア。A film carrier having a device hole and a cutting hole connected by a plurality of wiring patterns, characterized in that the tip positions of the wiring patterns are irregular in at least one of the device hole and the cutting hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16745881A JPS5868959A (en) | 1981-10-19 | 1981-10-19 | Film carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16745881A JPS5868959A (en) | 1981-10-19 | 1981-10-19 | Film carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5868959A true JPS5868959A (en) | 1983-04-25 |
Family
ID=15850046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16745881A Pending JPS5868959A (en) | 1981-10-19 | 1981-10-19 | Film carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5868959A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229328A (en) * | 1990-10-24 | 1993-07-20 | International Business Machines Corporation | Method for bonding dielectric mounted conductors to semiconductor chip contact pads |
| US5233221A (en) * | 1990-10-24 | 1993-08-03 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
| US5572068A (en) * | 1991-05-11 | 1996-11-05 | Goldstar Electron Co., Inc. | Integrated double-chip semiconductor package and method for fabricating same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5512791A (en) * | 1978-07-14 | 1980-01-29 | Nec Corp | Semiconductor device |
-
1981
- 1981-10-19 JP JP16745881A patent/JPS5868959A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5512791A (en) * | 1978-07-14 | 1980-01-29 | Nec Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229328A (en) * | 1990-10-24 | 1993-07-20 | International Business Machines Corporation | Method for bonding dielectric mounted conductors to semiconductor chip contact pads |
| US5233221A (en) * | 1990-10-24 | 1993-08-03 | International Business Machines Corporation | Electronic substrate multiple location conductor attachment technology |
| US5572068A (en) * | 1991-05-11 | 1996-11-05 | Goldstar Electron Co., Inc. | Integrated double-chip semiconductor package and method for fabricating same |
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