JPS5866498U - Telemeter device - Google Patents

Telemeter device

Info

Publication number
JPS5866498U
JPS5866498U JP16103981U JP16103981U JPS5866498U JP S5866498 U JPS5866498 U JP S5866498U JP 16103981 U JP16103981 U JP 16103981U JP 16103981 U JP16103981 U JP 16103981U JP S5866498 U JPS5866498 U JP S5866498U
Authority
JP
Japan
Prior art keywords
telemeter device
inspection
converter
time
telemeter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16103981U
Other languages
Japanese (ja)
Inventor
天内 紀元
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP16103981U priority Critical patent/JPS5866498U/en
Publication of JPS5866498U publication Critical patent/JPS5866498U/en
Pending legal-status Critical Current

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  • Selective Calling Equipment (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示すブ冶ツク図、第2図は、
第1図の装置の動作を示めすタイムチャートである。 2:試験用アナログデータ発生器、3:入力切換回路、
4:マイクロコンピュータ、6:エラー発生回数記憶回
路、7:出力回路。
Fig. 1 is a block diagram showing an embodiment of the present invention, and Fig. 2 is a block diagram showing an embodiment of the present invention.
2 is a time chart showing the operation of the apparatus shown in FIG. 1; 2: Test analog data generator, 3: Input switching circuit,
4: Microcomputer, 6: Error occurrence count memory circuit, 7: Output circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ゛ テレメータ装置において定時計測時間以外の空き時
間に、あらかじめ定めたアナログ値の試験用データをA
/D変換器に加え、マイクロコンピュータ制御により連
続的にA/D変換器の機能を監視し許容値範囲外のエラ
ー発生回数を記憶するとともに保守点検の際規定の偏差
値にあるか否かを検定することを特徴とする自己点検方
式テレメータ装置。
゛ During free time other than the regular measurement time on the telemeter device, test data of predetermined analog values are sent to A.
In addition to the A/D converter, the function of the A/D converter is continuously monitored by microcomputer control, and the number of errors outside the tolerance range is memorized, and at the time of maintenance and inspection, it is checked whether or not the deviation is within the specified deviation value. A self-inspection telemeter device characterized by verification.
JP16103981U 1981-10-30 1981-10-30 Telemeter device Pending JPS5866498U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16103981U JPS5866498U (en) 1981-10-30 1981-10-30 Telemeter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16103981U JPS5866498U (en) 1981-10-30 1981-10-30 Telemeter device

Publications (1)

Publication Number Publication Date
JPS5866498U true JPS5866498U (en) 1983-05-06

Family

ID=29953420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16103981U Pending JPS5866498U (en) 1981-10-30 1981-10-30 Telemeter device

Country Status (1)

Country Link
JP (1) JPS5866498U (en)

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