JPH03104236U - - Google Patents
Info
- Publication number
- JPH03104236U JPH03104236U JP1070790U JP1070790U JPH03104236U JP H03104236 U JPH03104236 U JP H03104236U JP 1070790 U JP1070790 U JP 1070790U JP 1070790 U JP1070790 U JP 1070790U JP H03104236 U JPH03104236 U JP H03104236U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- detection circuit
- test device
- transmitted data
- memory element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
Description
第１図はこの考案の一実施例によるパリテイ検
出回路の試験回路構成図、第２図はこの考案の他
の実施例を示すパリテイ検出回路の試験回路構成
図、第３図は従来のパリテイ検出回路の試験回路
構成図である。
図において、１……パリテイエラー生起値設定
レジスタ、２……入力バツフア、３……比較制御
回路、４……パリテイビツト反転素子、５……出
力バツフア、６……パリテイエラー生起値設定Ｒ
ＡＭ、７……パリテイエラー設定回路である。な
お、図中、同一符号は同一、又は相当部分を示す
。
Fig. 1 is a test circuit configuration diagram of a parity detection circuit according to one embodiment of this invention, Fig. 2 is a test circuit diagram of a parity detection circuit showing another embodiment of this invention, and Fig. 3 is a conventional parity detection circuit diagram. It is a test circuit configuration diagram of a circuit. In the figure, 1... Parity error occurrence value setting register, 2... Input buffer, 3... Comparison control circuit, 4... Parity bit inversion element, 5... Output buffer, 6... Parity error occurrence value setting R.
AM, 7... Parity error setting circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
て、パリテイエラーを生起させるパターンを格納
する記憶素子と、その記憶素子の内容と伝送デー
タを比較し制御する比較制御回路と伝送データの
パリテイビツトを反転する素子と入出力のバツフ
アを備えた瞬時的なパリテイエラーの発生試験を
可能にしたことを特徴とするパリテイ検出回路の
試験装置。 A test device that tests a parity detection circuit includes a memory element that stores a pattern that causes a parity error, a comparison control circuit that compares and controls the contents of the memory element and transmitted data, and an element that inverts the parity bit of the transmitted data. A test device for a parity detection circuit, characterized in that it is capable of testing the occurrence of an instantaneous parity error with an input/output buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1070790U JPH03104236U (en) | 1990-02-06 | 1990-02-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1070790U JPH03104236U (en) | 1990-02-06 | 1990-02-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104236U true JPH03104236U (en) | 1991-10-29 |
Family
ID=31514265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1070790U Pending JPH03104236U (en) | 1990-02-06 | 1990-02-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104236U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010044490A (en) * | 2008-08-11 | 2010-02-25 | Alps Electric Co Ltd | Multi-directional input device |
-
1990
- 1990-02-06 JP JP1070790U patent/JPH03104236U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010044490A (en) * | 2008-08-11 | 2010-02-25 | Alps Electric Co Ltd | Multi-directional input device |
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