JPS5866198A - Microcomputer resetting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer reset path for a total of 11 units using a microcomputer.

Measuring instruments that use micro-computers have stopped working due to the effects of noise and other factors. There is a membership fee to take measures for such cases, and the conventional structure is as shown in Figure 1. That is, a microphone built into the measuring instrument 10 has four processors (microcomputers; hereinafter referred to as single K).
The output of the CPU (U) 11 is transmitted to other devices via the output circuit 12, and the repetitive pulse B from the CPU II is transmitted to other devices via the output circuit 12.
P is input to the counter 13 as a reset signal. Then, the counter 13 counts the positive pulse CP from the outside and supplies it to the OR gate 14, and also supplies the reset signal R8 from the reset circuit 15 to the OR gate 14, so that the reset signal R8 output from the OR gate 14 is When the power is turned on, a reset signal R8 is outputted from the power supply reset circuit 15, and a reset signal RF is inputted to the CPUIIK via the OR gate 14, thereby resetting the CPUII. In addition, during normal operation, the counter 13 is reset by the repeated pulse RP before the counter 13 overflows depending on the number of clock pulses CP, so the output RPB of the counter 13 is always at the rLJ level. There is. therefore,
In this case, the reset signal RF from the OR gate 14 is also at the rLJ level, and the CPU 11 is not reset. However, when the CPU II stops, the repetitive pulse RP is not output, so the counter 13 counts the clock pulse CP and overflows, and the output RPB
Since the conventional reset method does not have a CPU II failure determination function, it has the disadvantage that even if the CPU II actually fails, it cannot easily detect the abnormality. be. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a microcomputer reset circuit that does not have the above-mentioned drawbacks.

This invention is established below.

The present invention relates to an i-microcomputer reset circuit for resetting a microcomputer when the power is turned on or restarted, and as shown in FIG.
Even if the occurrence time of the CPU elapses after the predetermined setting time, the CPU
The alarm signal AL is outputted to perform an alarm operation only when II is not restarted = 1L. Therefore, the pulse generator circuit is composed of a retriggerable monostable multivibrator (hereinafter simply referred to as monostable multi) 21 and a stable multivibrator η, and the monostable multivibrator 21 receives repeated pulses from the CPU II. RP is input as a trigger pulse, and the Q output signal RM of the monostable multi 21 and the clock pulse CP are input to the monostable multi 22 as a trigger. In addition, the time measurement circuit (9) receives the monostable multi input DW7 which is triggered by the Q output signal RM of the monostable multi 21.
It is composed of 0 tsubu after. Then, the Q output of the flip-flop is determined with reference to the time chart.

First, during normal operation, from CPU II to Figure 3 (A) VC
A repetitive pulse RP as shown is output, which triggers the retriggerable monostable multi 21, so that its output KM is at the rHJ level (FIG. 3(B)). However, since the monostable i-rute η is triggered when the signal voltage is at the rLJ level and the clock pulse CP is at the rHJ level, it is in a non-triggered state during normal operation, and its output RPB is at the rLJ level. CPU II is never reset. In addition, in the monostable multi 31, when the signal RM changes from the "I(" level V to the "L" level) and the C'PUII stops, the periodic repetitive pulses R and P disappear. Do not input a trigger to the triggerable monostable multi 21 for a period longer than its pulse width (and set the Q output signal KM to [L] level at time 11).
When the signal decoy becomes rLJ level, the monostable multi 31 is triggered, and its Q output signal RT becomes I'll level (FIGS. 3(B) and (G)). On the other hand, in the monostable multi n, after the signal RM becomes the [IL, ) level, when the clock pulse CP becomes the j'l-i J level (
At time point "2)K)9", while the temporary signal RT is at the rLJ level, the clock pulse RFB synchronized with the clock pulse CPK is output (Fig. 3 (H), (C), (
D) ). Then, this pulse R1'H is OR gate 1
4 and is input to the CPU 11 as a reset pulse RF, and the CPU 11 is reset. However, the CPU
If a predetermined period of time passes without II restarting and the Q output signal RT of the monostable multi 31 reaches the rHJ level (
Time point 13) The flip-flop is turned off, and the alarm signal AL is output from its Q output (31st W (El, (
to)). Note that the output signal RT of the monostable multi 31 is r
If the CPU II restarts before reaching the HJ level, the monostable multi-2
1 is triggered and its output KM becomes If-IJ level, and the rLJ level signal is input to the D terminal through the inverter, so the output RT of the monostable multi 31
4 shows another embodiment of the present invention.
It is shown in correspondence with FIG.
It consists of a counter (A) and a flip-flop (A). In addition, counter] 3 and opening repetition pulse R
, P. In this configuration, when the CPU II is stopped and the reset pulse RPB is output from the counter 13, the CPTJII is reset via the OR gate 14, and the counter counts the number of times. Do 1. Therefore, the reset pulse) (P
If B (T(, F ) is applied to the CPU 108 a predetermined number of times, it does not restart (), then the counter overflows and sets the flip-flop. Thus,
Flip-flops are used to notify the outside of an abnormality, but what kind of output state is desirable at the time of an abnormality depends on how the measurement gain is used.

An example of how this is applied to measurement when a microcomputer malfunctions is as shown in Figure 5.
- 101 is an excitation coil of the electromagnetic flow needle, 102 is a conduit, and in this example, the excitation coil 101 is connected to the fluid flow direction in the conduit 102 and the electrode 103m in the conduit 102, 1
03b is arranged so as to generate a magnetic field perpendicular to the mounting direction. 104 and 105 are buffer amplifiers with high input impedance, respectively, 106 is a differential amplifier equipped with an external resistor R1 to L4 for removing common mode noise, 107 is an AD converter with a sampling function, and 10
8 is a microprocessor (CPU), 109 is a CPU
108 is connected to a memory (RoM/RAM) by a data bus 110 and an address bus 111, 112 is an input/output port, 113 is an input/output port (113 is an input/output port), data information from 112 is converted to A, and the final output is V. is the DA conversion profit, and the above-mentioned 4ychi FIN, 5w1-b, 1M2-,, FM, -bi
These switches SW, a to 5w2-
b is a mink in which a rectangular wave-shaped excitation current flows through the excitation coiler 101, with one cycle consisting of four periods: positive, zero, negative, and zero (AI)
The data sampled by converter 107 and digitized is stored in memory 109 . and,
CPIJlog outputs sample values of flow rate signals by sequentially performing calculations on a set of four consecutive data while updating the data one by one on these data obtained in time series in the memory 109. The calculation formula differs depending on which period of the excitation cycle the first one of the four data is from.If the sampling data at each timing t1 to t7 is expressed as ■, ~■7, ■, positive Data in the excitation period ■When starting from 1:■. 1=-v,
+3V2- av, +v, ・Between songs (1) ■
, Data in a zero pause period starting from ■, which immediately follows: Vo! =V, -V3-V4+V, -...
...-(2) ■, data in the negative excitation period starts from ■: ■. 3=v, -av4+sv, -v,
...This becomes song (3).

Here, the CPU 108 repeatedly performs the calculations of the above equations (1) to (4) in order every time the data is updated, and usually calculates the calculated value (2) each time each equation is calculated. 1～■o
4 is taken as a sample value of the flow rate signal and outputted through the DA converter 113. If such arithmetic processing is performed every time data is updated, the response characteristics will become extremely fast.

For this normal sample value output, the CPU 10 in this example
8 sequentially compares each sample value with the previous sample value,
The difference is 1■. 4 '0111 l■ot'. 81
゜1■02 'oat or I■03 'o41 is thicker than a predetermined value (・If the value is larger than the predetermined value, the sudden change detection function determines that a sudden change has occurred in the electrochemical DC noise. In this case, for the three subsequent sample values including the sample value at that time, the value obtained by cumulatively adding V (appropriate change) to the sample value immediately before the sudden change is output as a substitute, and from the fourth time onwards, the above Based on the information preset by the calculations of equations (1) to (4), control is performed to maintain the positive end, the negative end, or the current value.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional microcomputer reset circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3(A) to (G) are examples of its operation. FIG. 4 is a block configuration diagram showing another embodiment of the present invention, and FIG. 5 is a configuration diagram when the present invention is applied to an electromagnetic flowmeter. lO...Measuring instrument, 11...CPU (microcomputer, microprocessor), 12...Output circuit, 13.34...Counter, 14...OR gate,
15...Power supply reset circuit, addition...pulse generation circuit, I...time measurement circuit.

Claims (1)

[Claims] In a circuit for resetting a microcomputer when the power is turned on or restarted, a pulse generation circuit repeatedly generates a pulse to restart the microcomputer when the microcomputer is stopped, and the time during which the pulse is generated is measured. 41-, the microcomputer reset comprises a time measuring circuit for detecting the pulse generation time, and performs an alarm operation only when the microcomputer does not restart even after the pulse generation time has passed a predetermined set time. circuit.