JPS586611A - Generating circuit for switching control signal - Google Patents

Abstract

PURPOSE:To manage with only one control signal input terminal for switching types of noise reduction, by putting a circuit in three kinds of operation in accordance with a ternary input signal. CONSTITUTION:The reference voltage VREF developed at a connection point J2 is equal to the potential obtained by dividing a power voltage through resistances R1 and R2. The base potential of a transistor (TR) Q1 is a voltage VREF+VBE the voltage VBE of a diode D1 higher than the voltage VREF. The base potential of a TRQ3 is a voltage VREF-3VBE the 3VREF of three diodes lower than the VREF. A switching control signal VS is supplied to the base terminal of a TRQ2. When the VS is nearly equal to the power voltage, the base potential of the TRQ2 is VREF+2VBE and higher than the base potential of the TRQ1, so the TRQ1 turns off and the TRQ2 turns on to generate a control signal (c), placing a noise reduction circuit in mode (c). When the VS is as high as the VREF, the TRQ1 turns on and the TRQ2 turns off to generate a control signal (b).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a switching control system that controls switching of circuit constants, etc., and supplies a switching control signal necessary for performing switching control to a plurality of circuits configured to perform mutually different actions. Related to signal generation circuits.

pander) circuits are increasingly being built into tape recorders. Such a compander circuit operates in the noise g operation mode (hereinafter referred to as B) according to the B type Dolby system.
Abbreviated as mode. ) compresses and expands mid-high frequency components to achieve a noise reduction effect of up to 10 dB.
It is abbreviated as lower C mode. ), the middle and high frequency components are compressed and expanded without a noise reduction effect of up to 20 dB, and in the noise reduction operation stop mode (hereinafter abbreviated as off mode), the input signal is linearly amplified and output.

In a circuit having three or more operation modes, such as a compander circuit, multiple switching control signals are required, and the number of input/output terminals of the circuit must be increased, making it difficult to integrate the circuit. .

An object of the present invention is to provide a switching control signal generation circuit that can reduce the number of input/output terminals in the entire circuit by generating a plurality of switching control signals in response to a switching command signal supplied to a single input terminal. It is to provide.

The switching control signal generation circuit according to the present invention is configured to generate a plurality of switching control signals corresponding to each of the three input terminal levels of a single human input signal: high level, low level, and intermediate level.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, a human input signal is supplied to an SS (spectral skewing) circuit 2 included in an encoder section 1 of a compander circuit in a Dolby system. S.S.
In the circuit 2, the input signal is directly supplied to one input terminal of the two-power output switch amplifier 3. The other input terminal of switch amplifier 3 has a center frequency of approximately 20 KI (
The input signal is supplied through two band rejection filters 4. The output of the switch amplifier 3 is supplied to an adder 5, and is also supplied to the sub-signal path 6 of (1) and (S). ) [, the output of the switch amplifier 3 in the sub-signal path 6 of
The signal is supplied to the variable impedance circuit 8 via the circuit 8, and is attenuated to a level corresponding to the human power impedance of the variable impedance circuit 8, and then supplied to the amplifier 9. Amplifier 9
The output of is supplied to the detector 10 and also to the O8 (overshoot suppression) circuit 11. The output of the wave detector 10 is supplied to a control current generation circuit 12. The control current generating circuit 12 supplies a control current according to the output of the wave detector 10 to the variable impedance circuit 8 to change the manual impedance of the variable impedance circuit 8. Further, a constant current source 13 is connected to the variable impedance circuit 8 via a switching element 14 to make the control current of the variable impedance circuit 8 excessively large and to make the human power impedance extremely small.
is connected to the control current input terminal of the

Then, the output of the O8 circuit 11 is supplied to the adder 5 as the output of the sub-signal path 6 of the hole S, and added to the output of the switch amplifier 3.

The output of the adder 5 is sent to the As (saturation prevention) circuit 15 and LL.
The signal is supplied to the sub signal path 16 of S. In the As circuit 15, the output of the adder 5 is also supplied to one input terminal of the switch amplifier F. The output of the adder 5 is supplied to the other input terminal of the switch amplifier 17 via a filter 18. The filter 18 has a frequency characteristic in which the amount of signal attenuation increases in the high frequency range in accordance with the characteristic of the tape in which the recording frequency characteristic decreases at the higher end as the recording level increases. The sub signal path 16 of LLS is HL
Similarly to the sub-signal path 6 of S, a high-pass filter 19. Variable impedance circuit 20. Amplifier 21. Detector 22, O8 circuit 23. Control current generation circuit 24. It is composed of a constant current source 25 and a switching element 26. and O8 circuit 2
The output of adder 2 is output from adder 2 as the output of sub-signal path 16 of LLS.
7 and is added to the output of the A8 circuit 15 to form the encoder output'.

The encoder output is supplied to the deck 28 as a recording signal to the supply encoder 29. The reproduced output from the decoder 29 is supplied to an adder 30. The output of adder 30 is output. LL
The output of the S sub-signal path 16' is supplied to an adder 30 and summed with the reproduced output. The output of the adder 32 is passed through the inverter 33 to the HLS sub-signal path 6' and the SS circuit 2'.
supplied to Output of HLS sub-signal path 6' - Threat 1-
one! The 1+ power is supplied to adder 34 and summed with the output of As circuit 15'. The output of the SS circuit 2' is then supplied to an amplifier (not shown) as a decoder output.

In addition, HLS sub-signal path 6.6', LIJS sub-signal path 1
6 and 16' have similar configurations, and 89
The circuit 2°2' and the As circuits 15 and 15' each have opposite frequency characteristics.

On the other hand, a switching control signal generation circuit 34 is provided which generates an off mode control signal α, a B mode control signal S, and a C mode control signal C as switching control signals to switch and control the operation modes of the encoder 1 and decoder 29. ing. In the switching control signal generation circuit 34, resistors RI, diodes D, D2. A resistor R2 is connected in series. The base of the first transistor Q is connected to the series connection point J between the resistor R1 and the diode D. First transistor Q and second transistor Q
2 form a true 1 differential pair 35. Reference voltage VR generated at the series connection point J2 of diodes D and D2
A diode D3.EF is connected in series in the forward direction. D...
It is supplied to the base of the third transistor Q through D. A second differential pair 36 is formed by the third transistor Q3 and the fourth transistor Q4. Also, the resistance R
, , R2, the diode D, and so on form a constant pressure generating means 37. The collector of transistor Q4 is connected to the common emitter connection point of transistors Q, ,Q. A constant current source ■ is connected between the common connection point of the transistors Q, , Q, and the ground, and the transistor Q, , Q2.
For example, a constant current source I2 . I
3.1. are connected to each other. tiger 1 transistor q2
A human power signal s for switching control is supplied to the base of the switch via a resistor R3. Tora 1 Jistar Q2. A diode D6.Q is connected between the bases of each of D6. D7 are connected in series in the forward direction. Further, a diode D8. The diodes D1o and DII are connected in series in the opposite direction such that the diodes D1 and D are connected in series in the forward direction and in parallel with them. Input voltage conversion means 38 is formed by these resistor R8 and diodes D6 to DI. And transistors Q, , Q2.
A B-mode control signal S, a C-mode control signal C, and an off-mode control signal α are output from the respective collectors of Q, . is supplied to one control input terminal of the switch amplifier 3 and the switching element 26 via each of the OR circuits 39, 40, and 41.
and one control input terminal of the switch amplifier 17, respectively. Furthermore, off mode control signal α
are also supplied to corresponding sections (not shown) of the decoder section 29. The B mode control signal is the sub signal path 6 of ITLS.
Filter 7° detector 10. The signal is supplied to the O8 circuit 11 and also to one control input terminal of the switch amplifier 3, the control input terminal of the switching element 26, and one control input terminal of the switch amplifier 17 via each of the OR circuits 39, 40, 41. Supplied. Further, the B-mode control signal is supplied to corresponding sections (not shown) of the SUMO decoder section 29. The C mode control signal C is the As circuit 1.
Switch amplifiers 17 and 3 in each of the 5° SS circuits 2
, the control input terminal of the control current generation circuit 12 in the sub-signal path 6 of the HLS, and the decoder section 2
9 (not shown).

In the above configuration, the reference voltage ' generated at the connection point J2
REF is equal to the potential obtained by dividing the power supply voltage +Vcc by resistors Ft, . And transistor Q1
The potential of the base of is the reference voltage REF and the diode D1.
The first predetermined potential ('REF
+■BE). Similarly, the pace potential of the transistor Q3 becomes a second predetermined potential (VREF 3 vBE) lower than the reference voltage REF by 3VBE. Now, when the potential of the human input signal 8 for switching control becomes almost equal to +cc and the C mode is commanded, the transistor Q
The potential of the base of 2 is (VREF + 2 vBE)
Also, the potential of the base of the transistor QQ becomes equal to the reference voltage VRF,F. Then, in the first differential pair 35, the base potential of the transistor Q2 becomes higher than the base potential of the transistor Q1, so that the transistor Q1 is turned off and the transistor Q2 is turned on. Also,
In the second differential pair 36, the transistor Q3 is turned off and the transistor Q4 is turned on, so that, for example, if I3 and ■ are set equal, a C mode control signal C consisting of a no-current signal is output from the collector of the transistor Q2. Output. A constant current source I2. is connected from the collector of the transistor Q, , O3. A constant current is output by each of I, and control signals α and b consisting of off-mode and B-mode no-current signals are not output. In response to the C mode control signal C, the control current generating circuit 12 changes the circuit constants, etc. so that it generates, for example, twice as much control current as in the B mode and supplies it to the variable impedance element 8. In addition, switch amplifiers 3 and 1
Each of the filters 4 and 18 performs manual switching of the stages.
Selectively output each output. As a result, the low-level mid-high frequency components of the human input signal are amplified in the sub-signal path 6 of the HLS, and then added to the original human input signal by the adder 5, thereby compressing the human input signal by a maximum of 1 odB.

Even lower levels of this compressed human signal in the mid-high range''
The human input signal is compressed by a total of 20 dB by amplifying the component in the sub-signal path 16 of the LLS, and becomes the encoder output.

The above switching control is also performed in the decoder section 29, and the encoder section 1. The decoder section 29 is both in the C mode, and a maximum noise of 20 dB due to compression/expansion of middle and high frequency components is performed.

Next, when the level of the human input signal 8 for switching control becomes almost equal to the level of the reference voltage REF and the B mode is commanded, the base potential of the transistor Q2 becomes equal to the level of the reference voltage VREF, and the transistor The potential of the base of Q4 becomes (VREF "vBE). Then, in the first differential pair 35, the transistor Q
1 is on and transistor Q2 is off. Also, the second
In the differential pair 36, transistor Q3 is off and transistor Q is on, and if, for example, I2 and 11 are set equal, the B-mode control signal consisting of a no-current signal is output from the collector of transistor Q. be done.

Transistor Q2. Constant current source I8 is connected from the collector of Q3.
．． A constant current is output by each of I, and control signals a and C consisting of off-mode and C-mode no-current signals are no longer output. The switching element 26 in the sub-signal path 16 of the LLS is turned on by the B-mode control signal, and the control current in the variable impedance element 20 becomes excessive, and the human power impedance of the variable impedance element 20 becomes an extremely small value of, for example, several tens of ohms. teLLS
The effect of enhancing the low-level middle and high frequency components in the sub-signal path 16 is eliminated. Further, the circuit constants of the filter 7 in the sub-signal path 6 of the HLS, the time constant circuit of the detector 10, and the O8 circuit 11 are switched and changed. At the same time, S
S circuit 2. In the As circuit 15, the switch amplifier 3,
The Ω input stages of each of the input terminals 17 are switched so that the signal supplied to one input terminal, that is, the signal input directly without going through the filters 4 and 18, is selectively output. As a result, only the low-level mid-to-high frequency components in the sub-signal path 6 of the TLS are enhanced, and the human signal is compressed by a maximum of 10 dB and delivered to the encoder output.

The above switching control is also performed in the decoder section 29, so that both the encoder section 1 and the decoder section 29 enter the B mode, and perform a maximum xodB noise reduction operation by compressing and expanding mid-high frequency components.

Next, when the level of the human power signal ■8 for switching control becomes almost zero and off mode is commanded, the transistor Q2
．． The level of each base of Q4 is (■REF-
2■BE), (VREF4VBE). Then, in the first differential pair 35, the transistor Q1 is turned on and the transistor Q2 is turned off. In addition, in the second differential pair 36, if the transistor Q3 is turned on and the transistor Q4 is turned off, for example, if I4 and I are set equal, only the off mode control signal α consisting of a no-current signal is It is output from the collector of transistor Q3. This off-mode control signal α causes the HLS sub-signal path 6. Each of the switching elements 14 and 26 in each of the sub-signal paths 16 of the LLS are both turned on, and the human power impedance of each variable impedance element 8, 200 becomes an extremely small value, and the switching elements 14 and 26 in each of the sub-signal paths 16 of the HLS are turned on. LL
The effect of enhancing the low-level middle and high frequency components in each of the S sub-signal paths 16 is eliminated. Also, SS circuit 2. As times °
In path 15, the input stages of switch ups 3 and 17 are switched so that directly input signals are selectively output without passing through filters 4 and 18.

The above switching control is also performed in the decoder section 29, so that both the encoder section 1 and the decoder section 29 are in the off mode, and no noise reduction operation is performed.

In the circuit example of FIG. 1, the switching control signal generation circuit 34
If a capacitor is connected between the connection point J2 and the ground to prevent fluctuations in the reference voltage VRgp', when the power is turned on and the power supply terminal VCC rises, the reference voltage V
REF will rise with a time constant determined by resistor R1 and the capacitor.

For this reason, a state may occur in which the level of the base of transistor Q3 is lower than the level in the steady state immediately after the power is turned on, and a state in which none of the mode control signals α, b, and c is outputted may occur.

Then, since each of the switch amplifiers 3 and 17 is configured to be controlled by one of the control signals α, b, and c, the control signals a and b are used.

When either of C starts to be supplied, switch amplifier 3,
17 suddenly turns from off to on, and the DC voltage of its output goes from - to +Vcc, through a process of 10Vco, and then shifts to the midpoint potential. In this process, problems such as click noise occur in the encoder output.

Therefore, an example of a circuit that prevents the occurrence of the problem shown in FIG. 2 will be shown. In FIG. 2, only the switching control signal generating circuit 34 is shown, and the encoder section 1° deck 28. The decoder section 29 is omitted because it has the same configuration as in FIG. 1. In the switching control signal generation circuit 34, differential pairs 35, 36 . Constant voltage generation means 37. The input terminal conversion means 38 is connected in the same manner as in FIG. However, in this example, the connection point J in the constant voltage generation circuit 37
A VRIJ fluctuation prevention code C is connected between 2 and ground. Also, resistors R, , R2, diodes DI, D
2. D3. In addition to the voltage generating circuit constituted by D4, another voltage generating circuit 42 is provided. This voltage generation circuit 42 consists of a constant current source ■ whose current sink terminal is connected to the power supply +■oc, and a constant voltage diode whose cathode is connected to the current discharge terminal of the constant current source I and whose anode is grounded. It consists of D2. Furthermore, a diode D1□ is connected in the forward direction between the cathode of the constant voltage diode Dz and the base of the transistor Q3. Incidentally, the Zener voltage (2) of the constant voltage diode D2 is, for example, (2) when the reference voltage (2)REF is in a steady state. C/
2 so that the resistance E11. When the resistance value of R2 is set, the voltage is sufficiently close to (■oc/-2■BE) in a range lower than (■oc/2-2■13E).

In this configuration, when the power is turned on and the power supply voltage rises to Vcc, the potential of the base of the transistor Q3 instantaneously changes to (Vcc).
z-VBE) and the potential at steady state (■CC/
2 3 VBE) in the lower range (■cc/2
-3VBE). Therefore, the mode control signal a is instantaneously outputted immediately after the power is turned on, and the switch amplifiers 3 and 17 shown in FIG. 1 are turned on immediately, thereby preventing the occurrence of click noise in the encoder output. Also, in steady state, the potential of the base of transistor Q3 is (Vcc/2-3VBE)
As a result, the diodes D and 2 are turned off, and the output voltage of the voltage generating circuit 42, which may fluctuate because there is no power storage means between the output terminal and the ground, is not supplied to the base of the transistor Q3. A stable operation can be obtained.

Incidentally, in the description of the above embodiment, the mode control signal a.

h, cFi is assumed to consist of a no-current signal, but conversely, the mode control signal α is assumed to be a state in which current exists in the form of inflow or outflow during each mode.

b, c, and in such a case, for example, the transistors Q, , Q2 . Connected to the collector of Q3 ■2. By connecting so-called current mirror circuits to each of them in place of the constant current sources I31-4, it is possible to treat the current output of these mirror circuits as mode control signals α, b, and c.

As described in detail above, the switching control signal generation circuit according to the present invention is configured to generate switching control signals in response to each of three different states of a single human input signal, so that the switching control signal generating circuit according to the present invention is configured to generate switching control signals in accordance with each of three different states of a single human input signal. This allows the number of input/output terminals of the entire circuit to be reduced.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing embodiments of the present invention, respectively. Explanation of symbols of main parts 35. 36... Differential pair 37... Constant voltage generation means 38... Input terminal conversion means

Claims (3)

[Claims] (1) A first differential pair consisting of a first and a second transistor, and a second differential pair consisting of a third and fourth transistor and supplying the current flowing through the third and fourth transistors to the second transistor. , constant voltage generating means that sets the potential at the control input terminal of the first and third transistors to first and second predetermined potentials, respectively; The potential at the control input terminal of the second transistor is approximately equal to the input voltage, or higher than the first predetermined potential by a first predetermined voltage, or lower than the first predetermined potential by a first predetermined voltage, and the potential at the control input terminal of the second transistor is set to the first predetermined voltage. input terminal converting means for converting the potential at the control input terminals of the first and fourth transistors to a potential lower by a second predetermined voltage than the potential at the control input terminals of the first and fourth transistors; Second. Third
and a switching control signal generating circuit that generates a switching control signal according to the state of each of the fourth transistors. (2) The constant voltage generating means includes a voltage dividing circuit connected between two predetermined potential points having mutually different tn% levels, and applies a voltage corresponding to the output voltage of the voltage dividing circuit to the first and second voltage points. 3
2. The switching control signal generating circuit according to claim 1, wherein the switching control signal generating circuit is supplied to a base of a transistor. (3) The constant voltage generating means is connected between two voltage generating circuits whose output voltages are slightly different from each other, an output terminal of one of the two voltage generating circuits having a lower output voltage, and a predetermined potential point. a power storage means, the output voltage of each of the two voltage generating circuits is passed through a rectifying element, and then the output voltage of the third voltage generating circuit is
The switching control signal generating circuit 0(4) according to claim 1, characterized in that the switching control signal generating circuit 0(4) is supplied to the base of the transistor.
a first differential pair consisting of first and second transistors, and a third
and a fourth transistor, and a second differential pair that supplies the current flowing through the third and fourth transistors to the second transistor; 2 constant voltage generating means for setting a predetermined potential to a control input terminal of the fourth transistor; input terminal converting means for setting the potential at a first predetermined voltage lower than the first predetermined potential and for setting the potential at the control input terminal of the second transistor to a potential lower by a second predetermined voltage than the potential at the control input terminal of the fourth transistor; A compander circuit that can control switching of circuit constants, etc. using a switching control signal, and perform various operations such as stopping noise reduction operation, noise reduction operation using a B-type Dolby system, and noise reduction operation using a C-type Dolby system. Said 1st and 2nd. A switching control signal generating circuit characterized in that the switching control signal is supplied according to the states of each of the third and fourth transistors.