JPS586631A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To decrease the number of input and output terminals by generating the 1st and 2nd switching signals when a single control input signal enters into a prescribed state, and performing switching control. CONSTITUTION:A Dolby encoder 1 which is placed in mode B, mode C and off mode by the 1st, 2nd and 3rd switching control signals (a), (b) and (c) respectively consists of a spectral skewing (SS) circuit 2, subsidiary signals paths 6 and 16 for HLS and LLS, and a saturation preventing circuit 15. A recording input signal inputted to the SS circuit 2 is applied through the encoder 1 to a deck 28, whose playback signal is outputted through a decoder 29. According to the potential relation between the reference voltage at a connection point J2 and a control input signal voltage VS, a switching control signal generating circuit 34 generates the switching control signals (a), (b) and (c) to place the encoder in prescribed mode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit that can be used in both B-type and C-type Dolby system noise reduction systems, and can also stop the noise reduction operation.

In the B-type Dolby system noise reduction operation mode (hereinafter abbreviated as B mode), this noise reduction circuit compresses and expands mid-high frequency components to a maximum of 1 odB.
This is a noise reduction operation mode using the C type Dolby system (hereinafter abbreviated as C mode).
In this case, the mid-high frequency components are compressed and expanded to a maximum of 20d.
In the noise reduction operation stop mode (hereinafter abbreviated as off mode), the input signal is linearly amplified and output. In such a noise reduction circuit having three operation modes, multiple switching control signals are required to control switching of circuit constants of each part, and the number of input/output terminals of the circuit increases, making it difficult to integrate the circuit. An inconvenience occurs.

Therefore, development is underway of a noise reduction circuit with a small number of input/output terminals, which is equipped with a switching control signal generation circuit that outputs a plurality of switching control signals supplied to each part according to the state of a single input signal. In the process of such development, an increase in circuit scale due to the provision of a switching control signal sometimes became a problem.

Therefore, an object of the present invention is to provide a noise reduction circuit that has the above three operation modes, has a small number of input/output terminals, and has a small circuit scale.

The noise reduction circuit according to the present invention has the following features: 1. Second. The compander circuit is provided with a compander circuit that becomes each operation mode of B mode, C mode, and off mode in response to a third switching control signal, and when a single control input signal becomes a first predetermined state, the first. Both of the second switching control signals are supplied to the compander circuit, and the control input signal is the second switching control signal. When each of the third predetermined states is reached, the second. The third switching control signal is configured to supply each of the third switching control signals to the compander circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In the figure, the recording input signal is included in the encoder section 1 of the compander circuit in the Dolby system.
(spectral skewing) circuit 2. In the SS circuit 2, the recording input signal is directly supplied to one input terminal of a two-man power, one-output switch amplifier 3.

A recording input signal is supplied to the other input terminal of the switch amplifier 3 via a band rejection filter 4 having a center frequency of about 20 KH2. The output of the switch amplifier 3 is supplied to an adder 5 and also to a sub-signal path 6 of the HLS.

In the sub-signal path 6 of the HLS, the output of the switch amplifier 3 is supplied to a variable impedance circuit 8 via a high-pass filter 7, and after being attenuated to a level corresponding to the input impedance of the variable impedance circuit 8, it is supplied to an amplifier 9. Ru. The output of the amplifier 9 is supplied to a detector lO and also to an O8 (overshoot suppression) circuit 11.

The output of the wave detector 10 is supplied to a control current generation circuit 12. The control current generation circuit 12 supplies a control current according to the output of the wave detector 10 to the variable impedance circuit 8 to change the input impedance of the variable impedance circuit 8.

Further, a constant current source 13 is connected to a control current input terminal of the variable impedance circuit 80 via a switching element 14 to make the input impedance extremely small by increasing the control current of the variable impedance circuit 8 . The output of the O8 circuit 11 is then supplied to the adder 5 as the output of the sub-signal path 6 of the HLS and added to the output of the switch amplifier 3.

The output of the adder 5 is connected to the As (saturation prevention) circuit 15 and the L
The signal is supplied to the sub signal path 16 of the LS. In the As circuit 15, the output of the adder 5 is supplied to one input terminal of a switch amplifier 17. The output of the adder 5 is supplied to the other input terminal of the switch amplifier 17 via a filter 18. The filter 18 has a frequency characteristic in which the amount of signal attenuation increases in the high frequency range in accordance with the characteristic of the tape in which the frequency characteristic decreases at the higher end as the recording level increases. The sub-signal path 16 of the LLS is provided with a high-pass filter 19 .similar to the sub-signal path 6 of the HLS. Variable impedance circuit 20, amplifier 21. Detector 22. O8 circuit 2
3. Control current generation circuit 24. It is composed of a constant current source 25 and a switching element 26. The output of the O8 circuit 23 is then supplied to the adder 27 as the output of the sub-signal path 16 of the LLS, where it is added to the output of the As circuit 15 to form an encoder output.

The encoder output is supplied to the deck 28 as a recording signal. The playback output output from the deck 28 is sent to the decoder 29.
supplied to The reproduced output from the decoder 29 is supplied to an adder 30. The output of the adder 30 is sent to the inverter 31
The signal is supplied to the As circuit 15' via.

The output of the AS circuit 15' is supplied to the sub-signal path 16' of the LLS and the adder 32. The output of the sub-signal path 16' of the LLS is supplied to an adder 30 (/C) and added to the reproduced output.
The signal is supplied to the sub signal path 6' and the SS circuit group. The output of the sub-signal path 6' of the HLS is supplied to an adder 34 and added to the output of the AS circuit 15'. And SS circuit 2'
The output is supplied to an amplifier (not shown) as a decoder output. The HLS sub-signal paths 6 and 6' and the LLS sub-signal paths 16 and 16' have similar configurations, and the S
The S circuits 2, 2' and the As circuits 15, 15' have opposite frequency characteristics.

On the other hand, a switching control signal is generated to generate a first switching control signal α, a second switching control signal S, and a third switching control signal C as switching control signals for controlling the switching of the operation modes of the encoder section 1 and the decoder section 29. In the two-switching control signal generation circuit 34 provided with the circuit 34, a resistor R1, a diode D+, , D2, a resistor &
are connected in series. The penis of the transistor Q is connected to the series connection point J+ of the resistor Rt and the diode D1. A differential pair 35 is formed by the transistors Q1°O2. Series connection point J of diodes D and D2
The reference voltage VREF generated at 2 is supplied to the bases of transistors Q, , Q, through diodes D3, D4 and Ds connected in series in the forward direction. transistor Q,
, Q, are connected to each other. Two differential pairs 36 are formed by the transistors Qs and Q and the transistors Qs and Qa whose bases are connected to each other and whose emitters are connected to each other. Transistor Q4
The collectors of the transistors are commonly connected to the collectors of the transistors Q1, and the power supply +VCC is supplied to the collectors of the transistors Q5.

Therefore, the collector of transistor Q6 is transistor Q,
, Q, are connected to the emitter common connection point.

A constant current source 11 is connected between the common connection point of the emitters of the transistor Q3 and the false emitter and ground. Power supply +Vcc and transistor circle, Q2. For example, a constant current source I2. I3. I. are connected to each other.

A switching control input signal V8 is supplied to the base of the transistor q via a resistor R3. Diodes Do and I% are connected in series in the forward direction between the base of the transistor Q2 and the common connection point of the bases of the transistors Q and Qa. Also, the base of transistor Q2 and the reference voltage VR
A diode D8°D is connected in series in the forward direction between the connection points 52, which are EF, and diodes D, , , D, are connected in series in the reverse direction in parallel therewith. Then, a second switching control signal is outputted from the common connection point of the collectors of transistors Q, , O4, and transistors Q2, . The third switching control signal C2 and the first switching control signal α are output from each collector of Qs. Incidentally, a capacitor C is connected between the connection point J2 and the ground in order to prevent the reference voltage vREF from fluctuating.

The first switching control signal α is applied to the control input terminal of the switching element 140 in the sub-signal path 6 of the HLS, the filter 7, the detector 10 . O8 circuit 11. It is supplied to each of one control input terminal of the switch amplifier 3, one control input terminal of the switching element 26, and one control input terminal of the switch amplifier 17. Furthermore, the first switching control signal α is also supplied to corresponding sections (not shown) of the decoder section 29. The second switching control signal S is supplied to the filter 7, the detector IO, and the OS circuit 11 in the sub-signal path 6 of the HLS, and is also supplied to one control input terminal of the switch amplifier 3, the control input terminal of the switching element 26, and the switch amplifier 17 control input terminals. Further, the second switching control signal is supplied to corresponding sections (not shown) of the SUMO decoder section 29. The third switching control signal C is applied to the other input terminal of each of the switch amplifiers 17.3 in each of the As circuits 15 and 88 circuits 2, the control input terminal of the control current generation circuit 12 in the sub-signal path 6 of the HLS, and the decoder section. 29 (not shown).

In the above configuration, the reference voltage v generated at the connection point J2
REF is equal to the potential obtained by dividing the power supply voltage +vcc by resistors R, , R2. Then, the potential of the base of the transistor Q1 is lower than the reference voltage VREF by the diode D.

The first predetermined potential (VREF
+VBE). Similarly, transistor Q3. The potential of the base of QI becomes a second predetermined potential (VREF 3 Vng ) lower by 3 V□ than the reference voltage VREF. now,
When the potential of the switching control input signal vs becomes almost equal to +vcc and the C mode is commanded, the potential of the base of the transistor Q2 becomes (VREF +2 VBE), and the potential of the bases of the transistors Q, Q6 becomes the reference. Voltage VR
The base potential of EF becomes low, turning off transistor Q1 and turning on transistor /O2. Also, in the differential pair 36, transistors Q3. If Q is off and transistors Qs and Qa are on, for example, and (1) are set equal, a third switching control signal C consisting of a no-current signal is output from the collector of transistor Q2. Common collector connection point of transistors Q, ,Q,
A constant current source r2. A constant current is output from each of I4, and switching control signals α and b consisting of the first and second no-current signals are not output. In response to the third switching control signal C, the control current generation circuit 12 generates, for example, twice the control current as in the B mode, and the variable impedance element 8
The circuit constants and the like are changed so that the input signal is supplied to the filters 4 and 1B, and the input stages of the switch amplifiers 3 and 17 are changed to selectively output the outputs of the filters 4 and 1B. As a result, in the sub-signal path 6 of the HLS, the middle and high frequency components of a lower level than the input signal are amplified, and then added to the original input signal by the adder 5, so that the input signal reaches a maximum of 10
dB compression. The lower level middle and high frequency components of this compressed input signal are amplified in the sub signal path 16 of the LLS, whereby the input signal is compressed by a total of 20 dB and sent to the encoder.

This becomes the output.

The above switching control is also performed in the decoder section 29, and the encoder section 1. Both decoder sections 29 are in the C mode, and a maximum noise low frequency operation of 20 dB is performed by compressing and expanding middle and high frequency components.

Next, the level of the switching control input signal vs is approximately the reference voltage V
When the level of RgF becomes equal to the level of B mode and the B mode is commanded, the potential of the base of transistor Q2 becomes the reference voltage VREF.
The potential of the base of transistor q becomes (VREF 2 VBE ), which is equal to the potential of . Then, in the differential pair 35, the transistor Q is turned on and the transistor Q2 is turned off. Also, in the differential pair 36, transistors Q3. Q4 is off, transistors Qs, Qa
If I2 and I2 are set to be equal, for example, a second switching control signal consisting of a no-current signal is output from the collector of transistor Q1. Transistor Q2. From the collector of Q3 is a constant current source I3. A constant current is output from each of I4, and switching control signals α and C consisting of the first and third no-current signals are no longer output.

The switching element 26 in the sub-signal path 16 of the LLS is turned on by the second switching control signal, and the control current in the variable impedance element 20 becomes excessive. For example, a number. LLS becomes an extremely small value of around 0.
The effect of enhancing the low-level middle and high frequency components in the sub-signal path 16 is eliminated. Further, the circuit constants of the filter 7, the time constant circuit of the detector 10, and the O8 circuit 11 in the sub-signal path 6 of the HLS are switched and changed. At the same time, S
In the S circuit 2 and the As circuit 15, the switch amplifier 3
, 170, so that the signal supplied to one input terminal, that is, the signal directly input without going through each of the filters 4 and 18, is selectively output. As a result, only the low-level middle and high frequency components in the sub-signal path 6 of the HLS are enhanced, and the input signal is compressed by a maximum of 10 dB and becomes the encoder output.

The above switching control is also carried out in the decoder section 29, and both the encoder section 1 and the decoder section 29 are in the B mode, and a noise four-range operation of a maximum of 10 dB is performed by compression and expansion of middle and high frequency components.

Next, when the level of the switching control input signal v8 becomes approximately ~ and the off mode is commanded, the potential of the base of the transistor Q2, the potential of the base of the transistor Q5. The potential of the base common connection point of Qa is (VREr 2VBE) +('
vRE2-4vBE) tonal. Soult, differential pair 35
, transistor Q is on, transistor Q2
is turned off. Also, in the differential pair 36, transistors Q3. Q4 is turned on, transistor QIQa is turned off, and the first and second switching control signals are output. This first
The switching element 14 in the HLS 6 is turned on by the switching control signal a, and the input impedance of the variable impedance element 8 becomes an extremely small value, thereby eliminating the enhancement effect of the low-level middle and high frequency components in the sub-signal path 6 of the HLS. In addition, the second switching control signal eliminates the effect of enhancing the low-level middle and high frequency components in the sub-signal path 16 of the LLS, and further changes the switching of the input stage of each of the switch amplifiers 3 and 17 in the SS circuit 2 and the AS circuit 15. As a result, signals directly inputted without going through each of the filters 4 and 18 are selectively output.

The above switching control is also performed in the decoder section 29, and both the encoder section 1 and the decoder section 29 are in the off mode, and no noise reduction operation is performed.

In the above operation, when off mode B is commanded, a second switching control signal S which is also generated in B mode is generated together with the first switching control signal α, and this second switching control signal S is generated in both OFF mode and B mode. In the operating mode, the switching control signal is supplied to the necessary switch amplifiers 3, 17 and switching element 26, so when equipped with a switching control signal generation circuit configured to generate the off mode command and the B mode command individually, The necessary OR (logical sum) circuit is not required in the noise reduction circuit according to the present invention, and the circuit scale can be reduced.

Incidentally, in the description of the above embodiment, the mode control signal α is used.

h and c are assumed to consist of no-current signals, but conversely, the mode control signal α is assumed to be a state in which current exists in the form of inflow or outflow during each mode.

It is also possible to use transistors Q7. Q2. By connecting so-called current mirror circuits to each of the constant current sources It, Is = I4 connected to the collector of Q3, the current outputs of those mirror circuits are used as the mode control signal αIbI'.
It would be a good idea to treat it as such.

As detailed above, the noise filter circuit according to the present invention performs switching control by generating both the first and second switching control signals when a single control input signal becomes the first predetermined state. The number of output terminals is small, and the OR circuit required when generating a single switching control signal according to each state of the control input signal is not required, so the circuit size can be reduced.

[Brief explanation of the drawing]

The figure is a circuit block diagram showing one embodiment of the present invention. Explanation of symbols of main parts 1... Encoder section 29...Decoder section

Claims (1)

[Claims] 1st. Second. The third switching control signal controls the switching of circuit constants, etc. to stop the operation in the noise range, continue the noise reduction circuit by the B type Dolby system, and continue the noise reduction circuit by the C type Dolby system. a compander circuit capable of generating said first and second switching control signals when a single control input signal enters a first predetermined state; and said compander circuit generating said first and second switching control signals when said control input signal enters a second predetermined state; 2. A switching control signal generating circuit, the switching control signal generating circuit generating the third switching control signal when the control input signal reaches a third predetermined state.