JPS586584A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease the probability of software error generation at the operation, by setting the threshold voltage of a MOSFET constituting a bistable circuit for memory cells to the high level and fixing a potential of H level of a cell at readout to a power supply voltage. CONSTITUTION:A memory cell 1a is at the initial state, a potential v1 of a drain D of a MOSFET2a is set to a power supply voltage VCC level, a potential v2 of the drain D of a MOSFET3a is at ground potential, a word line 12a is set to L level and the stable point of the cell 1a is P(VCC, 0). When the line 12a is charged, MOSFETs 15a and 16a are conductive to start readout. In this case, the stable point of the cell 1a is transited to R(VCC, VRL) and an H level potential VH of the cell 1a is kept to a voltage VCC. Thus, the threshold voltage VTH of the cell can be set higher than the potential of the L side of the cell at readout.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that can reduce the probability of soft errors occurring in a static memory cell in an operating state of the memory cell.

FIG. 1 is a circuit diagram showing a memory array of a conventional semiconductor memory device. In the figure, (1s to (1n) are memory cells, (2a) to (2n) Fi, whose drains (D) are connected to nodes (4a) to (4n), respectively, and gates (
G) are connected to nodes (5a) to (5n), respectively, and the source (S) is connected to ground.
T), (3a83n) have their drains (D) connected to the nodes (5a) and (5n), respectively, and their gates (0)
are connected to the node (41L84n) respectively, and the source (
8) is connected to ground woeyBr, (6a)
-(an) b, (7a) and (1n) are power supply terminals, (8
a88n) is connected to this power supply (6a)-(6n) and the node (4
a) High load resistors connected between each of (4n),
(9a)-(gin)" is this power supply terminal (7a)-(7
The high load resistors (lea) (Ion) connected between the nodes (5a) and (5n) are connected to the node (4a8)
The parasitic capacitances (11a) to (lln) are connected between the node (5n) and ground to store memory information, respectively.
a) Parasitic capacitances connected between (5n) and ground to store storage information, (121L) to (17n) are word lines, (13) and (14) are bit lines,
(15&) ~ (15n) a drain (or source)
is connected to the bit line (13), the gate is connected to the word twins (12a) to (12n) K, respectively, the source (or drain) is connected to the node (4a) to (4n), respectively, and the memory cell (1a) is connected to the bit line (13). )~(1n) MO8PK for gates with write and read control functions
D, (16a) to (16n) have their drains (or sources) connected to the bit line (14), gates connected to the word lines (12a) to (12n), respectively, and sources (t or drain) connected to the node. uosymT for gates connected to (5a) to (5n) respectively, (17a) and (17b) ed power supply terminal, (18) Hiro drain and gate connected to power supply terminal (17a), source connected to bit line (13) A diode-connected MO8FI? that connects to and precharges the bit line (13). , (
19) has drain and gate I! [# terminal (17b
), the source is connected to the bit line (14), and the source is connected to the bit line (14).
A diode-connected Mospmt precharges the bit line (14), (20) is an input terminal to which a column selection signal is input, (21) and (22) are VO lines, and (23) has a drain (or source) connected to a column select signal ( 2
1), whose gate is connected to the input terminal (20), and whose source (or drain) is connected to the bit line (13); ), the gate is connected to the input terminal (20), and the source (or drain) is connected to the bit line (14).

In addition, - as an example, 16 of 128 x 128 planes
In static RAM! 128 bit lines are arranged in columns, and each bit line is connected to the same bit line.

Next, a description will be given of the operation of the semiconductor memory device having the above configuration, particularly the mechanism by which a soft error occurs in any memory cell due to the minority carriers generated when the memory cell is irradiated with α particles. First, to simplify the explanation,
Let's focus on the memory cell (1a). ir, M in initial state
Osyr(2a) ノ)"L/In(D) potential v1 is "r level vi+(?m=Voo)h b, MosF
mT(3a) o Drain (D) potential v2 is “LI”
T v Ben, VL (vL = (1), the word line (12a) is set to "L" level, and the latch is in a stable state. On the other hand, when the memory cell is irradiated The α particles travel approximately 30 μm through the silicon substrate, during which time electron-hole pairs are generated.

The holes among these electron-hole pairs flow down to the substrate 81111 pole, and the electrons form the drain (D) of MO8FICT (2a)? collected in the diffusion layer. This collection requires ~100 na, but this time requires a parasitic capacitance (10 a) from the power supply through a high load resistor (8 a).
) is much shorter than the time constant of several μe required to supply charge to Therefore, the drain (D) of uosmT (3a), which has been charged in advance to the "■" level, is charged with an amount of electrons greater than the amount of charge Qo required to invert the latch.
If this occurs, the supply of positive charge sufficient to cancel this is not in time, and the 7 lip 70 tubes constituting the memory cell (la) are inverted, generating a soft effect. In this case, the probability of soft error occurrence is the drain (
D) greatly depends on the initial potential Vw, and this initial potential VB
As the initial potential vH increases, the soft error occurrence probability decreases, and as the initial potential vH decreases, the soft error occurrence probability increases. However, how this initial potential Vm changes over time in the operating state will be explained with reference to FIGS. 2 and 3. First, Figure 2 shows the correlation between the input and output transfer characteristics of the memory cell in Figure 1.
Drain (D) of r(2a) O potential v1 and D'=x
MO8FIT (3a) 2) Drain (D) potential v on the axis
2, the memory cell (1a) is in the initial state, and the stable point of the memory cell (1a) is P(Too, O)
It is in. Next, at t=tl in FIG. 3, when the word line (12,a) is charged, nosymr
(15a) and (16a) become conductive, and a read operation starts. The stable point of the memory cell (1a) during this reading shifts to Q(Van, VIL). However, 71
111 is the potential on the “H” level side of the memory cell (la) during reading; l)? ) and VmT are potentials on the "L" level side of the memory cell (1a) during reading. That is, at the time of reading, the Vmi of the first place of the train (D) of nosIPTfr (2a) decreases, and MO8FIn'I
'When the potential of the drain (D) of (3a) is -1=1g, when the word line (12a) is discharged, M08IF
RtT (15a) and (16a) are cut off.

At this time, the drain (D) of MO8FI[1T (3a)
The potential of MOSFET (2a) immediately drops to the ground potential through MO8Fff (2a), but the drain (D
) has an extremely large time constant (10 to 100
It is charged to the power supply voltage Voo in micrometers. After that, every time the word line (121L) is charged at t=ts, t=1+, the potential Vx of the drain (D) of MO8Fm (2a) decreases to Th value, and the word line (121L) is charged at t=t4゜t=ts. When the line (12a) is discharged, MOEIFII:T(
The drain (D) of 2a) starts charging to the power supply voltage Voa. That is, during operation, Vm changes with time, and the more the word line (12a) is charged and discharged, the more ■! The average voltage level of I decreases and v! Approaching LH. This phenomenon occurs in all memory cells in the memory array. - Therefore, in the operating state, the probability of soft errors occurring increases due to the decrease in the average voltage level of Vm.

In this way, conventional semiconductor memory devices have drawbacks such as an increase in the probability of soft errors occurring in the operating state because the average level of the potential on the H level side of the memory cell during operation decreases as described above. there were.

Therefore, the object of the present invention is to
This book provides a semiconductor memory device that can fix the "H" aa level side of 4 to the power supply voltage 'Voo and reduce the probability of soft error occurrence in the operating state.

In order to achieve such an object, the present invention sets the threshold voltage of the MOBFIeτ that constitutes the bistable circuit of the memory cell to be high, thereby lowering the "H" level side potential of the memory cell during reading to the power supply voltage To. .

This will be explained in detail below using an example.

FIG. 4 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. In the same figure, −(25) and (2
6) is a power supply terminal to which the power supply voltage Voo is applied, (27) is a load whose drain and gate are connected to the power supply terminal (25), whose source is connected to the bit fin (13), and which precharges this hit line (13). Transistor, (2
Reference numeral 8) is a load transistor whose drain and gate are connected to the power supply terminal (26), and whose source is connected to the bit line (14) and precharges the bit line (13).

In the table, mosFTiT (2a) to (2n) and (3a
) to (3n) during operation is RDOII, M
O87 (15a) to (15n) and (16&)
The on-resistance during operation of ~(16n) is Rto.

Let RLOII be the on-resistance of MO8FRiT (27) and (28) during operation. Also, uosyI! ! T(3
The threshold voltages 7 HD of a) to (3n) and (4a) to (4n) are set to satisfy the following conditions.

In order to satisfy this (m1 formula), MOSFET (3a)
~(button) and (41~(4n) threshold voltage V-r
By setting HD, l+ and Vm do not change over time and are fixed to the power supply voltage Voo. Further, FIG. 5 is a diagram showing the correlation between input and output transfer characteristics of memory cells during a read operation.

Next, the operation of the semiconductor memory device having the above configuration, particularly the operation for suppressing an increase in the probability of soft error occurrence in the operating state, will be described. To simplify the explanation here,
The memory cell (1a) will be explained. Now, in the initial state, the potential v1 of the drain (D) of MO8FIliT (2a) is at the power supply voltage Voa level, and Mo5IPW!
Potential V of the drain (D) of (3a)! is set to the ground potential, and the word line (12a) is set to "L" level, and the stable point of the memory cell (1a) is shown in Figure 5 (vl).
, Vo)=P(Woo, O). Next, when the word fin (12a) is charged, i&)8FICT (15
a) and (16a) become conductive and start a read operation. At this time, as shown in FIG. 5, the stable point of the memory cell during reading is (Vl, Vt) = (Too, VmL)
During the transition, the "H" level side potential vH of the memory cell (1a) remains maintained at the power supply voltage Voa. That is, in a configuration that satisfies the above formula (A), the bell side potential VIIL at "L" during reading is MO8FRiT (2a
) is lower than the threshold voltage VTID of this MO.
811TXT (2a) is not conducting and its drain (D)
The potential of Voa does not decrease as much as Voa.

Therefore, vH does not change over time and Vo
.

maintained at the same level. Therefore, it is possible to suppress an increase in the probability of soft error occurrence in the operating state.

In the above embodiment, the threshold voltage Vtw of the memory cell MO8PKT was set to be higher than the potential on the "L" side of the memory cell during reading, but the equation (A)
In order to satisfy the following, the threshold voltage of the MOSFET in the memory circuit is V! By making g uniform, the dimensions of each MO8FET are
Of course, it is also possible to set the value β of each MOEIFET. Also, M.O.
Of course, the VTIID of 8PR'l' (2a) and (3a) may be set to a different value from the Vti of other MOSFETs. In addition, in the above embodiment, an n-channel type M)8m was explained, but a p-channel type M)8m was explained.
O87] Of course, the same can be done in the case of CT. In this case, the polarity of the voltage may be reversed. Also,
In the above embodiment, a high load resistor was used as the blue-up device of the memory cell, but the depression type M: 1sm
Of course, you may also use .

As explained above in detail, according to the semiconductor memory device according to the present invention, the "H" level side potential of the memory cell in the operating state does not decrease, so that the probability of occurrence of an error in the operating state can be reduced. There are effects that can be reduced.

[Brief explanation of the drawing]

! Figure 1 is a circuit diagram showing a memory array of a conventional semiconductor memory device, Figure 2 is a diagram showing the correlation between the input and output transfer characteristics of the memory cells in Figure 1, and Figure 3 is a diagram showing the correlation between the input and output transfer characteristics of the memory cells in Figure 1. FIG. 4 is a time chart showing the potential of the drain of a transistor forming a stable circuit, FIG. 4 is a circuit diagram showing an embodiment of the semiconductor memory device according to the present invention, and FIG.
FIG. 3 is a diagram showing a correlation between input and output transfer characteristics of memory cells in the figure. (1a) to (1n)...memory cells, (2a) to (
2n) and (3a) to (3n)...MO8 field effect transistor, (4a) to (4n) and (5a) to
(5n)...Node, (6a) to (6n) and (7a) to (7n) ---Power terminal, (8a) to
(8n)...High load resistance, (9a)~(9n)...
・・High load resistance, (1G &) ~ (Ion) and (11
a) ~ (11n)... Parasitic disease, (12a) ~ (1
2n)...Word line, (13) and (1
4)...Hit line, (15a) to (15n) and (16a) to (16n)...MO8 field effect transistor for gate, (17a) and (17m))
...Power terminal, (18) and (19)...MO
8 field effect transistors, (20)...input terminals,
(21) and (22)...5 lines, (23)
and (24)... MO8 field effect transistor, (25) and (26)
...Power supply terminal, (27) and (28) ...Load transistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 2 v2 Figure 3 H Mu procedural amendment (voluntary) Commissioner of the Japan Patent Office 2, Name of the invention semiconductor storage device - 13, Person making the amendment 5, Subject of the amendment ( 1) Column for detailed explanation of the invention in the specification (2) Column for brief explanation of drawings in the specification (3) Drawing 6, content of amendment +11 11A Specification, page 9, line 18 to page 10, line 6 Correct the line "(c) and..." as shown in the following sentence. r MOSFET (25m) ~ (25n), MO
SFETs (26a) to (26n) correspond to (2a) to (2n) and (3m) to (3n) shown in Fig. 1, respectively, but MOSFETs (25m) (25n)
), (26m) The threshold voltage of (26n) is set higher than that of other MOS-FETs in the memory circuit.
(3m) is different from (3n). Further, (27a) and (27m) represent memory cells. ” (21st edition, page 10, line 7, page 11, line 6, page 11, line 19, page 11, line 20, page 12, line 13 r (2
a) Correct J to [25a) J, respectively. (3) Same book, page 10, line 7, r (2n) J to r (
25n) Correct as J. (4) Same book, page 10, line 7, X, page 11, line 8, 12
r(3a)J on page 13th line respectively r(26a)”
and correct it. (5) Same book, page 10, line 7, r (3n) J to r
(26n)”. (6) “■ and (to)” on page 10, line 1θ of the Ministry of Health, Labor and Welfare
Correct with Nishiki and a9J. (7) Same book, page 10, lines 11-12, same page, lines 15-16
Row r (3a) to (3n) and (4&) to (4n)
J as r (25m) ~ (25n) and (
26m) to (26n) J. (8) r (1 m
)” are respectively corrected as r(27a) J. (9) “(c) and ■” on page 14, lines 11-13 of the same book
~Load transistor. ” to r (25m) ~ (25n)
. (26m) ~ (26n) * * * * M 08
Field effect transistors, (27a) to (27n)...
・Memory cell. ” he corrected. αQ Figures 3 and 4 of the drawings will be corrected as separate sheets. Above Figure 3 H

Claims (4)

[Claims] (1) It has an iris x transistor and an H2 transistor, the drains of which are connected to a power supply via a first pull-up means and a second pull-up means, respectively. A memory cell whose sources are grounded, and whose gates and drains are cross-connected to form a bistable circuit; and the third transistor and fourth transistor of #
A first bit line and a t! g2 bit line, a word line connected to the gates of the third transistor and the II4 transistor and sharing the write 6 and read selection lines;
A semiconductor memory circuit comprising a load circuit connected to a bit twin and a load circuit connected to each of the second bit twin, characterized in that the semiconductor memory circuit is characterized in that the semiconductor memory circuit includes: (1) for turning one of the first transistor or the second transistor into a cut-off state when reading data; Storage device. (2) The semiconductor according to claim 1, wherein the threshold voltages of the first transistor and the second transistor are set to be different from the threshold voltages of the third transistor and the fourth transistor. Storage device. (3) The semiconductor memory device according to claim 1, wherein the pull-up means is composed of a high resistance material, high resistance polysilicon, or depletion type MO8Fl'r. (4) The threshold voltage of the first transistor and the second transistor is set to a value larger than the threshold voltage of the third transistor and the fourth transistor. Semiconductor storage device.