JPS5865457U - load control circuit - Google Patents

load control circuit

Info

Publication number
JPS5865457U
JPS5865457U JP15997481U JP15997481U JPS5865457U JP S5865457 U JPS5865457 U JP S5865457U JP 15997481 U JP15997481 U JP 15997481U JP 15997481 U JP15997481 U JP 15997481U JP S5865457 U JPS5865457 U JP S5865457U
Authority
JP
Japan
Prior art keywords
load
control circuit
signal
control signal
load control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15997481U
Other languages
Japanese (ja)
Other versions
JPS641573Y2 (en
Inventor
博之 小西
Original Assignee
富士通テン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テン株式会社 filed Critical 富士通テン株式会社
Priority to JP15997481U priority Critical patent/JPS5865457U/en
Publication of JPS5865457U publication Critical patent/JPS5865457U/en
Application granted granted Critical
Publication of JPS641573Y2 publication Critical patent/JPS641573Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は先行技術を示すブロック回路図、第２図は本考
案の一実施例のブロック回路図、第３図、第４図、第５
図および第６図は第１周波数−電圧変換回路１７の機能
を説明するための波形図である。 １０・・・負荷制御回路、１１・・・ロックアツプツレ
メイド、１２・・・マイクロコンピュータ、１３・・・
発振器、１６・・・ＡＮＤゲート、１７・・・第１周波
数−電圧変換回路、１８・・・第２周波数−電圧変換回
路。Figure 1 is a block circuit diagram showing the prior art, Figure 2 is a block circuit diagram of an embodiment of the present invention, Figures 3, 4, and 5.
6 are waveform diagrams for explaining the functions of the first frequency-voltage conversion circuit 17. FIG. DESCRIPTION OF SYMBOLS 10...Load control circuit, 11...Lock-up remade, 12...Microcomputer, 13...
Oscillator, 16...AND gate, 17...1st frequency-voltage conversion circuit, 18...2nd frequency-voltage conversion circuit.

Claims (1)

【実用新案登録請求の範囲】 発振器からのクロック信号によって同期動作を行ない、
負荷を制御するための２値化制御信号を出力する処理装
置を備え、正常な制御動作中には一定周期の発振信号が
前記処理装置から導出されるようにした負荷制御回路に
おいて、 前記発振信号および前記発振器からのクロック信号の少
なくとも一方の異常状態を検出する手段、および 前記制御信号が入力されるとともに前記異常状態の検出
手段の出力が与えられ、正常状態であるとき前記制御信
号をそのまま出力し、異常状態であるときには、前記制
御信号の論理状態に拘らず前記負荷を安全動作状態にす
る論理信号を出力する論理回路を含むことを特徴とする
負荷制御回路。[Claims for Utility Model Registration] Synchronous operation is performed using a clock signal from an oscillator,
A load control circuit comprising a processing device that outputs a binary control signal for controlling a load, the oscillation signal having a constant period being derived from the processing device during normal control operation. and means for detecting an abnormal state of at least one of the clock signals from the oscillator, and when the control signal is inputted and the output of the abnormal state detecting means is provided, and when the control signal is in a normal state, the control signal is output as is. A load control circuit characterized in that the load control circuit includes a logic circuit that outputs a logic signal that brings the load into a safe operating state regardless of the logic state of the control signal when the load is in an abnormal state.
JP15997481U 1981-10-26 1981-10-26 load control circuit Granted JPS5865457U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15997481U JPS5865457U (en) 1981-10-26 1981-10-26 load control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15997481U JPS5865457U (en) 1981-10-26 1981-10-26 load control circuit

Publications (2)

Publication Number Publication Date
JPS5865457U true JPS5865457U (en) 1983-05-04
JPS641573Y2 JPS641573Y2 (en) 1989-01-13

Family

ID=29952405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15997481U Granted JPS5865457U (en) 1981-10-26 1981-10-26 load control circuit

Country Status (1)

Country Link
JP (1) JPS5865457U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611552A (en) * 1984-06-12 1986-01-07 Diesel Kiki Co Ltd Control unit for vehicles
US10167909B2 (en) 2015-11-02 2019-01-01 Hyundai Autron Co., Ltd. Method and apparatus for controlling damper clutch to prevent engine stall

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259842A (en) * 1975-11-12 1977-05-17 Nippon Electric Co Method of manufacturing solid state electrolytic capacitor
JPS5833855U (en) * 1981-08-28 1983-03-05 日産自動車株式会社 Lock-up control device for lock-up automatic transmission

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833855B2 (en) * 1976-01-12 1983-07-22 東レ株式会社 Esterification method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259842A (en) * 1975-11-12 1977-05-17 Nippon Electric Co Method of manufacturing solid state electrolytic capacitor
JPS5833855U (en) * 1981-08-28 1983-03-05 日産自動車株式会社 Lock-up control device for lock-up automatic transmission

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS611552A (en) * 1984-06-12 1986-01-07 Diesel Kiki Co Ltd Control unit for vehicles
US10167909B2 (en) 2015-11-02 2019-01-01 Hyundai Autron Co., Ltd. Method and apparatus for controlling damper clutch to prevent engine stall

Also Published As

Publication number Publication date
JPS641573Y2 (en) 1989-01-13

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