JPS586473A - Trouble detecting system for digital modulating circuit - Google Patents

Abstract

PURPOSE:To detect a trouble of a digital modulating circuit and to increase the reliability fo writing information, by demodulating a modulated digital signal and then collating the modulated digital signal with the digital signal obtained before modulation to detect an error of modulation. CONSTITUTION:The writing 8-bit parallel digital signal is converted into a serial digital signal through an 8-digit shift register 1 and supplied to the 4-digit and 3-digit shift registers 2 and 3 respectively. The four types of signals obtained through the register 2 are converted into the MFM modulated digital signals through a modulating circuit 4. These modulated digital signals are demodulated by a demodulating circuit 5 and collated with the digital signal of the register 3 obtained before modulation through a collating circuit 6. At the same time, a signal interval monitor circuit 7 monitors the interval of the MFM modulated digital signal. An OR circuit 8 obtains an OR of the errors of modulation. Thus a trouble of the circuit 4 can be detected with high accuracy.

Description

[Detailed description of the invention] The present invention relates to failure detection in digital modulation circuits.

In digital IJIc storage devices such as magnetic disk devices, a variety of complex modulation methods including the MFM method are being adopted to reduce the size, increase speed, and increase capacity, especially to round off the high-density recording that is required for these purposes. started to be
Furthermore, the circuit configuration centered on the modulation circuit has become extremely complex, including the provision of a write compensation circuit to reduce the peak shift during reading that occurs when the recording density is increased.

Along with this, the possibility of failure occurring in the core portion is also increasing, but until now no effective means have been taken to directly detect failures occurring in this portion. For example, the read-after-write function is a very effective means of detecting failures in the entire writing system, but
It is not possible to directly detect failures in the modulation circuit, and it cannot be used in magnetic disk drives or the like. In addition, there is a fly-off that occurs when the current flowing through the magnetic head is reversed.
There is a method to detect write errors by detecting the pack voltage, but this method is also powerless to detect failures in the modulation circuit.

The present invention has been devised to cope with the current situation, and its purpose is to detect failures in digital modulation circuits and improve the reliability of written information.

To achieve the above object, the present invention includes a demodulation circuit that demodulates a modulated digital signal, and a demodulated digital signal obtained in the demodulation circuit that detects a failure in a digital modulation circuit. The apparatus includes a collation circuit that detects the modulator 2- by collating the signal with the signal, and a signal interval monitoring circuit that monitors the signal interval of the modulated digital signal to detect a modulation error.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram when the present invention is applied to an MFM modulation circuit, in which 1 is an 8-digit shift register that converts an 8-bit parallel digital signal, which is write information, into a serial digital signal; is a 4-digit shift register 1 that obtains n serial digital signals with a 1-bit period delay, a 2-bit period delay, a 3-bit period delay, and a 4-bit period delay of the serial digital signal obtained in the 8-digit shift register 1.
Register 3 is an 8-digit shift register 1. A 3-digit shift register is used to obtain the signal obtained in 3-bit periods of the serial digital signal obtained in register 1. 4 is a 4-digit shift) obtained in register 2. 5 is a demodulation circuit that demodulates the MFM modulation digital signal obtained in the modulation circuit 4 to obtain a demodulated digital signal; 6 is a demodulation circuit that obtains a demodulated digital signal using a signal of type 411; Compare the FJ4te')I'le signal with the digital signal before transformation obtained in the 3-digit shift register 3,
A matching circuit 7 generates a matching error signal when they do not match, and 7 monitors the MFM modulated digital signal interval obtained in the idiom circuit 4, and detects a signal interval exceeding 2 bit period, which is the maximum signal interval in the MFM modulation method. a signal interval monitoring circuit that generates a signal interval error signal when detecting the signal interval;
is an OR circuit which obtains the logical sum of the collation process 2- signal generated by the collation circuit 6 and the signal interval error signal generated by the signal interval monitoring circuit 7. In FIG. 1, a demodulation circuit 5, a collation circuit 6, a signal interval monitoring circuit 7, and an OR circuit 8 constitute a failure detection circuit io of the modulation circuit 4.

In such a configuration, if the modulation circuit 4 fails, the MFM
When an error occurs in the modulated digital signal, the matching circuit 6 and the signal interval monitoring circuit 7 detect the modulation error from different viewpoints, and the OR circuit 8 obtains the OR of these modulation errors. Failures in the modulation circuit 4 can be detected with high accuracy.

Next, the manner in which modulation errors are detected in this embodiment will be explained in more detail using a specific circuit diagram and time charts of signals at each part thereof. FIG. 2 is a specific circuit diagram of the failure detection circuit 10 shown in FIG. 1, and FIG. 3 illustrates a time chart of signals in each part thereof. Components of the failure detection circuit 10 shown in FIG. 1 and components of the circuit diagram shown in FIG. 2 do not correspond one-to-one, except for those using the same reference numerals. In these figures, A and B are two types of clock signals with different waveforms, E is a digital signal before modulation, and GF! , MFM modulated digital signal, α is the current waveform of the magnetic head shown for reference, H is the demodulated digital signal, ■ is the collation error signal, the lower order of the 2-digit binary counter that constitutes the JFi signal interval monitoring circuit. K is the output signal of the upper digit 7', L is the logical sum of the matching error signal I and the signal interval error signal M (not shown in FIGS. 2 and 3). It's a signal.

In FIG. 3, dotted lines indicate time charts of signals at various parts when a modulation error occurs as indicated by the MFM modulation digital signal lamp *) mark. The verification device 6 detects the modulation error and generates a signal as indicated by the (**) mark on the verification error signal generator. On the other hand, each digit 7' and 7# of a two-digit binary counter constituting the signal interval monitoring circuit
is the modulated digital signal G, as indicated by the symbol (#).
It is shown that the signal interval exceeds a 2-bit period and becomes a 3-bit period. As a result of these, the logical sum signal becomes <
*** Verification error signal as indicated by > mark and (
A signal spacing error signal is generated as indicated by the ##) symbol. In this embodiment, the logical sum of the collation error signal and the signal interval error signal is obtained, but it is of course possible to output these error signals separately. This is useful when investigating the

As explained above, the present invention makes it possible to directly and doubly detect a failure in a digital modulation circuit just by using a simple circuit, and therefore also improves the reliability of written information. There are two effects that can be done.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention,
5 is a demodulation circuit, 6 is a collation circuit, 7 is a signal interval monitoring circuit, and 10 is a failure detection circuit having these components. FIG. 2 is a specific circuit diagram of the failure detection circuit 10 of FIG. 1, and FIG. 3 is a time chart of signals in each part of FIG. 2.

Claims (1)

[Claims] a demodulation circuit that demodulates the digital signal modulated by the digital modulation circuit; a verification circuit that compares the demodulated digital signal obtained in the demodulation circuit with the digital signal before modulation to detect a modulation error; and a signal of the modulated digital signal. A failure detection method for a digital modulation circuit, comprising: a signal interval monitoring circuit that monitors the interval and detects a modulation error.