JPH0731884B2 - Sync signal recording method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to recording and transmitting digital data.

2. Description of the Related Art As a conventional synchronization signal recording method, when selecting a synchronization signal, a bit pattern that is unlikely to cause erroneous detection even if a bit shift occurs, or a certain special repeating bit pattern. Therefore, the same bit pattern as that of the synchronization signal was present in the modulation code string.

Therefore, as shown in, for example, Japanese Patent Laid-Open No. 55-67921, a synchronization protection circuit that utilizes the synchronism of the synchronization signal and gates and extracts only the synchronization signal is required as a means for preventing erroneous detection of the synchronization signal. did.

Problems to be Solved by the Invention However, in the above-mentioned configuration, since the synchronization protection circuit is required, there is a problem that the circuit scale becomes large, and when the synchronization protection is out of order due to an error or the like, or incorrect synchronization protection is performed. However, there is a problem that it takes time to recover again when applying.

It is an object of the present invention to surely detect a sync signal without using a sync protection circuit when using the 8-14 modulation method.

Means for Solving the Problems The present invention, when using the 8-14 modulation method, includes N bits (N bits) including a 16-bit pattern that does not appear in the modulated data sequence.
16) A sync signal recording method that uses a pattern as a sync signal.

Effect According to the present invention, since the bit pattern adopted for the sync signal does not appear in the modulation code string by the above means, the sync signal can be detected more reliably than when the sync signal appears in the modulation code string. As a result, it is possible to perform reliable sync detection with a simple structure without the need for a complicated sync protection circuit, and even when the sync signal is missing due to an error, etc., when the next sync signal is detected. Can return to correct operation.

Practical Examples Tables 1 to 6 show modulation code tables for 8-14 modulation in one embodiment of the present invention.

The allocation method of allocating the modulation code to the data is to obtain the CDS of all the modulation codes, and the modulation code of CDS = 0 is allocated to the data in a one-to-one relationship, CDS = + 2 and CDS = −4, CDS = −2.
And CDS = + 4, CDS = + 2 and CDS = -6, CDS = -2 and CDS = +
The 6 modulation codes are assigned to the data as a set.

Here, CDS is D from the beginning to the end of each modulation code.
SV (Digital Sum Variation: Digital Su
m Variation). DSV is the integral value of the waveform when the modulation code is NRZI modulated and the positive side is +1, and the negative side is -1. Here, the polarity at the start of NRZI conversion is the negative electrode side.

Of the one set of modulation codes, the modulation code with the smaller absolute value of CDS, that is, the modulation code of CDS = ± 2 is the modulation code of A group, and the modulation code of CDS = ± 4 and CDS = ± 6 is the modulation code of B group. The modulation code. The modulation code of CDS = 0 belongs to both groups.

For the modulation, the DSV value at the end of the modulation code immediately before the data to be modulated and the polarity when the NRZI modulation at the end of the modulation code is performed (H level is the positive side, L level is the negative side) Refer to. Here, DSV is from the start point of modulation, and the polarity of the start point is the negative electrode side.

Fig. 2 shows changes in polarity and DSV values. As shown in FIG. 2, the polarity is inverted by the bit "1" in the modulation code string.

The method of selecting the modulation code is shown in FIG. Modulation codes with a positive CDS value increase DSV when the polarity is negative and decrease DSV when the polarity is positive.

A modulation code with a negative CDS value decreases DSV when the polarity is negative and increases DSV when the polarity is positive. A modulation code whose CDS value is O keeps DSV constant regardless of whether the polarity is positive or negative.

Therefore, as shown in FIG. 3, when the polarity is positive and the DSV value at the end of the modulation code immediately before the data to be modulated is positive,
Of the two modulation codes of the A group and the B group corresponding to the data to be modulated, the CDS having a positive or zero CDS is assigned.

When the polarity is positive and the value of DSV at the end of the modulation code immediately before the data to be modulated is negative, the CDS of the two modulation codes of A group and B group corresponding to the data to be modulated is Assign a negative or zero modulation code.

When the DSV value at the end of the modulation code immediately before the data to be modulated is negative and the polarity is positive, the CDS of the two modulation codes of A group and B group corresponding to the data to be modulated is Assign a negative or zero modulation code.

When the DSV value at the end of the modulation code immediately before the data to be modulated is negative and the polarity is negative, of the two modulation codes of the A group and the B group corresponding to the data to be modulated, the CDS is Assign a positive or zero modulation code.

When the value of DSV at the end of the modulation code immediately before the data to be modulated is 0, regardless of whether the polarity is positive or negative, C
The modulation code of group A with a small absolute value of DS is assigned, and the amount of change in DSV is set to ± 2 or 0.

As a result, the DSV value of the modulation code string falls within a certain range.
In this example, the DSV is within ± 9.

At the time of demodulation, since the data is uniquely determined for the modulation code, 8-bit data is obtained by referring to the 14-bit modulation code.

The last bit of each modulation code is "0", and one or more bits "0" are included between the bits "1" and "1" in the modulation code. Within the modulation code, the maximum number of consecutive bit “0” s is limited to eight, and the maximum number of consecutive consecutive bits “0” is limited to four at both ends of the modulation code.

Also, the tip of the modulation code pattern consisting of 14 bits,
Or, there are 3 or more consecutive bits "0" at the rear end,
In addition, 7 consecutive bit "0" s in a pattern in which the bit "1" is sandwiched between consecutive 3 or more bit "0" s.
Patterns with more than one are not included in the modulation code.

Therefore, the pattern "10000000" occurs in the continuous part of the modulation code, but before and after this pattern "10000000"
Pattern does not occur continuously. Therefore,
The pattern "1000000010000000" does not appear in the modulation code string.

"10" is added to the rear end of this pattern to satisfy the continuous restriction of bit "0", and bit "0" is also added to the front end.
The arbitrary 10 bits are added so that the CDS of the synchronization signal becomes 0 while satisfying the continuous limitation of.

28 bits of “×××××××××× 100000001000000010” are used as a synchronization signal (the × part satisfies the continuous limitation of bit “0” and the CDS of the 28-bit standard signal becomes 0). Any 10 bits).

FIG. 1 shows a block diagram of the modulation / demodulation unit of this embodiment. In FIG. 1, 1 is input data, 2 is a framing unit, 3 is a modulating unit, 4 is a synchronization signal adding unit, 5 is an NRZI modulating unit, 6 is a recording unit, 7 is a reproducing unit, 8 is an NRZI demodulating unit, Reference numeral 9 is a sync signal detection unit, 10 is a shift register, 11 is a demodulation unit, 12 is a shift register, and 13 is an output end.

The input data 1 of 8 bits is input to the framing unit 2. In the framing unit 2, each frame is composed of a dummy sync signal, an address, an address error detection code, data, and an error correction code, as shown in FIG.

The framed data is input to the modulator 3. The modulator 3 performs modulation according to the 8-14 modulation algorithm described above.

Next, in the sync signal adding section 4, the dummy sync signal subjected to the 8-14 modulation and the normal sync signal "XXXXXXXXXXX"
Replace with XX × 100000001000000010 ".

After performing NRZI modulation in the NRZI modulator 5, the data is output to the recording unit 6 and recorded on a recording medium such as a magnetic tape.

At the time of reproduction, the NRZI demodulation unit 8 performs NRZI demodulation on the modulation code sequence reproduced by the reproduction unit 7.

The NRZI demodulated modulation code is input to the synchronization signal detector 9 and the shift register 10. In the synchronization signal detection unit 9, the fifth
As shown in the figure, the modulation code 15 input from the NRZI demodulator 8 is sequentially input to the shift register 14. Of the 16-bit output from the shift register 14 and the 28-bit synchronization signal, the 16-bit pattern 16 of "1000000010000000", which is a pattern that does not appear in the modulated data string, is compared by the comparator 17, and each frame Detects sync signal. When the two match, a detection signal is output from 18. Based on this detection signal, a clock is output to the shift register 10 for division into each modulation code and output to the demodulation unit 11 upon demodulation.

The shift register 10 demodulates one modulation code in parallel by the clock from the synchronization signal detection section 9 when the serially input modulation code is 14 bits.
Output to 11.

The demodulator 11 outputs 8 bits of data corresponding to the input modulation code to the shift register 12.

The shift register 12 serially outputs the input 8 bits of data from the output terminal 13.

As described above, by using the sync signal including the 16-bit pattern that does not occur when 8-14 modulation is performed, reliable sync detection is possible.

EFFECTS OF THE INVENTION As described above, according to the present invention, when the 8-14 modulation method is used, the synchronization signal including the 16-bit pattern “1000000010000000” that does not appear in the modulation code string is recorded, thereby simplifying the operation. With this configuration, the sync signal can be accurately detected, and even if the sync signal is missing due to an error or the like, it can be restored by the next sync signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a modulation / demodulation unit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of changes in polarity and DSV in a modulation code string of 8-14 modulation, and FIG. The figure shows 8-1
FIG. 4 is a diagram showing a method of selecting a modulation code of a 4-modulation system, FIG. 4 is a diagram showing a frame structure of an embodiment of the present invention,
FIG. 5 is a block diagram of a sync signal detecting section according to an embodiment of the present invention. 2 ... framing section, 3 ... modulation section, 4 ... synchronization signal addition section, 5 ... NRZI modulation section, 6 ... recording section, 7 ... playback section, 8 ... NRI demodulation section, 9 ... Sync signal detector, 10 ...
Shift register, 11 ... Demodulator, 12 ... Shift register.

Claims (1)

[Claims] 1. When the bit serial digital data is separated into 8 bits and the separated 8-bit data is converted into a modulation code of 14 bits, the last bit of the modulation code is set to "0", and the modulation code is set to "0". Within the modulation code, one or more bits "0" are included between the bit "1" and the bit "1", and the maximum number of consecutive bits "0" is eight. Is limited to 4 or less, and there are 3 or more consecutive bits “0” at the leading or trailing end of the modulation code, and the bit “0” of 3 or more bits. In the pattern where the bit “1” is sandwiched in the continuous part of, the limit is set so that the number of consecutive bit “0” does not exceed 7, and the CDS (Codew
ord Digital Sum), the modulation code with CDS = 0 corresponds to the 8-bit data in a one-to-one relationship, and CDS ≠
The modulation code of 0 corresponds to the 8-bit data as a set of two modulation codes having different CDS codes and different CDS absolute values, and two modulation codes corresponding to the 8-bit data. Which 16 bits in this modulation code string are used for the synchronization unit of the modulation code string that is modulated by using the 8-14 modulation method that removes the DC component by selectively using the modulation code. "1000000010000000", which is a pattern that does not match even if extracted
A method for recording a synchronization signal, characterized in that an N-bit (N ≧ 16) pattern including the data is recorded as a synchronization signal.