JPS5864549A - Selecting circuit - Google Patents

Abstract

PURPOSE:To store the least or greatest value in the 2nd memory at the end, and to easily select data, by successively inputting and storing N pieces of data in (n) units of the 2nd memories, and making comparison with external data and then storing the least or greatest value repeatedly. CONSTITUTION:The 2nd memory 10 for storing (n) pieces of predetermined data is provided to a data selecting circuit, and an address of the memory 10 is generated by a counter 6. Data sent to this memory 10 successively is compared by a comparator 11 with the least value (greatest value) of data sent to the memory 10 firstly or already to store a smaller (greater) address in a register 5, thereby supplying the address to the memory 10 through a selector 7. This operation is repeated to store prescribed (n) pieces of data in the memory 10, and those data are stored in a register 12; and the least or greatest value is stored in the memory 10 lastly, thus facilitating data selection.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selection circuit that can be implemented at N high speeds and is used in optical character reading devices and the like.

The Japanese optical character reader stores approximately 2,000 commonly used kanji in the first memory, and stores approximately 2000 commonly used kanji in the first memory.
Compare the kanji with the 0 character based on the similarity value and use this value as the second
I memorize the memo for January and output and process the memo with the highest degree of similarity. In such a case, N (predetermined predetermined data with the largest or smallest value from among the data of r/j or n pieces of data should be selected at high speed = 4). Conventionally, the following selection circuit is used. was.

Figure 1 is a block diagram of a conventional selection circuit, and Figure 2 is a block diagram of a conventional selection circuit.
A table is shown for selecting three pieces of data with large values from among the seven pieces of data in the figure. In the figure, the ILJ second memory, 2 is a control circuit, and 3 is a driver. The principle can be explained using Figure 2. The data A10 is memorized, and the addresses where these seven data are stored (values from addresses 1 to 7 in Figure 2) are controlled by the control circuit 2 and checked to determine the maximum value. 10 and its address 2 are memorized, and the content of address 1 is 4 and the maximum value of address 2 is 10.
The words are exchanged as shown in the mouth. Next, the content of the stored data at addresses 2 to 7 (this is controlled by control J [g1 path 2), the maximum value 9 and its address 7 are stored, and the content of address 2 is replaced with 4 as shown in C. Next, the data from addresses 3 to 7 are controlled by the control circuit 2, the maximum value 7 and its address 5 are stored, and the internal answer 6 of address 3 is replaced as shown in 2. If you output the internal data through driver 3, you will get three pieces of data with large values.If you want to select three pieces of small data, use the same method. In the case of 4, which is a replacement port, the minimum value from address 2 to address 7 is 2.
Replace the data with the data at address 2, and if the This will be stored in memory, so all you have to do is write it as an output child.

However, the second memory 1, such as the Japanese optical character Wh extraction device, which compares approximately 2,000 characters, indicates their U similarity as a value, and stores it once has a disadvantage of being large in size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a selection circuit that can perform selection quickly with a small-scale circuit configuration in order to eliminate the above-mentioned drawbacks.

In order to achieve the second object, the present invention inputs a second memo for storing N pieces of data, and stores the inner minimum value or maximum value of the n pieces of data. Next, compare with external data again, and if there is data larger (smaller) than the minimum value (maximum value), replace it with the minimum value (#ambassador) of the data stored so far. If the data of the new minimum value (maximum value) is repeatedly stored, the contents stored in the second memory ζ will finally become the data of the n largest value or the smallest value. Perform data collection.

One embodiment of the present invention will be explained below with reference to Figure 1.

No. 31 J is a block diagram of a selection circuit of an uninvented embodiment,
Figure 4 is a time chart showing the operation when n pieces of data are first stored in the second memory (hereinafter referred to as memory) in the case of Figure 3, and Figure 5 is the memory in the case of Figure 3. Figure 6 is a time chart showing the operation when the input data is smaller than the minimum value in the memory, and Figure 6 is a time chart showing the operation when the input value is larger than the minimum value in the memory in the case of Figure 3. =7-su0 In the figure, lO is memory 11, 4, 8 i'j comparator, 1
2 and 5 are registers, 6 is a counter, 7 is a selector, JA
L is the N values that are sent sequentially, BADD is the address of memo January 0, BFWE is the write signal to the memory 10,
0NTA is a control signal for using the output of register 5 or counter 6 as the address of memory 10, PTSTLI is a control signal for storing the output of counter 6 in register 5, ACE is a control signal for counter 6, VS
T is a control signal for storing the output of the memory 10 in the register 12ζ, OHB and F are the outputs of the comparator 11 and are stored in the memory 10.
Control signal to switch or not switch the contents of DS
ET indicates a control signal for searching for the minimum edge value for replacing the contents of the memory 10;

Initially, the first n pieces of data out of the N pieces of data sent are stored in the memory 10, which will be explained with reference to FIGS. 3 and 4. The start signal informs the sending of the data sent, and the control signal 0NTA selects the selector 7. When the processing of one data is completed, the END signal is issued to notify the end of the selection, and the next data VAL is sent together. let them know that it is okay to do so. This operation is repeated for each data process. The counter 6 is controlled by the control signal AOEl and stores the data VAL sent to the memory 10 at an address BAD.
For example D, 1 to n are compared with the value of nl by comparator 8 (trowel n)
Until this happens, each clock (this 1 is added and output).At first, the control signal 0NTA is on and the selector 7 outputs the output 1 of the counter 6 as the address of the memory 10.Also, the control signal Control signal PTS when 0HBFtj is on
The data VAL sent to the address I indicated by the counter 6 is sent to the memory 10, and the write signal BIi is output.
'WB (This address 1 is stored in the register 51. Next, the control signal 0NTA is turned off and the selector 7 outputs (Jl) The address 1 stored in the register 5 is output to the memory 104. -F
The data stored at the address l of the memory 10 is output from the digital output Do of the memory 10. Write the data VAL that is sent one after another to the memory 1 by the write signal Bl;'WE.
Addresses 2 to nG are stored using address 1 of 0 as a reference. At this time, the digital output T) is compared to the value from 0 and comparator
If the value of the sent data VAL is larger than the value of the digital output Do (the value of the data at address l), the control signal 0HBF' is turned off and the control signal PTST is turned off, as shown in Fig. 4A. If the output is not output and the value is small, the control signal OHB F is turned on as shown in FIG. The address HADD to the add terminal of 10 becomes this value (!:), and the minimum value of data up to this 4L is output from the digital output DO of the memory lO. n(giltRepeat until this happens! l-. Memo IJ10f In the situation where n pieces of data are stored, the address stored in register 5 is the address of the minimum value of n pieces of data, and therefore the address of memory 10 is The output from digital output D'0 is in a state where the minimum value is output.Next, data VAL is sent one after another.
When is smaller than the minimum value, the minimum value and the data VAL sent are compared with the comparator 11G, but since it is smaller, the control signal 0HBF is turned off as shown in FIG. 5, and therefore the control signal 0NTA is also turned off. Then the situation continues. If the value of the data VAL sent is larger than the minimum value, the control signal 0HBF is turned on as shown in FIG.
Write signal B FWE) Replace this data with the minimum value of the strange voice from the same address, and then write the memo I after changing the company.
To search for the minimum value among the data values stored in JlO, the search amount control signal 0NTA and the control signal AOBi are turned on. From this point on, the counter 6 successively compares the address l-n whose value is stored in the memory IO of the h-th block with the value of the comparator 84 n and outputs it. Initially, the first data is stored in the register 12 using the control signal V8TJ, and the address 1 of the value of this data is stored in the register 5# by outputting the control signal PTST. The comparator 4 compares the value of the data output from the register 12 with the value of the data sent next, and if it is smaller, turns on the control @1 signal 11- DSBT and turns on the control signals VST and PT8T. The value of this data is stored in the register 12.
In the address shown in FIG. 6, 4 is stored in register 5G. When a value smaller than the data value of the missing number arrives, the same operation as above is performed and the value and address (n-3 in FIG. 6) are stored in the register 12 and the register. Next is END4
Issue H and the process ends. This results in memory l
The address of the inner small value of the value of n data on O (in Fig. 6) is sent.The operation explained above can be repeated. When N data are sent out, this operation causes the memory lO to be It turns out that n pieces of data with large values are stored.

The above explained the operation of selecting n pieces of data with a large value, but when selecting n pieces of data with a small value, the minimum value is the maximum value, and when comparing with the comparator 11, when data with a smaller value comes Turn on the control signal OHB F, and also turn on the comparator 4.
When comparing to find the maximum 12-value of n data, turn on the control signal DSET when data with a large value arrives. The n pieces of data with the smallest value are stored in the memory 10 and selected. This is very effective when the value of l is sufficiently smaller than the value of N. Above, we only dealt with values, but if we memorize values indicating magnitude and related values, such as similarity and character code,
Since the optical character reading device does not need to store the recognition result (character code) and the degree of similarity between it and the input character, it can be used in the matching section of the optical character reading device.

As described above in detail, the present invention has the advantage of being able to select at high speed with a selection circuit having a small circuit configuration.

[Brief explanation of drawings]

The first factor is the block diagram of the conventional selection circuit, and the second factor is the block diagram of the conventional selection circuit.
3 is a block diagram of the selection circuit of the embodiment of the present invention, and FIG. 4 is the first table in the case of FIG. 3. Figure 5 shows the second memory in the case of Figure 3.
Figure 6 is a time chart showing the operation when the input data value is smaller than the minimum value in the second memory in the case of Figure 3. It is a time chart showing the operation. In the figure, 1 and 10 are second memories, 2 is a control circuit, 3 is a driver, 4, 8.11 is a comparator, 5.12 is a register, and 6
is a counter, 'If selector. 15- 11O for j'l'l; Wife O-b Jsu J% Q no eraser/catty

Claims (1)

[Claims] 1. A method of selecting n pieces of data having the largest value from a first memory storing N pieces of data, in which a predetermined n piece of data is stored. a second memory; a counter that generates the address of data on the second memory; a first register that stores the value of the data on the second memory; and a first register that stores the address of the data on the second memory. A second register for storing data and a first comparator for comparing the values of the data and other data are provided; When storing the data in the second memory, the data sent sequentially and the data sent first to the second memory or the data of the minimum value among the data sent in plural pieces of data are stored in the above-mentioned manner. The first comparator compares the data, stores the address of the smaller data in the second register, and repeats this process to store a predetermined n pieces of data in the second memory. At a time point, the address of the data having the smallest value among the n pieces of data is stored in the 81!2 register;
(2) Next, the first comparator compares the data in the first memory based on the address stored in the second register, and the value of the sent data is determined by the If the value is larger than the value of the n data on the second memory, the data of both are swapped and stored in the second memory, and the smallest value is selected from among the n data on the second memory. In order to search T, data is sequentially extracted based on the address output from the counter, compared by a second comparator, and the smaller data value is stored in the first register CC;
Also, store the address of the n data stored in the first register in the second register, repeat this, and store the minimum value among the n data in the first register ζ. The second register (this memory) compares the data sent again from the first memory with the minimum value of the data stored in the second memory,
A selection circuit characterized in that the above steps are repeated 11T until the data of the sent N([i'il) is completed.2. In the method of selecting n pieces of data, a second memory that stores n pieces of data determined in advance, a counter that generates an address of the data on the second memory, and data in the second memory A first register that stores a value of the data, a second register that stores an address of the data on the second memory, and a first comparator that compares the values of the data and other data. , ■ First, any n takes from the data in the first memory are sequentially transferred to the second memory.
When you stop storing the memo, the data sent next time and the data in the second memory (this data or the data that has already been sent multiple times) Maximum value data #' above
! 1 comparator, store the address of the larger data in the second register, and repeat this process.
Therefore, when the predetermined n pieces of data are stored in the second memory register, the address of the data with the largest value among the n pieces of data is stored in the second register, (2) Then, based on the address stored in the second register, the data with the maximum value is read out from the second memory, and the data that has been read out and the data that is successively sent thereafter are The data in the first memory are compared by the first comparator, and if the value of the data sent from the core is smaller than the value of the read data, the two data are exchanged and the data in the second memory are compared.
■The second memory that was then replaced
In order to find the largest data among n pieces of data on the memory of The value is stored in the first register, and the address of the data stored in the first register is stored in the second register.
Repeat the steps 3 and 3 to memorize the data in the first register, store the maximum value among the n data in the first register, and store the address of the data with the maximum value in the second register.
*9.The ratio between the data from the first memory that is sent again and the maximum value of the data stored in the second memory.*9. A selection circuit characterized in that the above process is continued until the N pieces of data sent are completed.