JPS59133659A - Address storage control system - Google Patents

Abstract

PURPOSE:To process plural information in a high speed within a single processing time, by holding in an address storage part, the address of pertinent data of retrieval data to be retrieved, which is extracted from an external storage device, synchronously with the read speed of a storage memory concerning retrieval information. CONSTITUTION:Information indicating a retrieving method of retrieval information is stored temporarily in a memory 6, and an initial value of retrieval information is stored in a memory 7. Data to be retrieved which are extracted from an extenal storage device 1 in accordance with contents of memories 6 and 7 are stored temporarily in memories 8 and 9. Data read out from the device 1 through an interface A2 and data read out from the memory 7 are compared with each other by a comparator 10, and read data from the device 1 is compared with data read out from memories 8 and 9 by comparators 11 and 12. In this case, a retrieval logic circuit control part 14 performs the logical control of each comparator output and holds the address of data to be retrieved in an address storage part 16 synchronously with the read speed of memories 8 and 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a control method for storing corresponding record addresses of searched data in an information retrieval device.

Prior Art When performing information retrieval using conventional hardware, one method of storing the address of the searched data that matches the search take is to prepare a dedicated address storage memory, store the corresponding record address, and There are two methods: to temporarily end the process, or to sequentially update new corresponding record addresses. However, with conventional search methods, the number of records that can be extracted in a single process is one, and it is difficult to extract multiple records in real time, and large hardware is required to make it possible.

When extracting desired information from an external storage device such as a magnetic disk, an information retrieval device stores a large amount of information in the storage device in the main memory of the central processing unit, and In addition, in order to process the information read from the magnetic disk in real time and extract the desired information, it is necessary to search once per access.
In an application in which only one item of information can be obtained and a large number of items are required, access to the external storage device is required for the number of items, which has the drawback of requiring a large amount of time.

Purpose: The present invention improves the above-mentioned conventional drawbacks, makes it possible to extract plurality of information within a single processing time, and enables flexible, inexpensive, and high-speed processing of storage methods for corresponding record addresses in search results. The purpose of this invention is to provide an address storage control system with the following configuration.

Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information retrieval device implementing the present invention.

1 is an external storage device under the control of this information retrieval device. 2 is an ink face A for controlling, transmitting and receiving the data and clock of the external storage device 1 mentioned above;

3 is an ink face B that sends and receives the address of the external storage bag @1 mentioned above and return information from the external storage device 1;
, 4 is a control unit MCT that controls the above-mentioned 1.2.3 and the entire information search device of the present invention.

5 switches the internal pass line, which will be described later, and controls the control unit MC.
A three-state gate that also controls the direction of data according to instructions from T4. Reference numeral 6 denotes a memory JM that temporarily stores information instructing a search method for search information. 7 is a memory Q1 that stores initial values of search information. Memory Q2 (8), Memory Q3
In (9), the searched data extracted from the external storage device 1 is temporarily stored, or the temporarily stored searched data is stored in the second memory according to the contents of the memory JM6 and memory Ql (7).
, a search register that also serves as a buffer memory and serves as a search data storage memory for searching the third extracted data. 10
A comparator CMI compares data read from the external storage device 1 via the ink face A2 with data read from the memory Q1 (7). 11 and 12 are reading data and memory Q2 (
8) or memory Q3 (9) Comparator CM2 or 0M3゜13 is memory JM
, 6. A length counter (L-C) that controls the addresses of the memory Ql (7), the memory Q2 (8), and the memory Q3 (9) and the length of the searched data. 14 is CMI
(10), CM2 (11)', CM3 (12), controls the logic of each comparator output, controls the operation of LC13, and controls the corresponding record address memory ADM16, which will be described later.
and a search logic circuit control unit IRCT that sends predetermined control information to the corresponding record status storage memory STM17.
. 15 is a record address counter RADC016 which counts the delimiter of the searched data according to the output information of the MCT4, holds it as the corresponding address in a series of records (records) of each data block θ, and sends it to the ADMI 6 according to the instruction of the IRCT14. As shown in FIG. 18 is a bus ink face BIF for connecting the information retrieval device of the present invention and a secondary device, etc.; 19 is a high-speed path line MBUS through which raw information from the external storage device 1 described above is exchanged, and 5BUS through which the status of each memory, counter value, and information to BIF 18 are exchanged under the control of M'LT4. Reference numeral 21 is a communication means LBUS between this information retrieval device and the other device, and an arbitrary communication means can be constructed using the BIF 18.

Next, the principle of operation of an information retrieval device according to a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an operational flowchart of the present invention.

Instructions are sent to this information processing device in a predetermined format via the LBUS 21 in FIG. 1, and the address of the external storage device l storing the data to be searched or the file name of each file is sent from the host device. The sent information is decoded by the control unit (MCT) 4, and control, etc. to the external storage device 1 is executed via each search register and the ink face B3, and the search process is started. When predetermined initial values are set in the search registers J'M and Q1 (step 100.l'o1), the external storage device 1 enters a data read cycle (step 1).
02). When the external storage device 1 reaches the search address, a waiting time begins, and when the search instruction address is reached (step 103-Y), MCT4J:1JL
A search start command is sent to c13 and RADc15 (step l'04), and in synchronization with the read speed of external storage device 1, it is output on MBUS19 via Ql (7) and interface A2 according to the contents of JM6. A comparison with the read data of the external storage device 1 is performed (
Step 105). This comparison uses the first and second half of one clock cycle to compare the upper limit value (or lower limit value) and the initial value of the lower limit value (or upper limit value), which is binary information, to the searched data. is included in the initialized values. Next, when it is determined that "Ql matches", it is selected whether the data is the first priority data (step 106). If the data is not in the first priority, it is then selected whether the data is in the second priority (step 107).

The conditions to be selected as the first priority are (1) when a match is first found within the range specified for search;

(2) From the corresponding data stored in Q2 and Q3,
If it is closer to the limit value.

The conditions to be selected as the second priority are: (1) within the specified search range, the second time the match is found and the corresponding data is further from the extreme value than the first time, or the first time matching data If equal to .

(2) For the first priority and second priority data stored in Q2' and 'Q3, the existing priority data is further from the extreme value than the existing second priority data. If it is close (in this case, the class data will replace the existing second priority data and become second priority data).

If it is determined that the data has the first priority (step 1
06-y, ), Q2 (8) and. 3 (9) A flag indicating whether or not the data stored in the data has the same content;
Determine the FSDB in step 1゜8). If the FSDB is 1, the first corresponding data from the start of the search (if they are not the same) or the data stored in Q2 (8) and Q3 (9) will be given priority. This means that data with a high degree of accuracy has been input as searched data. Therefore, it is determined whether the FDBL flag indicating that there was searched data that is the same as the first priority data in the past has been set (step 113), and if it has been set, it is reset (step 114). ). After that, in order to make the searched data stored in the work area the first priority data, the value of the record address counter where the searched data was recorded is set in the memory ADM (step 111), and at the same time, Q2 (8) , Q, 3 (
The work area stored in the searched data in 9) is set as the search data area, data further than the limit value in Q2 (8) and Q3 (9) is deleted, and the data storage location becomes the new work area. (Step 112).

Also, if FSDB=1, the already applicable data stored in Q2 (8) and Q3 (9) are equally searched data, that is, the first priority data is closer to the limit value than the already applicable data.
One of the existing applicable data must be deleted,
Set the FDBL flag to indicate that data equal to the existing data existed in the past.
9), F that indicates that the data corresponding to the layer is the same after that
, reset the SD p flag (step 110).
.

Then, in the same way as when FSDB = 1 mentioned above, set the value of the record address counter in the memory ADM, and search for the corresponding data that is later in time (already applicable data that is near the end of the address within the search instruction range), is deleted (step 111), and the deleted data area of Q2 or Q3 mentioned above is secured as a work area for the next record (step 112).

Next, if it is determined that it is not the first priority (step l”
O'6-N), it is determined whether the above-mentioned second priority condition is satisfied or not (step 107), and if it is determined that the second priority data is second priority data, the second priority data is ～I ■ Determine if it is equal to the priority data Step 1
15), Equal 4'Q2 (8), Q3 (9) It means that the data stored in the registers are equal, and then when the corresponding data interrupts the upper rank as the 19th priority data, , set the flag FSDB (indicating that the corresponding data of Q2 and Q3 are equal) for setting the FDBL (Step 116):
The value of the record address counter is set in the memory ADM (Step 114), the area where second priority data was stored is set as a new work area, and the area where searched data was stored is set as a new work area. The search data is set as the second priority data (step 112).

Also, if the second priority data is different from the first + ff priority data, for example in an unordered sorting process, if the first priority data is the second priority data, it will be treated as normal applicable data and a special flag will be set. does not involve setting or resetting. That is, the record address is set in the memory ADM (step 111), and the deleted data area is secured as a new work area (step 112).

If it is determined in step 107 that the data is not the second priority data, it is determined whether the data is similar to the second priority data (step 117). If it is different, Q2 (
8), sets the FDBL flag indicating that the same data as the corresponding data stored in Q3 (9) exists (step 118). Thereafter, it is processed as "not applicable" (step 119).

Next, using FIG. 3, the actual data storage state and comparison state will be explained along the flow of time.・Figure 3 is the first person in charge,
Data flow and Ql(7) when performing procedural sorting of numerical information from 50 to 125.

Q2 represents the storage state of data (8), Q3, and (9) and the storage state of record addresses. In the figure, the times are TO-Tl, T2. ...Tn, and the searched data is read output from an external storage device such as a disk device,
To distinguish each data, record N゛0, RO, R1, ・
There is =Rn. Ql (7) stores the limit values, lower limit and upper limit for sorting, and the comparator 7 in FIG. 1 checks whether the data to be searched is included in the desired values. That is, step 105 of the flowchart, T
In o, 50<123<125, so RO=123 is determined to be a "matching town" and is stored in the work area (W) of Q2 (8).In T1, 50<99×125 in Ql, and similarly R1= 99 is determined to be “applicable” and Q2 (8
), 99<1'23 holds true, so R1=99 becomes first priority data and RO=123 becomes second priority data. Each corresponding record address is shown in the storage state of the record-7 address in FIG. 3, with the upper one representing the first priority and the lower one representing the second priority. At T2, Ql is 50<
', 105 < 125, so "J is applicable, but in Q2 and Q3, 99 < 105 < 123 holds, so R O = 123, which was previously in the J2Pl priority order), will be deleted. Record address also stores R1 and R2.T
3, the condition of Ql is like 12 times, but Q2. 9 in Q3
R 2' =105, where 9=99<105, is deleted, and since the first and second priority data are equal, FSDB is set. T4 is satisfied under the condition of Ql, but Q2
．． Since the condition of Q3 is 99=99<102, the data of R4 has a low priority, so it is determined that the blade is not applicable. T5
Ql is I' applicable JIQ? , 91<99 in Q3
=99 holds, so it becomes first priority data and R3=9
9 is deleted. Since R, 3 = 99 and R1 = 99 are equal, as mentioned above, FSDB = 1 and the first priority ranking data existed, so FDBL is set and the existence of equal data other than the data stored in the register is set. You will be able to know whether or not there is. The conditions for T6 and Q1 are 11I! Although i is added to Q2 and Q3, 91<R6≦99 does not hold because R62100, so it becomes "not applicable". At T7, the condition of Ql is satisfied, and Q2. In Q3, R7(85)<91<99
holds true, so it becomes the first priority data and R7=85
is the first priority, R5=91 is the second priority, R1=
99 is deleted. Therefore, Q2, Q34 Koha (99)
FDBL is reset because it is no longer available.

The record address is stored in the record memory ApM for each record, but if it is determined that there is a match, the record address is stored in the ADM with matching information added to the beginning of the record address.

The ADM has an n-stage stack structure and reads the MCT at any time (any time until the end of reading this record).
By checking the ADM data, multiple records (searched data) can be obtained in one sorting process as described above.
You can also extract the record and find out the address of that record.

Physically Q2. By bringing the size of Q3 closer to the size of the external storage device, more data can be extracted at one time. In other words, it is possible to rearrange information stored randomly in a disk device or the like (representing random order when numerically representing a magnitude relationship) in accordance with a procedure or a grand request by searching the disk once. The structure of this record address is shown in FIG. Further, FIG. 5 shows the relationship between each register and the data to be searched. Il.

I2. ...Eng.5 is each record (RN, RN+1,
...) represents the item. Each item can serve as a key reference during a search, and II, I2. It is a unit of information that allows a logical product search for each item and a starting logical OR search for 11+12+3 as shown in I3. Such a search can be performed with an extremely simple configuration and high-speed search processing by comparing multiple pieces of comparison search data for the same subject data by dividing it into 8 from the size numbers of Q2 and Q3. do.

Effects As described above, by using the address storage control method of the present invention, it is possible to realize a plurality of information searches within a single processing time and to realize an information search that enables high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the tree embodiment. Figure 2 is an operation flowchart, Figure 3 is a diagram showing the flow of data when performing unordered sorting, Figure 4 is a diagram showing the structure of record addresses, and Figure 5 is a diagram showing the correspondence between searched data and each register. It is a diagram. In the figure, 1...external storage device, 2...interface A, 3...ink face B, 4...control unit, 6...memory JM, 7...memory Ql, 8...・・・
Memory Q2.9...Memory Q3.10...Comparator C
MI, 11...Comparator CM2.12...Comparator CM
3.13... Renx count, 14... Search logic circuit control unit, 15... Record address counter, 1
6...Memory ADM, 17...Memory STM, 18
...It's a lotus ink face. Patent applicant Canon Co., Ltd. 396

Claims (1)

[Claims] In an information processing device using an external storage device, a first storage section that stores search target data from the external storage device, a second storage section that stores at least one search data and search applicable data; a comparison section that compares the contents of the first storage section and the second storage section; a comparison condition storage section that instructs the comparison condition to the comparison section; and a comparison condition storage section that is synchronized with the read speed of the first storage section. An address storage control method characterized in that an address of at least one search target data in the second storage section among the search target data is held in an address storage section.