JPS5864058A - Thick multilayer substrate - Google Patents
Thick multilayer substrateInfo
- Publication number
- JPS5864058A JPS5864058A JP56162841A JP16284181A JPS5864058A JP S5864058 A JPS5864058 A JP S5864058A JP 56162841 A JP56162841 A JP 56162841A JP 16284181 A JP16284181 A JP 16284181A JP S5864058 A JPS5864058 A JP S5864058A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- conductor
- insulating layer
- substrate
- lower conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、厚膜多層基板に関するものであり、特に厚膜
抵抗の高密度実装に好適な混成集積回路等に使用する厚
膜多層基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thick film multilayer substrate, and more particularly to a thick film multilayer substrate used in a hybrid integrated circuit suitable for high-density packaging of thick film resistors.
厚膜混成集積回路は、回路の高密度実装の一つとして電
子機器に広く部用されている。しかし、一般に使われて
ｈる厚膜混成集積回路はセラミック基板上に導体配線を
一層または二層に形成し、厚膜抵抗はこの導体配線間に
配置、形成されている。その−例を第１図に示す、第１
図において、セラきツク基板−１の上に導体パターン２
を印刷、焼成によ）形成し、次に二層配線を行うための
絶縁層５と、この絶縁層上をクロスする上部導体４を形
成し、次に抵抗５が導体パターン間に形成され厚膜基板
が完成する。しかる後、牛導体等のチップ部品６が導体
ランド２′に搭載、″接続され混成集積回路が完成する
ものである。Thick film hybrid integrated circuits are widely used in electronic devices as a form of high-density circuit packaging. However, generally used thick film hybrid integrated circuits have conductor wiring formed in one or two layers on a ceramic substrate, and thick film resistors are arranged and formed between the conductor wiring. An example of this is shown in Figure 1.
In the figure, a conductor pattern 2 is placed on a ceramic board-1.
(by printing and firing), then an insulating layer 5 for two-layer wiring and an upper conductor 4 crossing this insulating layer are formed, and then a resistor 5 is formed between the conductor patterns to increase the thickness. The membrane substrate is completed. Thereafter, a chip component 6 such as a conductor is mounted on the conductor land 2' and connected to complete the hybrid integrated circuit.
このような構成の厚膜混成集積回路においては、抵抗体
パターンＳがセラミッーク基板１上に一層として形成さ
れているため、抵抗素子数が増えると、それに比例して
基板面積を広く必要とし、ｔた、チップ部品６を搭載す
る導体ランド２′も抵抗体５と同一面に形成されている
ので、チップ部品の搭載てきる数は抵抗体パターンにょ
シ制約を受け、実装密度が上げられないという欠点があ
る。In the thick-film hybrid integrated circuit having such a configuration, the resistor pattern S is formed as a single layer on the ceramic substrate 1, so as the number of resistor elements increases, the substrate area becomes proportionally larger, and t Furthermore, since the conductor land 2' on which the chip component 6 is mounted is also formed on the same surface as the resistor 5, the number of chip components that can be mounted is limited by the resistor pattern, making it impossible to increase the packaging density. There are drawbacks.
本発明の目的は、以上述べた欠点を解決するものであ〕
、厚ｌＩｉ混成集積回路の実装密度を高めることの出来
る厚膜多層基板を提供することにある。The object of the present invention is to solve the above-mentioned drawbacks.
An object of the present invention is to provide a thick film multilayer substrate that can increase the packaging density of thick lIi hybrid integrated circuits.
この発明の特徴とするところは、厚Ｈ抵抗体を絶縁層を
介して上下の二層に形成すると共に、上下の抵抗体がト
リミングによシ高精度な抵抗値が得られるようにし、歩
留よく生産できる厚膜多層基板を可能にすることである
。The features of this invention are that the thick H resistor is formed in two layers (upper and lower) with an insulating layer interposed in between, and the upper and lower resistors are trimmed to obtain a highly accurate resistance value. The objective is to enable thick film multilayer substrates that can be easily produced.
以下、本発明の一実施例を第２図によシ説明する６Ｍ２
図において、１はセラミック基板であり、この基板の上
に下部導体パターン１２・を印刷焼成によ多形成する。Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 6M2.
In the figure, 1 is a ceramic substrate, and a lower conductor pattern 12 is formed on this substrate by printing and firing.
次に、下部抵抗体１５を下部導体間に同じく印刷、焼成
によ多形成する。１３は下部導体と下部抵抗体を被覆す
る念めの絶縁層であ）、ガラス等で形成する。１４は絶
縁層上に形成した上部導体であり、下部導体と必要な個
所で接続が行われている。１７は上部導体間に形成され
友上部抵抗体であり、抵抗値のトリミングによシ削られ
る部分１８を点線で示し、この部分には下部導体、下部
−抗体は形成されていない、１６はチップ部品であ〕上
部導体ランド１４′に搭載、接続されるものである゛。Next, a lower resistor 15 is formed between the lower conductors by printing and firing in the same manner. Reference numeral 13 denotes an insulating layer for covering the lower conductor and the lower resistor), which is made of glass or the like. Reference numeral 14 denotes an upper conductor formed on the insulating layer, and is connected to the lower conductor at necessary locations. Reference numeral 17 indicates a companion upper resistor formed between the upper conductors, and a dotted line indicates a portion 18 that is removed by trimming the resistance value, and the lower conductor and lower antibody are not formed in this portion.16 is a chip. It is a component that is mounted and connected to the upper conductor land 14'.
このような構成の本実施例によれば、抵抗体は下部と上
部の二層に形成されておシ、上部抵抗体は、その抵抗ト
リミングが行われる部分を下部導体と下部抵抗体の無い
部分に配置されているので、上部抵抗体をレーザまたは
サンドブラストによシトリミングを行っても、下部の厚
膜配線を切断するような危険がなく、高精度な抵抗を得
ることが、できる、なお、下部抵抗体は絶縁層を形成す
る前にトリミングを行い精度を高めておくことができる
。According to this embodiment with such a configuration, the resistor is formed in two layers, the lower and upper layers, and the upper resistor has a portion where the resistance trimming is performed between the lower conductor and the portion without the lower resistor. Since the upper resistor is trimmed by laser or sandblasting, there is no danger of cutting the lower thick film wiring, and a highly accurate resistor can be obtained. The precision of the lower resistor can be improved by trimming it before forming the insulating layer.
本発明によれば、抵抗体が下部と上部の二層に形成され
るので、従来のように一層で形成する場−合と比べ単位
面積当シの抵抗体の実装密度が向上し集積度を高め、か
つセラミック基板を小形化できる効果がある。According to the present invention, since the resistor is formed in two layers, the lower and upper layers, the mounting density of the resistor per unit area is improved compared to the conventional case where the resistor is formed in a single layer, and the degree of integration is improved. This has the effect of making it possible to reduce the size of the ceramic substrate.
また、チップ部品は上部導体の上に搭載接続を行うこと
ができるので、下部抵抗体の上などを有効に利用できる
ようになり、従来あように抵抗パターンによる配置の制
約が無くなり実装密度を高めることができる。In addition, since chip components can be mounted and connected on top of the upper conductor, the area above the lower resistor can be used effectively, eliminating the conventional restrictions on placement due to resistor patterns and increasing packaging density. be able to.
従って１本発明によれば従来よシ大幅に実装密度を高め
られ、しかも抵抗を二層にしても歩留りよ〈生産ができ
る効果がある。Therefore, according to the present invention, the packaging density can be greatly increased compared to the conventional method, and even if the resistor is made of two layers, the yield can be improved.
第１図は従来の厚膜基板を示す縦断面図、９２図は本発
明の厚膜多層基板を示す縦断面図である。
１．１４−・・セラミック基板
２．１２°°・導体
３．１３・・・絶縁層
４．１４・・・上部導体
５ ・・・・・・抵抗体
１５ ・・・・・・下部抵抗体、１７・・・上部抵抗体
６．１６ ・・・≠ツブ部品
才 ｌ 図
り２図FIG. 1 is a longitudinal sectional view showing a conventional thick film substrate, and FIG. 92 is a longitudinal sectional view showing a thick film multilayer substrate of the present invention. 1.14- Ceramic substrate 2.12°° Conductor 3.13 Insulating layer 4.14 Upper conductor 5 Resistor 15 Lower resistor , 17... Upper resistor 6.16...≠Tub parts l Diagram 2
Claims (1)
形成し友後、絶縁体層を印刷、焼成によ膜形成して、下
部導体、下部抵抗体を被覆し、更に絶縁体層上に上部導
体、上部抵抗体を印刷、焼成によ膜形成する厚膜多層配
線基板において、上部抵抗体のトリミングされる部分の
下側には、下部導体および下部抵抗体が形成されていな
いことを特徴とする厚膜多層基板。A lower conductor and a lower resistor are formed on the insulating substrate by printing and firing, and then an insulating layer is formed by printing and firing to cover the lower conductor and lower resistor, and then on the insulating layer. A thick film multilayer wiring board in which an upper conductor and an upper resistor are formed by printing and firing, characterized in that the lower conductor and lower resistor are not formed below the trimmed portion of the upper resistor. Thick film multilayer substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56162841A JPS5864058A (en) | 1981-10-14 | 1981-10-14 | Thick multilayer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56162841A JPS5864058A (en) | 1981-10-14 | 1981-10-14 | Thick multilayer substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5864058A true JPS5864058A (en) | 1983-04-16 |
Family
ID=15762256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56162841A Pending JPS5864058A (en) | 1981-10-14 | 1981-10-14 | Thick multilayer substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5864058A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06200567A (en) * | 1992-12-01 | 1994-07-19 | Katsuya Hiraoka | Concrete secondary product and construction method using the product |
-
1981
- 1981-10-14 JP JP56162841A patent/JPS5864058A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06200567A (en) * | 1992-12-01 | 1994-07-19 | Katsuya Hiraoka | Concrete secondary product and construction method using the product |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4539622A (en) | Hybrid integrated circuit device | |
| JPS5864058A (en) | Thick multilayer substrate | |
| JP3913094B2 (en) | Thick film multilayer wiring board | |
| JPS5841800B2 (en) | Method of forming ceramic multilayer substrate | |
| JPH01298796A (en) | Hybrid integrated circuit | |
| JPS59119794A (en) | Hybrid thick film integrated circuit | |
| JPH0548272A (en) | Printed circuit board | |
| JPH02265297A (en) | Manufacture of thick film multilayered substrate | |
| JPS63253659A (en) | Thick-film hybrid integrated circuit device | |
| JPH053160B2 (en) | ||
| JPH0714111B2 (en) | Multilayer substrate with built-in capacitor | |
| JPS54158884A (en) | Manufacture of semiconductor device | |
| JPH0134337Y2 (en) | ||
| JPS5843242Y2 (en) | printed wiring board | |
| JPS59161675U (en) | Multilayer thick film circuit board | |
| JPS63205901A (en) | Hybrid integrated circuit substrate | |
| JPH0645761A (en) | Short circuit forming device | |
| JPH0138924Y2 (en) | ||
| JPH0219976B2 (en) | ||
| JPH10190302A (en) | High frequency circuit board and capacity adjustment method | |
| JP2743524B2 (en) | Hybrid integrated circuit device | |
| JPS62277784A (en) | Printed board | |
| JPS60208887A (en) | Thick film multilayer circuit substrate | |
| JPS6155931A (en) | Manufacture of thick film hybrid integrated circuit device | |
| JPS60194557A (en) | Hybrid ic |