JPS5863192A - Method of forming pattern - Google Patents
Method of forming patternInfo
- Publication number
- JPS5863192A JPS5863192A JP16183081A JP16183081A JPS5863192A JP S5863192 A JPS5863192 A JP S5863192A JP 16183081 A JP16183081 A JP 16183081A JP 16183081 A JP16183081 A JP 16183081A JP S5863192 A JPS5863192 A JP S5863192A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- photoresist
- pattern
- ferrite
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 22
- 229910000859 α-Fe Inorganic materials 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 14
- 239000004020 conductor Substances 0.000 description 7
- 239000002223 garnet Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はフェライト基板上へ薄膜回路パターンを形成す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming thin film circuit patterns on ferrite substrates.
第１図に従来方法によりその表面にパターンが形成され
たフェライト基板の断面を示す。FIG. 1 shows a cross section of a ferrite substrate with a pattern formed on its surface by a conventional method.
従来、０ａ−Ｖ−Ｇｄ系ガーネット、Ｙ−Ａ４系ガーネ
ット、Ｙガーネット、０ａ−Ｙ−Ｇｄ系ガーネット、Ｌ
ｌ系ガーネットと呼ばれているフェライト基板では、そ
の表面のメタライズ化は一般的に真空蒸着の場合はＮｉ
０ｒ＋Ａｕを、無電解メッキの場合はＮｉ 、Ｏｕ等の
金属膜を被着し、その上に導電性の良い金属を電解メッ
キすることにより、行なわれている。Conventionally, 0a-V-Gd series garnet, Y-A4 series garnet, Y garnet, 0a-Y-Gd series garnet, L
For ferrite substrates called l-based garnet, the surface is generally metallized using Ni when vacuum evaporated.
In the case of electroless plating, a metal film of Ni, O, etc. is deposited on 0r+Au, and a highly conductive metal is electrolytically plated thereon.
しかし、この方法ではフェライト基板材料は、アルミナ
セラミックス基板と比較しフェライトのグレンサイズが
一様に整っていないことによりピンホールが多く発生す
るため、フェライト基板と金属膜の密着性が弱いという
欠点があった。However, with this method, compared to alumina ceramic substrates, ferrite substrate materials have the disadvantage of weaker adhesion between the ferrite substrate and the metal film due to the uneven grain size of the ferrite, which causes more pinholes. there were.
本発明の目的はこれら問題を解決するためになされたも
ので、その目的とするところはフェライト基板と導体膜
の密着性を改善した回路基板のパターン形成方法を提供
することにある。The object of the present invention was made to solve these problems, and the object thereof is to provide a method for forming a pattern on a circuit board that improves the adhesion between a ferrite substrate and a conductor film.
前記目的を達成するために本発明によるパターン形成方
法はフェライト基板上に絶縁膜を被着した後、前記絶縁
膜上に導体膜を被着し、さらに前記導体膜上にフォトレ
ジストを塗布して所定の部分のフォトレジストを除去し
、この除去した部分に回路パターンとなる電解メッキを
施こした後、前記フォトレジストと前記回路パターン以
外の導体膜を除去する工程を含んでいる。In order to achieve the above object, a pattern forming method according to the present invention includes depositing an insulating film on a ferrite substrate, depositing a conductive film on the insulating film, and further coating a photoresist on the conductive film. The method includes the steps of removing a predetermined portion of the photoresist, electrolytically plating the removed portion to form a circuit pattern, and then removing the photoresist and the conductive film other than the circuit pattern.
以下、図面に従って本発明方法を詳細に説明する。Hereinafter, the method of the present invention will be explained in detail with reference to the drawings.
第２図〜第７図は本発明の詳細な説明するだめの図で、
各工程におけるフェライト基板を示したものである。Figures 2 to 7 are diagrams for detailed explanation of the present invention.
The ferrite substrate in each process is shown.
まずフェライト基板ｌの面にスパッタリング方法により
絶縁層３を被着する。この工程で、被着されるのは例え
ば５１０２で、その厚さは１０００Ａ程度である。First, an insulating layer 3 is deposited on the surface of a ferrite substrate 1 by sputtering. In this step, for example, 5102 is deposited, and its thickness is about 1000A.
次にその上に二層からなる導体層４を形成した後、片面
のみフォトレジストを塗布する。そして所定の位置、す
なわちパターンを形成すべき位置のフォトレジストを取
除いた後、その取除いた位置に電解メッキにより導体膜
６を形成するＯ
さらにフォトレジスト５、導体パターンとなる部分を除
く導体層、絶縁層を除去する。Next, a two-layer conductor layer 4 is formed thereon, and then a photoresist is applied to only one side. After removing the photoresist at a predetermined position, that is, the position where a pattern is to be formed, a conductor film 6 is formed at the removed position by electrolytic plating. layer, remove the insulating layer.
以上により、フェライト基板上には所定の回路パターン
が完成する。Through the above steps, a predetermined circuit pattern is completed on the ferrite substrate.
フェライト基板１上では絶縁層３を介して上層の金属膜
が形成されているため密着性が良くなる。Since the upper metal film is formed on the ferrite substrate 1 with the insulating layer 3 interposed therebetween, the adhesion is improved.
以上説明したように本発明によるパターン形成方法によ
ればフェライトを基板材料とする非可逆回路装置の製造
においてフェライト基板と導体膜の密着性を強化できる
。As explained above, according to the pattern forming method of the present invention, it is possible to strengthen the adhesion between a ferrite substrate and a conductive film in the production of a non-reciprocal circuit device using ferrite as a substrate material.
第１図は従来のパターン形成の断面図である。
第２〜７図は本発明によるパターン形成方法の一実施例
を説明するための図で、第２図は絶縁基板の断面図、第
３図は基板上に絶縁膜を付着した断面図、第４図は基板
上に導体膜を付着した断面図、第５図は基板上にフォト
レジスト処理をした断面図、第６図は基板上に電解メッ
キをした断面図、第７図は基板上にパターン形成した断
面図である。
１・・・絶縁基板 ２・・・導体層３・・・絶
縁層 ４・・・導体層５・・・フォトレジス
ト ６・・・導体層特許出願人 日本電気株式会社
代理人 弁理士 井 ノ ロ 壽FIG. 1 is a cross-sectional view of conventional pattern formation. 2 to 7 are diagrams for explaining one embodiment of the pattern forming method according to the present invention, in which FIG. 2 is a cross-sectional view of an insulating substrate, FIG. 3 is a cross-sectional view of an insulating film adhered on a substrate, and FIG. Figure 4 is a cross-sectional view of a conductor film adhered to a substrate, Figure 5 is a cross-sectional view of a substrate treated with photoresist, Figure 6 is a cross-sectional view of electrolytic plating on a substrate, and Figure 7 is a cross-sectional view of a conductive film applied to a substrate. FIG. 3 is a cross-sectional view of a pattern formed. 1... Insulating substrate 2... Conductor layer 3... Insulating layer 4... Conductor layer 5... Photoresist 6... Conductor layer patent applicant NEC Corporation representative Patent attorney Inoro Hisashi
Claims (1)
に導体膜を被着し、さらに前記導体膜上にフォトレジス
トを塗布して所定の部分のフォトレジストを除去し、と
の除去した部分に回路パターンとなる電解メッキを施と
した後、前記フォトレジストと前記回路パターン以外の
導体被膜を除去する工程を含む回路基板のパターン形成
方法。After depositing an insulating film on a ferrite substrate, a conductive film is deposited on the insulating film, a photoresist is further applied on the conductive film, and a predetermined portion of the photoresist is removed. A method for forming a pattern on a circuit board, comprising the step of electrolytically plating a portion to form a circuit pattern, and then removing the photoresist and the conductive film other than the circuit pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16183081A JPS5863192A (en) | 1981-10-09 | 1981-10-09 | Method of forming pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16183081A JPS5863192A (en) | 1981-10-09 | 1981-10-09 | Method of forming pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5863192A true JPS5863192A (en) | 1983-04-14 |
Family
ID=15742721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16183081A Pending JPS5863192A (en) | 1981-10-09 | 1981-10-09 | Method of forming pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5863192A (en) |
-
1981
- 1981-10-09 JP JP16183081A patent/JPS5863192A/en active Pending
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