JPS5863141A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5863141A
JPS5863141A JP56161726A JP16172681A JPS5863141A JP S5863141 A JPS5863141 A JP S5863141A JP 56161726 A JP56161726 A JP 56161726A JP 16172681 A JP16172681 A JP 16172681A JP S5863141 A JPS5863141 A JP S5863141A
Authority
JP
Japan
Prior art keywords
output
semiconductor integrated
integrated circuit
resistance
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56161726A
Other languages
Japanese (ja)
Other versions
JPH0115139B2 (en
Inventor
Shinji Tanaka
慎二 田中
Isao Yoshida
功 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP56161726A priority Critical patent/JPS5863141A/en
Publication of JPS5863141A publication Critical patent/JPS5863141A/en
Publication of JPH0115139B2 publication Critical patent/JPH0115139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To manufacture the semiconductor integrated circuit device including output terminal with less resistance without sensing the resistance generated naturally by a method wherein the conductive line is provided between bonding pad of semiconductor integrated circuit element and external terminal making use of small metallic wire. CONSTITUTION:The overall semiconductor integrated circuit device including DC voltage stabilizing circuit is indicated by equivalent circuit in the diagram. As evident in the diagram, external terminal 3 leading output is connected to bonding pad 3' connecting to emitter of output transistor Q1 as well as to bonding pad 3'' connecting to input point of error amplifier A comprising detection transistor as usual to constitute the negative feedback circuit. Consequently the effect of resistance Rw in the conductive line becomes negligible while the output resistance may be reduced down to 10mOMEGA or less even if small metallic wire with diameter of 50mum or less is utilized.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置特に、直流電圧安定化回路
等の負帰還を利用して出力端子の出力抵抗を低く抑えた
回路部を集積化した半導体集積回路装置に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device that integrates a circuit section that uses negative feedback such as a DC voltage stabilization circuit to suppress the output resistance of an output terminal. It is.

出力端子の出力抵抗を低く抑える目的で負帰還を利用す
る回路構成を採り、これを単一の半導体基体内へ集積化
した半導体集積回路装置に於ては、集積化される回路部
をみる限り、その出力発生点は所期の目的を達成しうる
低インピーダンスとされている。しかしながら、半導体
集積回路装置の実装に際して不可欠である半導体基体上
のポンディングパッドから外部導出端子までの通電路は
、上記の負帰還路には含まれていない。このため、かか
る通電路の抵抗分すなわち、ポンディングパッドと外部
導出端子との間を接続する金属細線の抵抗分ならびにポ
ンディングパッドおよび外部導出端子と金属細線との間
の接触抵抗によりもたらされる抵抗分等が半導体基体上
のポンディングパッドまでの出力抵抗に単純に加算され
てしまい、完成した半導体集積回路装置の外部に導出さ
れた出力端子における出力抵抗を低くするのには限界が
あった。
In a semiconductor integrated circuit device that employs a circuit configuration that utilizes negative feedback for the purpose of keeping the output resistance of the output terminal low, and integrates this into a single semiconductor substrate, as far as the integrated circuit section is concerned, , the output generation point has a low impedance that can achieve the intended purpose. However, the current-carrying path from the bonding pad on the semiconductor substrate to the external lead-out terminal, which is essential when mounting a semiconductor integrated circuit device, is not included in the above-mentioned negative feedback path. Therefore, the resistance of the current carrying path, that is, the resistance of the thin metal wire connecting the bonding pad and the external lead-out terminal, and the resistance caused by the contact resistance between the bonding pad, the external lead-out terminal, and the thin metal wire. This is simply added to the output resistance up to the bonding pad on the semiconductor substrate, and there is a limit to lowering the output resistance at the output terminal led to the outside of the completed semiconductor integrated circuit device.

第1図は上記の内容を直流電圧安定化回路の例で示した
もので、半導体集積回路装置全体の等価回路を記しであ
る。実線の枠内は半導体集積回路装置全体を、破線の枠
内は半導体集積回路素子を示し、また図中1〜3は半導
体集積回路装置の外部端子を、1′〜3′は半導体集積
回路素子のポンディングパッド部を、さらにRwは上述
した通電路の抵抗分を示す。
FIG. 1 shows the above content using an example of a DC voltage stabilizing circuit, and shows an equivalent circuit of the entire semiconductor integrated circuit device. The solid line frame indicates the entire semiconductor integrated circuit device, and the dashed line frame indicates the semiconductor integrated circuit element. In the figure, 1 to 3 indicate external terminals of the semiconductor integrated circuit device, and 1' to 3' indicate the semiconductor integrated circuit element. Further, Rw represents the resistance of the above-mentioned current-carrying path.

この等価回路図に於て、半導体集積回路素子の出力点で
あるポンディングパッド部3′における出力抵抗は、帰
還がない状態での出力トランジスタQ1 のエミッタに
おける出力抵抗をZ□とし、負帰還のループゲインをT
とすると、Zo/Tで表わされる。このため、出力の発
生する外部端子3における出力抵抗ZOUTは次式で表
わされる。
In this equivalent circuit diagram, the output resistance at the bonding pad portion 3', which is the output point of the semiconductor integrated circuit element, is defined as Z□, which is the output resistance at the emitter of the output transistor Q1 in the absence of feedback, and Set the loop gain to T
Then, it is expressed as Zo/T. Therefore, the output resistance ZOUT at the external terminal 3 where the output is generated is expressed by the following equation.

上式でも明らかな通り、zoUTを小さくするために出
力トランジスタQ1 のエミッタにおける出力抵抗zO
を小さくし、一方、ループゲインTを大きくしても、通
電路の抵抗分Rwが残ってしまう。
As is clear from the above equation, in order to reduce zoUT, the output resistance zO at the emitter of the output transistor Q1
Even if the loop gain T is made small and the loop gain T is made large, the resistance Rw of the current-carrying path remains.

実際の直流電圧安定化回路の例によると、Z()= 2
09.  T = 80 d B 、  RW = 5
0 mΩ(Rwは線径が5oμmのAu線自体の抵抗分
ならびにAu線とポンディングパッドならびに外部端子
との接続により生じる接触抵抗の和)程度の値を持ち、
これらを第1式に代入すると出力抵抗2OUTは となり、はとんどRwで出力抵抗値が決定されているこ
とは明らかである。ところで、直流電圧安定化回路にお
いては、出力端子の出力抵抗として数十mΩ以下の値を
要求されることが多々あり、従来は、第1図で示した通
電路の抵抗分Rwを小さくするために金属細線として線
径が100μmを越えるものを使用することによりこの
要求を満たしてはいるが、この金属細線は通常高価なA
u線であるため、半導体集積回路装置のコストの高騰を
招き、また線径の増大によシボンディングパッド面積を
拡げる必要が生じ、素子構造の変更をもたらす不都合も
生じる。
According to the example of an actual DC voltage stabilization circuit, Z()=2
09. T = 80dB, RW = 5
It has a value of about 0 mΩ (Rw is the sum of the resistance of the Au wire itself with a wire diameter of 5 μm and the contact resistance caused by the connection between the Au wire and the bonding pad and external terminal),
When these are substituted into the first equation, the output resistance 2OUT becomes, and it is clear that the output resistance value is mostly determined by Rw. By the way, in DC voltage stabilization circuits, the output resistance of the output terminal is often required to have a value of several tens of mΩ or less. This requirement is met by using thin metal wires with a wire diameter of over 100 μm, but these thin metal wires are usually expensive A.
Since it is a U-ray, the cost of the semiconductor integrated circuit device increases, and as the wire diameter increases, it becomes necessary to increase the area of the bonding pad, resulting in the inconvenience of changing the element structure.

1 本発明は、かかる問題点の排除を意図してなされたもの
で、出力端子の出力抵抗を負帰還回路を利用して低く抑
えた半導体集積回路装置に於て、通電路の抵抗分による
出力抵抗の増大とはほぼ無関係な低い出力抵抗の出力端
子を具備する半導体集積回路装置を提供するものである
1 The present invention has been made with the intention of eliminating such problems, and in a semiconductor integrated circuit device in which the output resistance of the output terminal is kept low by using a negative feedback circuit, the output due to the resistance of the current carrying path is reduced. The present invention provides a semiconductor integrated circuit device having an output terminal with a low output resistance that is almost unrelated to an increase in resistance.

本発明の半導体集積回路装置に於ては、出力をとり出す
外部端子に対して、出力トランジスタの出力電極に繋が
るポンディングパッドを第1の金属細線により接続する
とともに、さらに検出トランジスタの入力電極に繋がる
ポンプイングツくラドを設け、このポンディングパッド
を第2の金属細線により接続することによって、半導体
基体内に作り込まれた出力トランジスタ、第1の金属細
線。
In the semiconductor integrated circuit device of the present invention, the bonding pad connected to the output electrode of the output transistor is connected to the external terminal from which the output is taken out by a first thin metal wire, and the bonding pad is further connected to the input electrode of the detection transistor. An output transistor and a first thin metal wire are fabricated in a semiconductor substrate by providing a pumping pad connected to the pad and connecting this pumping pad with a second thin metal wire.

外部端子、第2の金属細線ならびに出力トランジスタと
同様半導体基体内へ作シ込まれた検出トランジスタで負
帰還路を構成がとられている。
A negative feedback path is constituted by an external terminal, a second thin metal wire, and a detection transistor implanted into the semiconductor substrate like the output transistor.

本発明の一実施例を、従来例との対比を明確にする意味
で直流電圧安定化回路を取り上げて説明する。第2図は
第1図と同様直流電圧安定化回路を含む半導体集積回路
装置全体を等価回路で示しだものである。図でも明らか
な通り、出力をとり出す外部端子3は従来と同様出力ト
ランジスタQ1のエミッタに繋がるポンディングパッド
3′へ接続されるとともに検出トランジスタで構成され
る誤差増幅器Aの入力点に繋るポンディングパッド3′
にも接続され、上記の負帰還回路が構成されている。こ
の結果、このような回路構成の下での外部端子3の出力
抵抗ZOUTは次式であられされる。
An embodiment of the present invention will be described by taking up a DC voltage stabilizing circuit in order to clearly compare it with a conventional example. Similar to FIG. 1, FIG. 2 shows an equivalent circuit of the entire semiconductor integrated circuit device including a DC voltage stabilizing circuit. As is clear from the figure, the external terminal 3 from which the output is taken out is connected to a bonding pad 3' connected to the emitter of the output transistor Q1, as in the conventional case, and is also connected to a bonding pad 3' connected to the input point of the error amplifier A consisting of a detection transistor. Ding pad 3'
is also connected to constitute the above-mentioned negative feedback circuit. As a result, the output resistance ZOUT of the external terminal 3 under such a circuit configuration is given by the following equation.

第1図の回路と比較すると、通電路の抵抗分Rwの出力
抵抗ZoUTへの影響はループケイン分の1となる。第
2式に(1)式と同様な数値を代入するととなシ、その
差は歴然としている。この例によればZoとTでほとん
どZOUTが決まシ、通電路の抵抗分RWの影響は無視
できる程度に小さい。また、10fflΩ以下の出力抵
抗も線径が60μm以下の細い金属細線の使用の下でも
うろことができる。
Compared to the circuit shown in FIG. 1, the influence of the resistance Rw of the current-carrying path on the output resistance ZoUT is 1 of the loop Caine. When the same numerical values as in equation (1) are substituted into the second equation, the difference is obvious. According to this example, ZOUT is almost determined by Zo and T, and the influence of the resistance RW of the current-carrying path is so small that it can be ignored. Further, an output resistance of 10 fflΩ or less can be achieved even when a thin metal wire with a wire diameter of 60 μm or less is used.

以上説明したところから明らかなように、本発明によれ
ば、半導体集積回路素子のポンディングパッドと外部端
子間に通電路を付与するだめの金属細線によって必然的
に付与される抵抗分を意識することなく低い出力抵抗の
出力端子をもつ半導体集積回路装置を実現することがで
きる。
As is clear from the above explanation, according to the present invention, it is possible to take into account the resistance inevitably imparted by the thin metal wire that serves to provide a conductive path between the bonding pad of the semiconductor integrated circuit element and the external terminal. Therefore, it is possible to realize a semiconductor integrated circuit device having an output terminal with low output resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は直流電圧安定化回路を集積化した従来の半導体
集積回路装置全体の等価回路図、第2図は直流電圧安定
化回路を集積化した本発明の一実施例にかかる半導体集
積回路装置全体の等価回路図である。 1・・・・・・直流電圧安定化回路入力用外部端子、1
′・・・・・・直流電圧安定化回路入力用ポンディング
パッド、2・・・・・・共通外部端子、2′・・・・・
・共通外部端子に繋がるポンディングパッド、3・・・
・・・出力用外部端子、3′・・・・・・出力用外部端
子に繋がるボンディング“−1,。 クソド、3′・・・・・・誤差増幅器の入力に繋がるボ
ンデ・・・・・導電路の抵抗分。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図
FIG. 1 is an equivalent circuit diagram of the entire conventional semiconductor integrated circuit device in which a DC voltage stabilization circuit is integrated, and FIG. 2 is a semiconductor integrated circuit device according to an embodiment of the present invention in which a DC voltage stabilization circuit is integrated. FIG. 2 is an overall equivalent circuit diagram. 1... External terminal for DC voltage stabilization circuit input, 1
'...Bonding pad for DC voltage stabilization circuit input, 2...Common external terminal, 2'...
・Ponding pad connected to common external terminal, 3...
...Output external terminal, 3'...Bonding "-1," connected to the output external terminal. Damn, 3'...Bonde connected to the input of the error amplifier... Resistance of conductive path. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路基板内に作り込まれた出力トランジスタ
の出力端子に繋るボンディングパットt−第1の導電接
続手段を介して出力用外部導出端子へ接続するとともに
、前記半導体集積回路基板内に作り込まれた検出用トラ
ンジスタの入力端子に繋がるポンディングパッドを設け
、同ポンディングパッドを第2の導電接続手段を介して
前記出力用外部導出端子へ接続し、前記両トランジスタ
、第1および第2の導電接続手段および出力用外部導出
端子を含む負帰還路を形成して出力用外部導出端子の出
力抵抗を低抵抗値に抑制したことを特徴とする半導体集
積回路装置。
A bonding pad t connected to an output terminal of an output transistor built in the semiconductor integrated circuit board - connected to an output external lead terminal via the first conductive connection means, and also connected to the output terminal formed in the semiconductor integrated circuit board. A bonding pad connected to the input terminal of the detected transistor is provided, and the bonding pad is connected to the output external lead terminal via a second conductive connection means, and both the transistors, the first and second A semiconductor integrated circuit device characterized in that a negative feedback path including a conductive connection means and an external output terminal is formed to suppress the output resistance of the external output terminal to a low resistance value.
JP56161726A 1981-10-09 1981-10-09 Semiconductor integrated circuit device Granted JPS5863141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56161726A JPS5863141A (en) 1981-10-09 1981-10-09 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56161726A JPS5863141A (en) 1981-10-09 1981-10-09 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5863141A true JPS5863141A (en) 1983-04-14
JPH0115139B2 JPH0115139B2 (en) 1989-03-15

Family

ID=15740711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56161726A Granted JPS5863141A (en) 1981-10-09 1981-10-09 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5863141A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525228A (en) * 1975-07-02 1977-01-14 Hitachi Ltd Interrupt priority control method of communication control device
JPS5530210A (en) * 1978-08-25 1980-03-04 Hitachi Ltd Transistor amplifier circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525228A (en) * 1975-07-02 1977-01-14 Hitachi Ltd Interrupt priority control method of communication control device
JPS5530210A (en) * 1978-08-25 1980-03-04 Hitachi Ltd Transistor amplifier circuit

Also Published As

Publication number Publication date
JPH0115139B2 (en) 1989-03-15

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