JPH05259322A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05259322A JPH05259322A JP4051185A JP5118592A JPH05259322A JP H05259322 A JPH05259322 A JP H05259322A JP 4051185 A JP4051185 A JP 4051185A JP 5118592 A JP5118592 A JP 5118592A JP H05259322 A JPH05259322 A JP H05259322A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal plate
- temperature
- package
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
温度制御を必要とする半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device requiring temperature control.
【０００２】[0002]
【従来の技術】従来の半導体装置は、抵抗の温度特性
（数１００ｐｐｍ〜数１０００ｐｐｍ）やトランジスタ
のＶBFの温度特性（２ｍＶ／℃）あるいは増幅率ｈFEの
温度特性などの条件を考慮して設計されている。また、
半導体装置の使用温度範囲が狭い範囲に制限されている
場合は、恒温槽に半導体装置を入れて温度コントロール
している。2. Description of the Related Art In a conventional semiconductor device, a temperature characteristic of resistance (several hundred ppm to several thousand ppm), a temperature characteristic of V BF of a transistor (2 mV / ° C.), a temperature characteristic of an amplification factor h FE , etc. are considered. Is designed. Also,
When the operating temperature range of the semiconductor device is limited to a narrow range, the temperature is controlled by putting the semiconductor device in a constant temperature bath.
【０００３】図２はかかる従来の一例を示す恒温槽を用
いた半導体装置の斜視図である。図２に示すように、従
来の半導体装置１２は使用温度範囲を狭く指定されてい
るとき、恒温槽１０に入れて使用する。この半導体装置
１２はコンデンサ１３や抵抗１４と共に基板１１上に搭
載され、恒温槽１０内で温度コントロールされる。FIG. 2 is a perspective view of a semiconductor device using a constant temperature oven showing such a conventional example. As shown in FIG. 2, the conventional semiconductor device 12 is used by being put in the constant temperature bath 10 when the operating temperature range is specified to be narrow. The semiconductor device 12 is mounted on the substrate 11 together with the capacitor 13 and the resistor 14, and the temperature is controlled in the constant temperature bath 10.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の半導体
装置は、各種の温度特性を考慮した設計をしなければな
らないので、設計の自由度が制限されるという欠点があ
る。The conventional semiconductor device described above has a drawback that the degree of freedom in design is limited because it must be designed in consideration of various temperature characteristics.
【０００５】また、従来の半導体装置はその使用温度範
囲を狭い範囲に制限されているとき、恒温槽に入れて温
度コントロールをしなければならない。そのため、実装
上の形状が大きくなるという欠点がある。Further, when the temperature range of the conventional semiconductor device is limited to a narrow range, the semiconductor device must be placed in a constant temperature bath for temperature control. Therefore, there is a drawback that the mounting shape becomes large.
【０００６】本発明の目的は、かかる設計の自由度を増
すとともに、使用温度範囲が制限されたときにも恒温槽
を不要にする半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that increases the degree of freedom in design and eliminates the need for a constant temperature bath even when the operating temperature range is limited.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
複数の端子を備えたパッケージと、前記パッケージ内に
搭載し且つペルチェ効果を持つように接合した第１およ
び第２の金属板と、前記第２の金属板上に搭載する温度
センサ内蔵の半導体チップとを有して構成される。The semiconductor device of the present invention comprises:
A package having a plurality of terminals, first and second metal plates mounted in the package and joined so as to have a Peltier effect, and a semiconductor chip containing a temperature sensor mounted on the second metal plate. And is configured.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１（ａ），（ｂ）はそれぞれ本発明の一
実施例を示す半導体装置の平面図およびその断面図であ
る。図１（ａ），（ｂ）に示すように、本実施例は箱形
のパッケージ１に第１の金属板２と第２の金属板３とを
固定し、その第２の金属板３の上に半導体チップ４を搭
載する。この半導体チップ４は温度センサを内蔵してい
る。しかも、半導体チップ４はボンディングワイヤ５に
より、パッケージ１の端子８Ａ〜８Ｆに結合された電極
６，７と接続される。かかる半導体装置において、半導
体チップ４に内蔵した温度センサにより、電極６と電極
７を用い金属接合部９に電流を流すと、ペルチェ効果を
利用した温度コントロールを実現できる。従って、半導
体装置の動作温度を可変に出来、更にある一定温度の設
定制御が可能になる。Embodiments of the present invention will now be described with reference to the drawings. 1A and 1B are a plan view and a sectional view of a semiconductor device showing an embodiment of the present invention, respectively. As shown in FIGS. 1A and 1B, in this embodiment, the first metal plate 2 and the second metal plate 3 are fixed to the box-shaped package 1, and the second metal plate 3 is fixed. The semiconductor chip 4 is mounted on top. The semiconductor chip 4 has a built-in temperature sensor. Moreover, the semiconductor chip 4 is connected by the bonding wires 5 to the electrodes 6 and 7 coupled to the terminals 8A to 8F of the package 1. In such a semiconductor device, when a temperature sensor built in the semiconductor chip 4 causes a current to flow through the metal bonding portion 9 using the electrodes 6 and 7, temperature control using the Peltier effect can be realized. Therefore, the operating temperature of the semiconductor device can be made variable, and the setting control of a certain constant temperature becomes possible.
【０００９】[0009]
【発明の効果】以上説明したように、本発明の半導体装
置は、ペルチェ効果を持つように二種類の金属板を接合
し、その接合した金属板上に温度センサ内蔵の半導体チ
ップを設置して温度コントロールをするので、設計の自
由度を増すとともに、恒温槽を不要にできるという効果
がある。As described above, in the semiconductor device of the present invention, two kinds of metal plates are joined so as to have a Peltier effect, and a semiconductor chip with a built-in temperature sensor is installed on the joined metal plates. Since the temperature is controlled, the degree of freedom in design is increased and the constant temperature bath can be eliminated.
【図１】本発明の一実施例を示す半導体装置の平面およ
び断面を表わす図である。FIG. 1 is a diagram showing a plane and a cross section of a semiconductor device according to an embodiment of the present invention.
【図２】従来の一例を示す恒温槽を用いた半導体装置の
斜視図である。FIG. 2 is a perspective view of a semiconductor device using a constant temperature bath showing a conventional example.
１ パッケージ ２ 第１の金属板 ３ 第２の金属板 ４ 半導体チップ ５ ボンディングワイヤ ６，７ 電極 ８，８Ａ〜８Ｆ 端子 ９ 金属接合部 1 Package 2 1st metal plate 3 2nd metal plate 4 Semiconductor chip 5 Bonding wire 6,7 Electrode 8,8A-8F terminal 9 Metal junction part
Claims (1)
パッケージ内に搭載し且つペルチェ効果を持つように接
合した第１および第２の金属板と、前記第２の金属板上
に搭載する温度センサ内蔵の半導体チップとを有するこ
とを特徴とする半導体装置。1. A package provided with a plurality of terminals, first and second metal plates mounted in the package and joined so as to have a Peltier effect, and a temperature for mounting on the second metal plate. A semiconductor device having a semiconductor chip with a built-in sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4051185A JPH05259322A (en) | 1992-03-10 | 1992-03-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4051185A JPH05259322A (en) | 1992-03-10 | 1992-03-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05259322A true JPH05259322A (en) | 1993-10-08 |
Family
ID=12879803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4051185A Withdrawn JPH05259322A (en) | 1992-03-10 | 1992-03-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05259322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000002270A (en) * | 1998-06-18 | 2000-01-15 | 김영환 | Temperature controller using peltier effect |
-
1992
- 1992-03-10 JP JP4051185A patent/JPH05259322A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000002270A (en) * | 1998-06-18 | 2000-01-15 | 김영환 | Temperature controller using peltier effect |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |