JPS5862932A - Analog switch circuit - Google Patents

Analog switch circuit

Info

Publication number
JPS5862932A
JPS5862932A JP16161681A JP16161681A JPS5862932A JP S5862932 A JPS5862932 A JP S5862932A JP 16161681 A JP16161681 A JP 16161681A JP 16161681 A JP16161681 A JP 16161681A JP S5862932 A JPS5862932 A JP S5862932A
Authority
JP
Japan
Prior art keywords
signal
paths
switch circuit
analog switch
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16161681A
Other languages
Japanese (ja)
Inventor
Isao Sagusa
佐草 功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16161681A priority Critical patent/JPS5862932A/en
Publication of JPS5862932A publication Critical patent/JPS5862932A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a circuit of low distortion factor, by branching an analog input signal into a plurality of parallel paths and controlling an analog switch circuit inserted at the middle point of the paths. CONSTITUTION:An input signal (a) applied to an input terminal 1 is branched into parallel paths (a), (b) and (c) and analog switch circuits 2, 3 are inserted between resistors R1, R2, and R'1, R'2 of the paths (a), (b). A joining point (d) of the paths (a), (b) and (c) is connected to a - signal input terminal of an operational amplifier 7 and the output of the amplifier 7 is fed back to the - signal input terminal via a resistor R4. The circuits 2, 3 are controlled with a control signal from control terminals 5, 6 and 5', 6'. Through the combination of the applied time of the control signal, the synthesized value of the signal of the joining point (d) of the paths (a), (b), and (c) is changed to compensate the deterioration in distortion characteristics due to diodes and to decrease the distortion factor of the analog switch circuits.

Description

【発明の詳細な説明】 本発明は、ひずみ率の低下を図ったアナログスイッチ回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog switch circuit designed to reduce distortion.

従来、アナログスイッチ回路としては、信号経路に直列
にスイッチ回路を挿入し、第1図のように構成して用い
られる場合が多かった。同図において、11は信号の入
力端子、12はスイッチ回路で、互に逆接続された2組
のダイオード対り、。
Conventionally, analog switch circuits have often been used with a switch circuit inserted in series in a signal path and configured as shown in FIG. In the figure, 11 is a signal input terminal, 12 is a switch circuit, and has two pairs of diodes connected in opposite directions.

D2と”3 e ”4によりなる。14は出力端子、1
621−・ 及び16は前記ダイオード対D1.D、と”3 e ”
4のそれぞれの制御端子、17は演算増幅器、”IL 
* Rbは抵抗である。
It consists of D2 and "3 e" 4. 14 is the output terminal, 1
621-. and 16 are the diode pair D1. D, and “3 e”
4, each control terminal 17 is an operational amplifier, "IL
*Rb is resistance.

第2図は制御端子16及び16への制御信号のタイミン
グ関係を示す図である。制御信号は正の電源電圧(V+
)と負の電源電圧(V−)−の間で切換るパルスで、互
に逆相と汝っている。このため期゛間〒1には、ダイオ
ードDl#D、はいずれもON、従ってスイッチ回路1
2もOR4!:なり、逆に期間T2にはOFFとなる。
FIG. 2 is a diagram showing the timing relationship of control signals to control terminals 16 and 16. The control signal is connected to the positive supply voltage (V+
) and the negative power supply voltage (V-)-, which are in opposite phase to each other. Therefore, during period 〒1, both diodes Dl#D are ON, and therefore the switch circuit 1
2 is also OR4! : and, conversely, becomes OFF during period T2.

入力端子11よ少入力されたアナログ信号は制御信号に
よシ次々とON −OFFスイッチングされて出力端子
14に出力が得られる。一般にダイオードDI ”””
4はONの場合にスイッチング電流が流れ、その入出力
特性は非直性を有するため、従ってON抵抗も入力信号
のレベルやダイオード特性の変動、その他の原因により
変化し、ひずみ率としては一40!B程度しか期待でき
ないのが実情である。しかしこの値は低ひずみ率特性が
要求される場合には不十分なものであった。
The analog signals input to the input terminal 11 are sequentially switched ON and OFF according to the control signal, and an output is obtained at the output terminal 14. Generally diode DI “””
4, a switching current flows when it is ON, and its input/output characteristics have non-linearity, so the ON resistance also changes depending on the input signal level, fluctuations in diode characteristics, and other causes, and the distortion rate is -40 ! The reality is that we can only expect a grade of B. However, this value was insufficient when low strain rate characteristics were required.

本発明は上記した従来の問題点を除去したものであって
1、以下にその一実施例と共に説明する。
The present invention eliminates the above-mentioned conventional problems, and will be described below along with one embodiment thereof.

第3図〜第6図は、正弦波電圧をスイッチングして階段
波波−として出力する回路に応用した実施例であって、
第3図はその回路図、第4図は入出力電圧の波形図、第
6図はスイッチ回路の切換えのタイミング関係を示す説
明図である。第3図において、2は第1のスイッチ回路
、3は第1のスイッチ回路と同一構成の第2のスイッチ
回路、R1−R4,R(、’町は抵抗、4は出力端子、
6,6゜s/、 e/はそれぞれ前記第1.第2のスイ
ッチ回路2,3に対応する制御端子、7は演算増幅器で
ある。
FIGS. 3 to 6 show embodiments applied to a circuit that switches a sine wave voltage and outputs it as a staircase wave.
FIG. 3 is a circuit diagram thereof, FIG. 4 is a waveform diagram of input/output voltages, and FIG. 6 is an explanatory diagram showing the timing relationship of switching of the switch circuit. In FIG. 3, 2 is a first switch circuit, 3 is a second switch circuit having the same configuration as the first switch circuit, R1-R4,R(,' is a resistor, 4 is an output terminal,
6, 6°s/ and e/ are respectively the first. A control terminal 7 corresponding to the second switch circuits 2 and 3 is an operational amplifier.

第4図において、イル二はそれぞれ制御端子6゜6 、
5’、 6’の制御電圧波形、ホは入力端子1への入力
アナログ信号波形、へは出力端子4からの出力波形であ
る。なお上記実施例では、R3)Rζ+Rf>馬+R2
・・・・・・・・・・・・・・・・・・(1)Rlg<
<R1,R2・・・・・・・・・・・・・・・ニ二・・
・・・・・・・・・情に選ばれているもっとする。但し
Rsはスイッチ回路2,3のオン時の抵抗値である。
In FIG. 4, the control terminals 6°6 and 2, respectively,
5' and 6' are the control voltage waveforms, E is the input analog signal waveform to the input terminal 1, and E is the output waveform from the output terminal 4. In the above embodiment, R3) Rζ+Rf>Horse+R2
・・・・・・・・・・・・・・・・・・(1) Rlg<
<R1, R2・・・・・・・・・・・・Nini...
・・・・・・・・・I will do more if I am chosen by love. However, Rs is the resistance value when the switch circuits 2 and 3 are turned on.

次の上記実施例の動作を説明する。入力端子1に加わっ
た入力信号は、a、b、cの3経路に分れ、経路aでは
抵抗R,と”2 y経路すでは抵抗R1′。
Next, the operation of the above embodiment will be explained. The input signal applied to the input terminal 1 is divided into three paths, a, b, and c, with a resistance R in the path a and a resistance R1' in the 2y path.

Hz  また経路Oでは抵抗R3を紅て後、再びd点に
合流して、演算増幅器7の(−)信号端子に共通入力さ
れる。前記経路aとbの中間には、抵抗R1とR2の中
間にに第1のスイッチ回路2が、また抵抗R,lとR2
′の中間には第2のスイッチ回路3がそれぞれアースと
の間に接続されていて、これらのスイッチ回路がONの
時にはいずれも低い値のON抵抗R11!が信号の経路
a及びbと並列に挿入されることになる。
Hz In the path O, after turning on the resistor R3, the signal joins again to the point d, and is commonly input to the (-) signal terminal of the operational amplifier 7. Between the paths a and b, there is a first switch circuit 2 between the resistors R1 and R2, and between the resistors R, l and R2.
'A second switch circuit 3 is connected between each ground and the ground, and when these switch circuits are ON, the ON resistance R11! is a low value. will be inserted in parallel with signal paths a and b.

上記構成で例えば、第1のスイッチ回路2がON第2の
スイッチ回路3がOyyとなると、第1のスイッチ回路
の信号は、 (Rz/R1)(Rt+昌/R* (Rt +Rz /
Rs )゛・・−・−・−・・(樽 に減衰され(/は並列接続を表わす。)、前記(模式に
おいて R2/Rs=Rgとなるから、近似的にRa・
(Rt /R2)<< 1  となり、大巾に減衰を受
けることになる。従って、この場合d点に合流される信
号は、ハホ経路す、cによって定まり、抵抗R1′+R
11!−,R3の並列合成値とR4の比により出力電圧
が定まる。
In the above configuration, for example, when the first switch circuit 2 is ON and the second switch circuit 3 is Oyy, the signal of the first switch circuit is (Rz/R1)(Rt+Chang/R* (Rt +Rz/
Rs)゛・・−・−・−・・(Attenuated by the barrel (/ represents parallel connection), as mentioned above (in the model, R2/Rs=Rg, so approximately Ra・
(Rt /R2)<< 1, and the signal will be greatly attenuated. Therefore, in this case, the signal added to point d is determined by the path c, and the resistance R1'+R
11! -, the output voltage is determined by the ratio of the parallel composite value of R3 and R4.

次に第4図のように一2組のスイッチ回路2.3がそれ
ぞれ異なる制御信号によシ駆動された場合には、第6図
の関係で、スイッチ回路が4通シに切換り、この時経路
aとbでその抵抗の和の間に(1)式に示した関係があ
ると、第4図へに示すような階段波状の出力パルス波形
が得られる。
Next, when the 12 sets of switch circuits 2.3 are driven by different control signals as shown in FIG. If there is a relationship shown in equation (1) between the sum of the resistances in the time paths a and b, a staircase-like output pulse waveform as shown in FIG. 4 is obtained.

前記のようにアナログスイッチ−のひずみ特性はダイオ
ードがONの時に悪化するが、上記構成で ′はスイッ
チ回路が信号路と並列に挿入されていて例えばスイッチ
回路の固有Oひすみ率が−40(IB1前記((2)式
による信号減衰率が一6011Bとすると、OFF状態
のダイオードのひすみ率は極めて低い゛ので問題となら
ず、綜合で一4◇+(−eo) =−1ooaのひずみ
率が得られ、結局60(1Bのひずみ率改善が達成でき
たことになる。なお上記構成で、信号減衰度を大きく取
ると、出力が減少するが、これは演算増幅器7の増幅度
を十分大きく取って補償してやればよい。なお上記説明
では、スイッチング素子としてダイオードを使用した場
合を説明したが、トランジスタ、awos等の他のアナ
ロ夛スイッチング素子を使用した場合にも同様適用され
ることはいうまでもない。また前記並列接続した分岐の
数も上記3([に限らず2個以上の種々な場合が考えら
れる。
As mentioned above, the distortion characteristics of an analog switch deteriorate when the diode is ON, but in the above configuration, the switch circuit is inserted in parallel with the signal path, and for example, the inherent O distortion factor of the switch circuit is -40 ( IB1 (Assuming that the signal attenuation rate according to equation (2) is 16011B, the distortion factor of the diode in the OFF state is extremely low, so there is no problem, and the total distortion is -4◇+(-eo) =-1ooa. In the end, a distortion rate improvement of 60 (1B) was achieved.In the above configuration, if the degree of signal attenuation is increased, the output decreases, but this is because the amplification degree of the operational amplifier 7 is not sufficiently increased. All you have to do is take a larger value and compensate.In the above explanation, we have explained the case where a diode is used as the switching element, but the same applies to the case where other analog switching elements such as transistors and AWOS are used. Needless to say, the number of parallel-connected branches is not limited to the above-mentioned 3 ([), but various cases of 2 or more can be considered.

以上説明したように、本発明によれば、アナログ入力信
号を複数個の並列経路に分岐し、各経路の中間点に、そ
れぞれ信号路とアース間に接続したアナログスイッチ回
路を挿入し、これらをスイッチング制御して、その出力
を抵抗帰還をした演算増幅器に入力することによって、
極めて低ひずみ率のアナログスイッチ回路が実現出来そ
の工業的価値は大である。
As explained above, according to the present invention, an analog input signal is branched into a plurality of parallel paths, and an analog switch circuit connected between the signal path and the ground is inserted at the intermediate point of each path. By controlling switching and inputting the output to an operational amplifier with resistive feedback,
An analog switch circuit with an extremely low distortion rate can be realized, and its industrial value is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のアナログスイッチ回路の結線図、第2図
は同要部の波形図、第3図は本発明の−実雄側によるア
ナログスイッチ回路の結線図、第4図はその要部の信号
波形図、第6図はその動作を説明のための図である。 1・・・・・・入力端子、2.3・・・・・・スイッチ
回路、4・・・・・・出力端子、5,6.5’、6’・
・・・・・制御端子、7・・・・・・演算増幅器、R1
−R4,Rf、 il/・・川・抵抗。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第 
4wA 81m1 0 畠 2 図 凧 3 図 3R3゜ 第 51!I
Fig. 1 is a wiring diagram of a conventional analog switch circuit, Fig. 2 is a waveform diagram of its main parts, Fig. 3 is a wiring diagram of an analog switch circuit according to the actual male side of the present invention, and Fig. 4 is a diagram of its main parts. The signal waveform diagram in FIG. 6 is a diagram for explaining the operation. 1...Input terminal, 2.3...Switch circuit, 4...Output terminal, 5, 6.5', 6'.
...Control terminal, 7...Operation amplifier, R1
-R4, Rf, il/...river/resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person
4wA 81m1 0 Hatake 2 Figure Kite 3 Figure 3R3゜No. 51! I

Claims (1)

【特許請求の範囲】[Claims] 信号の入力端子に一端が共通接続された複数個の並列抵
抗回路と、前記並列抵抗回路のうち少なくとも一個の抵
抗回路の中間点とアースの間に接続され、それぞれ制御
信号端子を有する少なくとも一個のスイッチ回路と、前
記並列抵抗回路の共通接続された他端と出力端子との間
に接続された演算増幅回路とからなるアナログスイッチ
回路。
a plurality of parallel resistance circuits each having one end commonly connected to a signal input terminal; and at least one parallel resistance circuit connected between an intermediate point of at least one of the parallel resistance circuits and ground, each having a control signal terminal. An analog switch circuit comprising a switch circuit and an operational amplifier circuit connected between the other commonly connected end of the parallel resistance circuit and an output terminal.
JP16161681A 1981-10-09 1981-10-09 Analog switch circuit Pending JPS5862932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16161681A JPS5862932A (en) 1981-10-09 1981-10-09 Analog switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16161681A JPS5862932A (en) 1981-10-09 1981-10-09 Analog switch circuit

Publications (1)

Publication Number Publication Date
JPS5862932A true JPS5862932A (en) 1983-04-14

Family

ID=15738551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16161681A Pending JPS5862932A (en) 1981-10-09 1981-10-09 Analog switch circuit

Country Status (1)

Country Link
JP (1) JPS5862932A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218041A (en) * 1983-05-25 1984-12-08 Mitsubishi Electric Corp High frequency switching circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380943A (en) * 1976-12-26 1978-07-17 Ricoh Co Ltd Controllable attenuator
JPS5582521A (en) * 1978-12-18 1980-06-21 Matsushita Electric Ind Co Ltd Attenuator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380943A (en) * 1976-12-26 1978-07-17 Ricoh Co Ltd Controllable attenuator
JPS5582521A (en) * 1978-12-18 1980-06-21 Matsushita Electric Ind Co Ltd Attenuator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218041A (en) * 1983-05-25 1984-12-08 Mitsubishi Electric Corp High frequency switching circuit

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