JPS6187421A - Digital circuit - Google Patents
Digital circuitInfo
- Publication number
- JPS6187421A JPS6187421A JP59207130A JP20713084A JPS6187421A JP S6187421 A JPS6187421 A JP S6187421A JP 59207130 A JP59207130 A JP 59207130A JP 20713084 A JP20713084 A JP 20713084A JP S6187421 A JPS6187421 A JP S6187421A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- transistor
- potential
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/603—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with coupled emitters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
- H03K17/04213—Modifications for accelerating switching by feedback from the output circuit to the control circuit in bipolar transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はデータ処理装置に於けるディジタル回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital circuit in a data processing device.
従来この種のディジタル回路を第２図を用いて説明する
。A conventional digital circuit of this type will be explained with reference to FIG.
電流＄１５は第１のトランジスタ９．１０と第２のトラ
ンジスタ１１から流れて来る電流の総和を一定の電流値
にする回路であシ、第１のトランジスタ９．１０に流れ
る電流は、基準電源端子４より高い電位を入力端子５も
しくは６に印加すると増加し、第２のトランジスタＩＩ
Ｋ流れる電流は減少し基準電圧端子４よシも低い電位を
入力端子５および６に印加すると第１のトランジスタ９
゜ｌＯに流れる電流は減少し相対的に第２のトランジス
タ１１に流れる電流は増加する。第１のトランジスタ９
．ｌＯに流れる電流が増加すると、第１の電源端子ｌか
ら第１の抵抗１２を通って流れる電流が増加するため、
第１のトランジスタ９゜ｌＯのコレクタ端子の電位が降
下する。従って第３のトランジスタ１６に流れる電流が
減少し、エミッタ端子の電位が降下する。この時相対的
に第２のトランジスタＩＩＫ流れる電流が減少し、第１
の電源端子ｌから第２の抵抗１３を通って流れる電流が
減少し、第２のトランジスタ１１のコレクタ端子の電位
は上昇する。このため第４のトランジスタ１８に流れる
電流は増加しエミッタ端子の電位を上昇させる。The current $15 is a circuit that makes the sum of the currents flowing from the first transistor 9.10 and the second transistor 11 a constant current value. When a potential higher than terminal 4 is applied to input terminal 5 or 6, it increases and the second transistor II
The current flowing through K decreases, and when a lower potential than the reference voltage terminal 4 is applied to the input terminals 5 and 6, the first transistor 9
The current flowing through °lO decreases, and the current flowing through the second transistor 11 relatively increases. first transistor 9
．． When the current flowing through lO increases, the current flowing from the first power supply terminal l through the first resistor 12 increases, so
The potential at the collector terminal of the first transistor 9°lO drops. Therefore, the current flowing through the third transistor 16 decreases, and the potential at the emitter terminal drops. At this time, the current flowing through the second transistor IIK decreases relatively, and the current flowing through the first transistor IIK decreases.
The current flowing from the power supply terminal l through the second resistor 13 decreases, and the potential at the collector terminal of the second transistor 11 increases. Therefore, the current flowing through the fourth transistor 18 increases, raising the potential of the emitter terminal.
第１のトランジスタ９．ＩＯＫ流れる電流が減少すると
第１の電源端子ｌから第１の抵抗１２を通って流れる電
流が減少し、第１のトランジスタ９．１０のコレクタ端
子の電位が上昇する。従って第３のトランジスタ１６に
流れる電流が増加しエミッタ端子の電位が上昇する。こ
の時相対的に第２のトランジスタ１１に流れる電流が増
加し、第１の電源端子ｌから第２の抵抗１３を通って流
れる電流が増加し、第２のトランジスタ１１のコレクタ
端子の電位は降下する。このため第４のトランジスタ１
８に流れる電流は減少し、エミッタ端子の電位を降下さ
せる。First transistor9. When the current flowing through IOK decreases, the current flowing from the first power supply terminal l through the first resistor 12 decreases, and the potential at the collector terminal of the first transistor 9.10 increases. Therefore, the current flowing through the third transistor 16 increases and the potential at the emitter terminal rises. At this time, the current flowing through the second transistor 11 relatively increases, the current flowing from the first power supply terminal l through the second resistor 13 increases, and the potential of the collector terminal of the second transistor 11 decreases. do. Therefore, the fourth transistor 1
The current flowing through 8 decreases, lowering the potential at the emitter terminal.
ここにおいて第４の抵抗１７および′Ｍ５の抵抗１９は
第３のトランジスタ１６および第４のトランジスタ１８
に流れる電流を電圧に変換するものである。Here, the fourth resistor 17 and the resistor 19 of 'M5 are connected to the third transistor 16 and the fourth transistor 18.
It converts the current flowing through the circuit into voltage.
しかしながらディジタル回路の集積化が大規模になるに
従って定電流源に流す電流値および第３および第４のト
ランジスタに流す電流値を少なくしないと電力制限によ
シ作成できなくなってきている。即ち、第３もしくはＭ
４のトランジスタが電流を流す時は、トランジスタと抵
抗の並列抵抗により駆動するが電流が減少する時は第４
もしくは第６の抵抗のみで駆動するととくなるため、負
荷の容量が大きい時に立下がり時間が増大し、遅延時間
も大きくなる傾向にあるという問題点があった。However, as the scale of integration of digital circuits increases, it has become impossible to create a circuit due to power limitations unless the current value flowing through the constant current source and the current value flowing through the third and fourth transistors are reduced. That is, the third or M
When the fourth transistor passes current, it is driven by the parallel resistance of the transistor and the resistor, but when the current decreases, the fourth transistor
Alternatively, since it is driven only by the sixth resistor, there is a problem that when the load capacity is large, the fall time increases and the delay time also tends to increase.
本発明は、第２のトランジスタ１１のコレクタ端子とベ
ース端子間に第６の抵抗を追加し、入力端子５．６に印
加される電位に応じ第２のトランジスタ１１のベース端
子の基準電位を変化させることにより負荷によゐ立上が
シおよび立下がり時間が増大して本遅延時間を小さくで
きるディジタル回路を提供するものである。そして具体
的には、上記従来の問題点の解決手段として所定数の入
力端子と、ベース端子が前記入力端子に接続されコレク
タ端子が相互に接続され：かつエミッタ端子が相互に接
続された単数もしくは複数の第１のトランジスタト、前
記第１のトランジスタのコレクタ端子に接続され他の一
方が第１の電源端子に接続され第１の抵抗と、前記第１
のトランジスタのエミッタ端子に接続され他の一方が第
２のＭ源端子に接続された定電流源と、エミッタ端子が
前記第１のトランジスタのエミッタ端子接続された第２
のトランジスタと、前記第２のトランジスタのコレクタ
端子（接続され他の一方を前記第１の電源端子に接続さ
れた第２の抵抗と、前記第２のトランジスタのベース端
子に接続され他の一方を基準電源端子に接続されたｔｓ
３の抵抗と、前記第２のトランジスタのコレクタ端子に
接続され他の一方を第２のトランジスタのベース端子に
接続された帰還回路からなるディジタル回路を提供する
ものである。The present invention adds a sixth resistor between the collector terminal and the base terminal of the second transistor 11, and changes the reference potential of the base terminal of the second transistor 11 according to the potential applied to the input terminal 5.6. The purpose of the present invention is to provide a digital circuit in which the rise and fall times due to the load are increased and the delay time can be reduced. Specifically, as a solution to the above-mentioned conventional problems, a predetermined number of input terminals, a base terminal connected to the input terminal, a collector terminal connected to each other, and an emitter terminal connected to each other are provided. a plurality of first transistors, one of which is connected to the collector terminal of the first transistor and the other of which is connected to a first power supply terminal; a first resistor;
a constant current source connected to the emitter terminal of the first transistor and the other connected to the second M source terminal; and a second constant current source whose emitter terminal is connected to the emitter terminal of the first transistor.
a second resistor connected to the collector terminal of the second transistor, the other one being connected to the first power supply terminal; ts connected to the reference power supply terminal
3 and a feedback circuit connected to the collector terminal of the second transistor and the other end connected to the base terminal of the second transistor.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
本発明の実施例を示す第１図において本発明のディジタ
ル回路は、入力端子５．６と、ベース端子が入力端子５
．６に接続され、コレクタ端子が相互に接続されかつエ
ミッタ端子が相互く接続された第１のトランジスタ９．
１０と、前記第１のトランジスタ９．ｌＯのコレクタ端
子に接続され他の一方が第１の電源端子ｌに接続された
第１の抵抗１２と、前記＠１のトランジスタ９．１０の
エミッタ端子に接続され他の一方が第２の電源端子２に
接続された定電流５１１５と、エミッタ端子が前記ｔａ
ｌのトランジスタ９．１０のエミッタ端子に接続された
第２のトランジスタ１１と、前記第２のトランジスタ１
１のコレクタ端子に接続され他の一方が前記第１の電源
端子ｌに接続された第２の抵抗１３と、前記第２のトラ
ンジスタ１１０ベース端子に接続され他の一方が基準電
源端子４に接続された第３の抵抗１４と、ベース端子が
前Ｅ第１のトランジスタ９．１０のコレクタ端子に接続
されコレクタ端子が前記第１の電源端子ＩＫ接続され、
かつエミッタ端子が第１の出力端子゛ｌに接続された第
３のトランジスタ１６と、前記ｔａ３のトランジスタ１
６のエミッタ端子に接続され他の一方が第３の電源端子
３に接続された第４の抵抗１７と、ベース端子が前記第
２のトランジスタ１１のコレクタ端子に接続されコレク
タ端子が前記第１の電ｌ１１１１ＩＩｌ子ＩＫ接続され
かつエミッタ端子が第２の出力端子８に接続された第４
のトランジスタ１８と、前記ｔａ４のトランジスタ１８
のエミッタ端子に接続され他の一方が前記第３の電源端
子３に接続された第６の抵抗１９と、前記第２のトラン
ジスタ１１のコレクタ端子Ｋｍ続されかつ他の一方が第
２のトランジスタ１１のベース端子に接続された帰還回
路２０からなるディジタル回路である。In FIG. 1 showing an embodiment of the present invention, the digital circuit of the present invention has an input terminal 5.6 and a base terminal connected to the input terminal 5.
．． 6, the first transistors 9.6 having their collector terminals connected to each other and their emitter terminals connected to each other;
10, and the first transistor 9. A first resistor 12 is connected to the collector terminal of lO and the other side is connected to the first power supply terminal l, and the other side is connected to the emitter terminal of the transistor 9 and 10 of @1 and the other side is connected to the second power supply terminal. A constant current 5115 connected to terminal 2 and an emitter terminal connected to the ta
a second transistor 11 connected to the emitter terminal of the transistor 9.10 of the second transistor 1;
a second resistor 13 connected to the collector terminal of the second transistor 110 and the other end connected to the first power supply terminal l; and a second resistor 13 connected to the base terminal of the second transistor 110 and the other end connected to the reference power supply terminal 4. A third resistor 14 whose base terminal is connected to the collector terminal of the first transistor 9.10 and whose collector terminal is connected to the first power supply terminal IK,
and a third transistor 16 whose emitter terminal is connected to the first output terminal ``1'', and the transistor 1 of the ta3.
a fourth resistor 17 whose base terminal is connected to the collector terminal of the second transistor 11 and whose collector terminal is connected to the first transistor 11; A fourth terminal connected to the terminal IK and whose emitter terminal is connected to the second output terminal 8
and the transistor 18 of ta4.
A sixth resistor 19 is connected to the emitter terminal of the second transistor 11 and the other end is connected to the third power supply terminal 3, and the collector terminal Km of the second transistor 11 is connected to the sixth resistor 19, and the other end is connected to the second transistor 11. This is a digital circuit consisting of a feedback circuit 20 connected to the base terminal of.
定電流源１５は第１のトランジスタ９．１０と第２のト
ランジスタに流れる電流の和が一定となる回路である。The constant current source 15 is a circuit in which the sum of currents flowing through the first transistor 9 and the second transistor is constant.
ここで第２のトランジスタ１１０ベース端子に印加され
ている基準電位より高い電位が入力端子に印加されると
第１のトランジスタ９、ＩＯＫ多くの電流が流れその電
流は電源端子ｌから＊１の抵抗１２を通して流れるため
第１のトランジスタのコレクタ電位は降下する。その時
第２のトランジスタＩＩＫ流れる電流は相対的に減少し
、第・ｌの電源端子ｌから第２の抵抗１３に流れる電流
が減少するため第２のトランジスタ１１のコレクタ端子
の電位は上昇する。Here, when a potential higher than the reference potential applied to the base terminal of the second transistor 110 is applied to the input terminal, a large current flows through the first transistor 9, IOK, and the current flows from the power supply terminal l to the resistance of *1. 12, the collector potential of the first transistor drops. At that time, the current flowing through the second transistor IIK decreases relatively, and the current flowing from the lth power supply terminal l to the second resistor 13 decreases, so that the potential at the collector terminal of the second transistor 11 increases.
また入力端子５．６に第２のトランジスタ１１０ベース
端子の基準電位より低い電位が印加されると第１のトラ
ンジスタ９．ＩＯＫ流れる電流は減少し第１のトランジ
スタ９．１０のコレクタ端子の電位を上昇させ、相対的
に第２のトランジスタＩＩＫ流れる電流を増加させ第２
のトランジスタ１１のコレクタ端子の電位を降下させる
。Further, when a potential lower than the reference potential of the base terminal of the second transistor 110 is applied to the input terminal 5.6, the first transistor 9. The current flowing through IOK decreases, increasing the potential at the collector terminal of the first transistor 9.10, and relatively increases the current flowing through the second transistor IIK.
The potential of the collector terminal of the transistor 11 is lowered.
本発明において、第２のトランジスタ１１のコレクタ端
子とベース端子の間に帰還回路２０がありそのため第２
のトランジスタ１１のコレクタ端子の電位が高い時は帰
還回路２０を通してベース端子に流れる電流が増加しベ
ース端子の電位を上昇させ、また第２のトランジスタ１
１のコレクタ端子の電位が降下した時は帰還回路２０を
通してベース端子に流れる電流が城少しベース端子の電
位を降下させる。In the present invention, there is a feedback circuit 20 between the collector terminal and the base terminal of the second transistor 11, so that the second
When the potential of the collector terminal of the second transistor 11 is high, the current flowing to the base terminal through the feedback circuit 20 increases, raising the potential of the base terminal.
When the potential of the collector terminal 1 drops, the current flowing to the base terminal through the feedback circuit 20 causes the potential of the base terminal to drop a little.
従って入力端子５．６に印加される電位が高い時は第２
のトランジスタ１１のベース端子の基準電位を高くなり
、入力端子５．６に印加される電位が高い電位から低い
電位になる時＠１のトランジスタ９．１０と第２のトラ
ンジスタ１１との電流の切り換えの時期を速くする。Therefore, when the potential applied to input terminal 5.6 is high, the second
When the reference potential of the base terminal of the transistor 11 is increased and the potential applied to the input terminal 5.6 changes from a high potential to a low potential, the current between the transistor 9.10 of @1 and the second transistor 11 is switched. speed up the timing.
また入力端子５．６に印加される電位が低い時は第２の
トランジスタ１１のベース端子の基準電位が低く表り入
力端子５．６に印加される電位が低い電位から高い電位
になる時第１のトランジスタ９．１０と第２のトランジ
スタとの電流の切シ換えの時期を速くする。Further, when the potential applied to the input terminal 5.6 is low, the reference potential of the base terminal of the second transistor 11 appears low, and when the potential applied to the input terminal 5.6 changes from a low potential to a high potential, the reference potential of the base terminal of the second transistor 11 appears low. To speed up the switching of current between the first transistor 9 and the second transistor.
この様にして電流の切シ換えが速くするととによシ第１
のトランジスタ９．１０のコレクタ端子および第２のト
ランジスタ１１のコレクタ端子の電位の変化が速くする
。第１のトランジスタ９゜ｌＯのコレクタ端子および第
２のトランジスタ１１のコレクタ端子の各電位は各々第
３のトランジスタ１６および第４のトランジスタ１８の
ベース端子に伝達され、第１のトランジスタ９．１０の
コレクタ端子の電位が高い時第３のトランジスタ１６に
流れる電流を多くしエミッタ端子の電位を高くして第１
の出力端子７に出力し低い時第３のトランジスタ１６に
流れる電流を少なくしエミッタ端子の電位を低くして第
１の出力端子７に出力しまた第２のトランジスタ１１の
コレクタ端子の電位が低い時に第４のトランジスタ１８
に流れる電流を少なくしエミッタ端子の電位を低くして
第２の出力端子８に出力し、電位が高い時に第４のトラ
ンジスタ１８に流れる電流を多くシ、工ζツタ端子の電
位を高くして第２の出力端子８に出力する。If the current can be switched quickly in this way, it will be especially useful.
The potentials of the collector terminals of the transistors 9 and 10 and the collector terminal of the second transistor 11 change quickly. The respective potentials of the collector terminal of the first transistor 9.10 and the collector terminal of the second transistor 11 are transmitted to the base terminals of the third transistor 16 and the fourth transistor 18, respectively, and the potentials of the collector terminal of the first transistor 9. When the potential of the collector terminal is high, the current flowing through the third transistor 16 is increased, the potential of the emitter terminal is high, and the first
When the current is low, the current flowing through the third transistor 16 is reduced, the emitter terminal potential is lowered, and the emitter terminal is outputted to the first output terminal 7, and the collector terminal potential of the second transistor 11 is low. Sometimes the fourth transistor 18
The current flowing through the fourth transistor 18 is increased to lower the potential of the emitter terminal and output to the second output terminal 8, and when the potential is high, the current flowing to the fourth transistor 18 is increased, and the potential of the emitter terminal is increased. It is output to the second output terminal 8.
第４の抵抗１７および第６の抵抗１９は各々第３のトラ
ンジスタ１６に流れる電流および第４のトランジスタ１
７に流れる電流を電圧に変換する回路であり、第３の電
源端子３は第２の電源端子２と同じであっても動作１変
わりがない。The fourth resistor 17 and the sixth resistor 19 are connected to a current flowing through the third transistor 16 and a current flowing through the fourth transistor 1, respectively.
This is a circuit that converts the current flowing through the power supply terminal 7 into a voltage, and even if the third power supply terminal 3 is the same as the second power supply terminal 2, the operation remains the same.
本発明に係るディジタル回路は、上記の如きものなので
第２のトランジスタのベース端子の電位を入力端子に印
加される電位に応じて変化させることＫより負荷によシ
立上がシ時間もしくは立下がり時間が増大しても遅延時
間を少なくすることが可能なるという効果を奏する。Since the digital circuit according to the present invention is as described above, the potential of the base terminal of the second transistor is changed according to the potential applied to the input terminal. Even if the time increases, the delay time can be reduced.
第１図は、本考案の一実施例を示す回路図、第２図は従
来のディジタル回路の例を示す回路図である。
ｌ・・・第１の電源端子 ２・・・第２の電源端子３
・・・第３の電源端子 ４・・・基準電源端子５．６
・・・入力端子 ７・・・第１の出力端子８・
・・第２の出力端子FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional digital circuit. l...First power terminal 2...Second power terminal 3
...Third power supply terminal 4...Reference power supply terminal 5.6
...Input terminal 7...First output terminal 8.
...Second output terminal
Claims (4)
前記入力端子に接続され、コレクタ端子が相互に接続さ
れ、かつエミッタ端子が相互に接続された単数もしくは
複数の第１のトランジスタと、前記第１のトランジスタ
のコレクタ端子に接続され他の一方が第一の電源端子に
接続された第１の抵抗と、前記第１のトランジスタのエ
ミッタ端子に接続され、他の一方が第２の電源端子に接
続された定電流源と、エミッタ端子が前記第１のトラン
ジスタのエミッタ端子に接続された第２のトランジスタ
と、前記第２のトランジスタのコレクタ端子に接続され
他の一方を前記第１の電源端子に接続された第２の抵抗
と、前記第２のトランジスタのベース端子に接続され他
の一方を基準電源端子に接続された第３の抵抗と、前記
第２のトランジスタのコレクタ端子に接続され他の一方
を前記第２のトランジスタのベース端子に接続された帰
還回路とからなるディジタル回路。(1) a predetermined number of input terminals and output terminals, and a single or plural first transistors whose base terminals are connected to the input terminals, whose collector terminals are mutually connected, and whose emitter terminals are mutually connected; a first resistor connected to the collector terminal of the first transistor and the other end connected to a first power supply terminal; and a first resistor connected to the emitter terminal of the first transistor and the other end connected to a second power supply terminal. a constant current source connected to a terminal, a second transistor whose emitter terminal is connected to the emitter terminal of the first transistor, and a second transistor whose emitter terminal is connected to the collector terminal of the second transistor and whose other one is connected to the first transistor. a second resistor connected to the power supply terminal; a third resistor connected to the base terminal of the second transistor and the other end connected to the reference power supply terminal; and a third resistor connected to the collector terminal of the second transistor. and a feedback circuit, the other end of which is connected to the base terminal of the second transistor.
端子に接続され、コレクタ端子が前記第１の電源端子に
接続されかつエミッタ端子が第１の出力端子接続される
第３のトランジスタと、前記第３のトランジスタのエミ
ッタ端子に接続され他の一方を前記第２の電源端子もし
くは第３の電源端子に接続された第４の抵抗とを備える
請求の範囲第１項記載のディジタル回路。(2) a third transistor whose base terminal is connected to the collector terminal of the first transistor, whose collector terminal is connected to the first power supply terminal, and whose emitter terminal is connected to the first output terminal; 2. The digital circuit according to claim 1, further comprising a fourth resistor connected to the emitter terminal of the transistor No. 3 and the other end connected to the second power supply terminal or the third power supply terminal.
端子に接続されコレクタ端子が前記第１の電源端子に接
続されかつエミッタ端子が第２の出力端子に接続された
第４のトランジスタと、前記第４のトランジスタのエミ
ッタ端子に接続され他の一方を前記第２の電源端子もし
くは前記第３の電源端子に接続された第６の抵抗とを備
える請求の範囲第１項記載のディジタル回路。(3) a fourth transistor whose base terminal is connected to the collector terminal of the second transistor, whose collector terminal is connected to the first power supply terminal, and whose emitter terminal is connected to the second output terminal; 2. The digital circuit according to claim 1, further comprising a sixth resistor connected to the emitter terminal of the transistor No. 4 and the other end connected to the second power supply terminal or the third power supply terminal.
タル回路。(4) The digital circuit according to claim 1, in which the constant current source is a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207130A JPS6187421A (en) | 1984-10-04 | 1984-10-04 | Digital circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207130A JPS6187421A (en) | 1984-10-04 | 1984-10-04 | Digital circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6187421A true JPS6187421A (en) | 1986-05-02 |
Family
ID=16534687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207130A Pending JPS6187421A (en) | 1984-10-04 | 1984-10-04 | Digital circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187421A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4669306A (en) * | 1984-06-13 | 1987-06-02 | Nippondenco Co., Ltd. | Heat-wire type air flow measurement apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5494269A (en) * | 1978-01-09 | 1979-07-25 | Hitachi Ltd | Logic circuit |
-
1984
- 1984-10-04 JP JP59207130A patent/JPS6187421A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5494269A (en) * | 1978-01-09 | 1979-07-25 | Hitachi Ltd | Logic circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4669306A (en) * | 1984-06-13 | 1987-06-02 | Nippondenco Co., Ltd. | Heat-wire type air flow measurement apparatus |
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