JPS586160A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS586160A JPS586160A JP56103974A JP10397481A JPS586160A JP S586160 A JPS586160 A JP S586160A JP 56103974 A JP56103974 A JP 56103974A JP 10397481 A JP10397481 A JP 10397481A JP S586160 A JPS586160 A JP S586160A
- Authority
- JP
- Japan
- Prior art keywords
- field oxide
- well
- oxide film
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、半導体基板内Ｋ
ｆｆｉｆｆ型のウェルを備えた半導体装置。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device.
A semiconductor device equipped with an ffiff type well.
特に相補１１Ｍｌ８半導体装置の勇造方法に関する。In particular, it relates to a method for manufacturing complementary 11Ml8 semiconductor devices.
相補型ＭＩ８半導体装置は、通常、半導体基板にその逆
導電型の不純物でウェルを形成し％仁のウェル内に、こ
のウェルの不純物と逆導電チャンネル屋のＭＩＳ半導体
装置と、基板内に基板不純物と逆導電チャンネル製のＭ
Ｉ８半導体装置を形成している。これらＭＩ８半導体装
置はｈ ｊｆＮチャンネルＭＩ８半導体装置ないしはＰ
チャンネルＭＩ８半導体装置を意味するが、これらの装
置を同一基板内に備えた相補型ＭＩＢ牛導体装置は低電
力消費の半導体装置として広く知られている。Complementary MI8 semiconductor devices usually form a well in a semiconductor substrate with an impurity of the opposite conductivity type. and M made of reverse conducting channel.
An I8 semiconductor device is formed. These MI8 semiconductor devices are h jfN channel MI8 semiconductor devices or P
This refers to a channel MI8 semiconductor device, and a complementary MIB conductor device including these devices on the same substrate is widely known as a semiconductor device with low power consumption.
これらの半導体装置において、基板と逆導電型チャンネ
ルのＭＩ８半導体装置は基板を共通にして用−１基板と
同一導電型チャンネルのＭＩ８半導体装置はウェルの中
に形成し、そのウェルを共通にして用いている。そのウ
ェルの形成方法においてまずはじめにウェルを形成して
から、トランジス一部を位置合わせする方法では、その
位置合わせのマージンを見込んでおかないと、拡散層と
基板とがシ■−トしてしまうというような不都合があり
え、また、トランジスタ部とフィールド部分を分離する
ための酸化膜に対して自己整合的にウェルを形成する方
法では、各ウェルがこの酸化膜によって分離されてしま
うため、各ウェルを共通の電位にするには、＃ｉに述べ
た方法より、各ウェル関を結線するためのコンタクト穴
及びその配線がはるかに多くなり、集積度を著しく悪化
させてｉた。In these semiconductor devices, MI8 semiconductor devices with a channel of conductivity type opposite to the substrate are formed in a common substrate, and MI8 semiconductor devices with a channel of the same conductivity type as the substrate are formed in a well, and the well is used in common. ing. In the method of forming the well, first forming the well and then aligning a part of the transistor, the diffusion layer and the substrate will be sheeted unless a margin for the alignment is taken into account. In addition, in the method of forming wells in a self-aligned manner with respect to the oxide film used to separate the transistor part and the field part, each well is separated by this oxide film. In order to have a common potential, the number of contact holes and interconnections for connecting each well is far greater than in the method described in #i, which significantly deteriorates the degree of integration.
本発明は、このような不都合がなく、フィールド酸化膜
に対して自己整合的にウェルを形成し、集積度の高い相
補型ＭＩ８半導体装置を製造できる方法を提供するもの
である。The present invention provides a method for manufacturing a highly integrated complementary MI8 semiconductor device by forming a well in a self-aligned manner with respect to a field oxide film without such inconvenience.
従来のフィールド酸化膜をマスクにして自己整合的にウ
ェルを形成する相補型ＭＩ８半導体装置の製造方法は第
１＃Ａ（ａ）〜（・）に示すようなものであった。まず
第１図（−に示すように、基板１（例えばｎ１ｌｓｉ基
板）上に酸化によりシリコン酸化膜２を形成し、しかる
後、耐酸化性物質３（たとえばシリコン窒化Ｍ）を前記
シリコン酸化＠２の上に形成し、素子領域となる部分以
外のシリコン窒化ｍ’を選択的に工、チンダする６次に
鶴１図伽）に示すように、酸化により、フィールド酸化
１１４を形成し、しかる後、シリコン窒化膜を除去する
。A conventional method for manufacturing a complementary MI8 semiconductor device in which a well is formed in a self-aligned manner using a field oxide film as a mask is as shown in #1 #A(a) to (.). First, as shown in FIG. Then, as shown in Figure 1), a field oxide 114 is formed by oxidation, and then the silicon nitride m' other than the part that will become the element region is selectively etched and tinned. , removing the silicon nitride film.
次に第１図（ｃ）に示すように、基板ｌと逆導電製の不
純物を持つウェル（本例でＦｉｐつ、ル＞１形成する部
分以外を例えばフォトレジスト５及びフィールド酸化膜
でマスクし、例えばボロンのイオン注入によりＰウェル
６ｔ−フィールド酸化ｊ［Ｋ対して自己整合的に形成す
る。久に第１図（ｄ）に示すように、通常の相補型半導
体装置の製造方法に従い。Next, as shown in FIG. 1(c), the area other than the part where a well (Fip>1 in this example) having impurities of opposite conductivity to the substrate 1 will be formed is masked with, for example, a photoresist 5 and a field oxide film. , for example, by implanting boron ions in a self-aligned manner with respect to the P-well 6t-field oxide j[K.As shown in FIG. 1(d), a conventional complementary semiconductor device manufacturing method is followed.
ポリシリコン７をゲート電極として、Ｐチャンネル型の
拡散層８．Ｎチャンネルｍｏ拡散層９をそれぞれボロン
不純物とリンネ細物をイオン注入することによシ形成す
る。次に第１図（・）に示すように、層間絶縁膜１０を
気相成長Ｓ１へによ）形成し、コンタク、ト穴をめけ、
金属配線・ｌｉｔ施すことにより相補型ＭＩＳ半導体装
置ができる。Using polysilicon 7 as a gate electrode, a P-channel type diffusion layer 8. The N-channel MO diffusion layer 9 is formed by ion-implanting boron impurities and Linnean impurities, respectively. Next, as shown in FIG.
A complementary MIS semiconductor device can be created by applying metal wiring and lit.
以上親羽した従来の製造方法による相補ｆｉＭＩ８半導
体装置において／ｒｉ、フィールド酸化膜をマスクにし
てウェルが形成されており、トランジスタの拡散層はウ
ェルの深さより浅く、ウェルの内に、フィールド酸化膜
で自己整合的に形成されているため、ウェルと拡散層の
目合せマージンを見込む必要がないので高集積化に過し
ているが１例えばウェルを同電位にする場合、各ウェル
にＰ形振散層とＮ形振散層を隣９合わせにして、これら
の拡散層をまたｉてコンタクト穴を設けて金属配！Ｉ勢
で結線しなければならず、他の金属配線の自由度を阻害
してｉた。In the complementary fiMI8 semiconductor device manufactured by the conventional manufacturing method described above, a well is formed using a field oxide film as a mask, the diffusion layer of the transistor is shallower than the depth of the well, and the field oxide film is formed within the well. Since the wells and diffusion layers are formed in a self-aligned manner, there is no need to allow for alignment margins between the wells and the diffusion layer, allowing for high integration. Place the diffusion layer and the N-type diffusion layer next to each other, make a contact hole across these diffusion layers, and then connect the metal! The wires had to be connected in one way, which hindered the freedom of other metal wiring.
そζで１本発明の製造方法は、フィールド酸化膜を形成
する前にフィールド酸化膜形成領域に選択的に不純物層
を形成し、しかる後、フィールド酸化膜を形成し、その
フィールド酸化膜に対しウェルを自己整合的に形成する
ことにより、ウェルを基板内で結線することを可能にし
、集積度の高い相補＠ＮＩＢ半導体装置を得るものであ
る。Therefore, in the manufacturing method of the present invention, before forming a field oxide film, an impurity layer is selectively formed in the field oxide film formation region, and then a field oxide film is formed, and an impurity layer is formed on the field oxide film. By forming the wells in a self-aligned manner, it is possible to connect the wells within the substrate, thereby obtaining a highly integrated complementary@NIB semiconductor device.
本発明の製造方法の実施例を第２図（４）〜（ｅ）で示
す。Examples of the manufacturing method of the present invention are shown in FIGS. 2(4) to 2(e).
まず第２図（ａ）に示すように、Ｎｌｌシリプン基板ｌ
上にシリコン酸化Ｆｓ２を熱酸化によ）形成し、しかる
後、シリコン窒化膜３を積層し、素子領域となる部分以
外１遇択的にエツチングし、さらに７オトレジスト５を
後にフィールド酸化される部分に選択的にマスクとして
残し、しかるｉｌＫ例えはボロンをイオン注入するとと
によＪ）、 ＰＩＮの不純物層１２を形成する。First, as shown in Figure 2(a), a Nll silicone substrate l
Silicon oxide Fs2 is formed thereon (by thermal oxidation), and then a silicon nitride film 3 is laminated and selectively etched except for the part that will become the element region. The impurity layer 12 of the PIN is then selectively left as a mask and then ion implanted with boron, for example, to form the impurity layer 12 of the PIN.
次に第２図伽）に示すように、フォトレジスト５及びシ
リコン窒化膜３を除去した後、熱酸化によりフィールド
酸化膜４を形成する。Next, as shown in FIG. 2, after removing the photoresist 5 and silicon nitride film 3, a field oxide film 4 is formed by thermal oxidation.
次に第２図（ｅ）に示すようにＰウェルを形成しない部
分にフォトレジスト５′を選択的ｔｔｃｆ！Ｉシｓその
フォトレジスト５′及びフィールド酸化１［４をマスク
にして、ボロンをイオン注入し、熱麩理する仁とにより
てＰウェル６を形成する。この際。Next, as shown in FIG. 2(e), a photoresist 5' is selectively applied to the area where the P-well will not be formed. Using the photoresist 5' and field oxide 1[4 as a mask, boron ions are implanted and thermally treated to form a P well 6. On this occasion.
＃Ｉ２図（耐工程で形成されて―るＰａｌ不純物層１２
とＰウェル６が一方向の拡散によりて１７ＮＩｉＡされ
る。#I2 diagram (Pal impurity layer 12 formed in the resistance process)
and P-well 6 are unidirectionally diffused to 17 NIiA.
そのため、 ４！ｒＰウエルを同電位にするために必要
でＴｏりた第１図（・）に示したコンタクト穴や金属配
線の形成工程がいらなくなるという大きな効果が生まれ
る０次に第２図（ｄ）に示すように、ポリシリコン７を
ゲート電極としてＰチャンネル型の拡散層８．Ｎチャン
ネル型の拡散層９をそれぞれボロン不純物とリンネ細物
でイオン注入することにより形成する。この際、それぞ
れの拡散層はフィールド酸化膜に対して自己整合的に形
成されるため、Ｍ、ｔばＮチャンネル・トランジスタの
ソース・ドレイン拡散領域は深いＰウェルの内にあシ、
基板とショー卜するおそれがない。Therefore, 4! The process shown in Figure 2 (d) has the great effect of eliminating the need for the contact hole and metal wiring formation steps shown in Figure 1 (-), which were necessary to make the rP wells at the same potential. With polysilicon 7 as a gate electrode, a P-channel type diffusion layer 8. N-channel type diffusion layers 9 are formed by ion implantation with boron impurities and linenite impurities, respectively. At this time, each diffusion layer is formed in a self-aligned manner with respect to the field oxide film, so that the source/drain diffusion regions of the M and T type N-channel transistors are located within the deep P well.
There is no risk of contact with the board.
次に第２図（ｅ）に示すように１層間絶縁膜４０′を気
相成長ＳｔＯ，で形成し、コンタクト穴をあけ、金属配
線１１に−施すことによシ、目的とする相補型ＭＩ８半
導体装置を得る。Next, as shown in FIG. 2(e), an interlayer insulating film 40' is formed using vapor-phase grown StO, a contact hole is made, and the metal wiring 11 is coated with the desired complementary type MI8. Obtain a semiconductor device.
以上説明したように、本発明のフィールド酸化膜を形成
する前にフィールド酸化膜形成領域に選択的に不純物層
全形成し、しかる後、フィールド酸化膜を形成し、その
フィールド酸化膜に対しウェルを自己整合的に形成する
という製造方法により、ウェルとソース・ドレイン拡散
層の目合せマージンを見込む必要がなく、かつフィール
ド酸化膜の下の不純物層によってウェル間の結線を基板
内で可能にしたことで第１図（ｅ）で示した工程で必要
だった各ウェルを同電位にするためのコンタクト穴や金
属配線がいらなくな）、高集積化が可能となった。As explained above, before forming the field oxide film of the present invention, the entire impurity layer is selectively formed in the field oxide film formation region, and then the field oxide film is formed, and a well is formed for the field oxide film. Due to the manufacturing method of self-aligned formation, there is no need to allow for alignment margins between the well and source/drain diffusion layer, and connections between wells can be made within the substrate using an impurity layer under the field oxide film. This eliminates the need for contact holes and metal wiring to bring each well to the same potential, which were required in the step shown in FIG. 1(e)), making high integration possible.
また、この製造方法に依ってフィールド酸化膜を形成す
る前にフィールド酸化膜形成領域に形成する不純物層の
濃度ヶ高めることによル、この不純物層の抵抗を低める
事も可能であシ、Ｐつ、ルの濃度を低下させてＮ型拡散
層の拡散容量を小さくすることも可能となシ、高速で高
集積な相補型ＭＩＳ半導体装置を得る事になる。Furthermore, according to this manufacturing method, by increasing the concentration of the impurity layer formed in the field oxide film formation region before forming the field oxide film, it is also possible to lower the resistance of this impurity layer. Furthermore, it is possible to reduce the diffusion capacitance of the N-type diffusion layer by lowering the concentration of metal, thereby obtaining a high-speed, highly integrated complementary MIS semiconductor device.
なお、通常ウェルのタイプはＮｌｌ基板に対してＦｉ、
ｐウェル、Ｐ型基板に対してはＮウェルになるが、基板
の導電型については本質的でなく、基板を選択しさえす
ればＮ型基板もＰ型基板に４適用できる。Note that the normal well type is Fi,
Although it becomes an N-well for a P-well or P-type substrate, the conductivity type of the substrate is not essential, and an N-type substrate can be applied to a P-type substrate as long as the substrate is selected.
第１図（ａ）〜（ｅ）は従来の製造工程を説明するため
の工程順の断面図で１１第２図（ａ）〜（・）は本発明
の一実施例を説明するための工程順の断面図である。
ｌ・・・Ｎ型Ｓ１基板、２−・シリコン醸化Ｉｔ ｓ・
・・シリコン値化１ｍ’−４・・・フィールド績化ＩＬ
５”・・フォトレジスト、６・−Ｐウェル、７−・・ポ
リシリコン。
８・・・・・・拡散層（Ｐ”）、９・・・拡散層（Ｎ＋
）％４−フィールド酸化ａ、ｌ Ｏ・ＣＶＤ−８ｉｏ１
．１１−・・金属、１２・・・不純物層。
第１図Figures 1 (a) to (e) are cross-sectional views in the order of steps for explaining conventional manufacturing processes, and Figures 2 (a) to (•) are cross-sectional views for explaining an embodiment of the present invention. FIG. l...N-type S1 substrate, 2--Silicon fermentation It s...
...Silicon value 1m'-4...Field value IL
5"...Photoresist, 6...-P well, 7-...Polysilicon. 8...Diffusion layer (P"), 9...Diffusion layer (N+
)%4-field oxidation a,l O・CVD-8io1
．． 11-...Metal, 12... Impurity layer. Figure 1
Claims (1)
以外の耐酸化性ｍを除去する工程と、この耐酸化性膜の
なｉ領域の一部に基板と逆導電型の第１の不純物を注入
する工程と、＊記耐酸化性展をマスクとして基板を酸化
し厚い酸化ｊＩ＆を形成する工程と、前記耐酸化性膜を
除去する工程と、この耐酸化性膜の存在した領域に前記
厚い酸化膜をマスクにして基板と逆導電型の第２の不Ｍ
ｅを注入し、この不純物を熱処理してウェルを形成し。 帥配第１の不純物に依りて形成され要領域とこの第２０
不純物に依りて形成されたウェルとを結ぶ工程を含むこ
とを％黴とする半導体装置の製造方法。[Claims] A step of growing an oxidation-resistant film on a semiconductor substrate of one conductivity type and removing oxidation-resistant m outside a predetermined OIA region, and a step of implanting a first impurity of a conductivity type; a step of oxidizing the substrate using the oxidation resistance film as a mask to form a thick oxide layer; a step of removing the oxidation-resistant film; Using the thick oxide film as a mask, a second non-metallic material having a conductivity type opposite to that of the substrate is applied to the region where the film was present.
This impurity is then heat-treated to form a well. The main region is formed by the first impurity and this 20th impurity.
A method for manufacturing a semiconductor device that includes a step of connecting wells formed with impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56103974A JPS586160A (en) | 1981-07-03 | 1981-07-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56103974A JPS586160A (en) | 1981-07-03 | 1981-07-03 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS586160A true JPS586160A (en) | 1983-01-13 |
| JPH0115150B2 JPH0115150B2 (en) | 1989-03-15 |
Family
ID=14368297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56103974A Granted JPS586160A (en) | 1981-07-03 | 1981-07-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS586160A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5331979A (en) * | 1976-09-06 | 1978-03-25 | Nec Corp | Insulated gate type field effect semiconductor device |
| JPS5529105A (en) * | 1978-08-23 | 1980-03-01 | Toshiba Corp | Manufacturing of complementary mos integrated circuit |
-
1981
- 1981-07-03 JP JP56103974A patent/JPS586160A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5331979A (en) * | 1976-09-06 | 1978-03-25 | Nec Corp | Insulated gate type field effect semiconductor device |
| JPS5529105A (en) * | 1978-08-23 | 1980-03-01 | Toshiba Corp | Manufacturing of complementary mos integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0115150B2 (en) | 1989-03-15 |
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