JPS5860490A - Controlling method for memory - Google Patents
Controlling method for memoryInfo
- Publication number
- JPS5860490A JPS5860490A JP56158917A JP15891781A JPS5860490A JP S5860490 A JPS5860490 A JP S5860490A JP 56158917 A JP56158917 A JP 56158917A JP 15891781 A JP15891781 A JP 15891781A JP S5860490 A JPS5860490 A JP S5860490A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- prom
- storage elements
- addresses
- life
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はメモリの制御方法に関し、特にメモリに記憶す
べきデータ量が小さい場合に用いて好適なものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control method, and is particularly suitable for use when the amount of data to be stored in the memory is small.
近年、書込みを行ったリードオンリーメモリの書込内容
を変更できるものとして、例えばｆＤＡＲＯＭ（１ｉｌ
ｒ、ｅｏＴａｒｏＡｔ、 ＡＬＴＥＲムＢＬε几Ｅ＾
Ｄ ＯＮＬＹＭａＭｏｕｙ）のようなプログラマブル・
リードオンリーメモリ（以下ＦＲＯＭと称す）が普及し
てきた。In recent years, for example, fDAROM (1il
r,eoTaroAt, ALTERMUBLε几E＾
Programmable devices such as D ONLY MaMouy
Read-only memory (hereinafter referred to as FROM) has become popular.
しかしながら、このＦＲＯＭは消去および書込み可能回
数（以下寿命と称す）が約１０６回に制限される性質が
ある。このため、ＦＲＯＭの内部に収容されている記憶
素子のどれか１つでも寿命に達した場合、他の記憶素子
がまだ使用可能であっても、ＦＲＯＭチップ全体を取換
えねばならないため、非常に経済性が悪かった。However, this FROM has a property that the number of times it can be erased and written (hereinafter referred to as life span) is limited to approximately 106 times. For this reason, if any one of the memory elements housed inside the FROM chip reaches the end of its lifespan, the entire FROM chip must be replaced even if other memory elements are still usable. The economy was bad.
したがって、本発明の目的はＰ Ｒ，ＯＭを長期間にわ
たって使用することができるメモリの制御方法を提供す
るものである。Therefore, an object of the present invention is to provide a memory control method that allows PR,OM to be used for a long period of time.
このような目的を達成するために本発明は、当初 ＦＲ
ＯＭの記憶素子のうち所定の部分の記憶素子だけを使用
し、この部分の記憶素子に寿命に運したものが発生した
時、当初使用していた部分の記憶素子以外の部分の記憶
素子を使用するものである。以下本発明を実施例を示す
図面を用いて詳細に説明する。In order to achieve such an object, the present invention was originally developed by FR.
Only the memory elements in a predetermined part of the memory elements in the OM are used, and when something occurs that causes the memory elements in this part to reach the end of their lifespan, the memory elements in a part other than the part originally used are used. It is something to do. Hereinafter, the present invention will be explained in detail using drawings showing embodiments.
図は本発明の一実施例を示す回路図である。図において
、１ば６４ワード×８ビツトの ＦＲＯＭであり、アド
レス選択端子 ム。−に、およびデータ端子り。−Ｄ８
を備えている。そして、アドレス選択端子のうち Ａ
。〜ム４Ｆｉ演算装置２のアドレスバス２ａに接続され
ており、データ端子り。The figure is a circuit diagram showing one embodiment of the present invention. In the figure, 1 is a 64-word x 8-bit FROM, and has an address selection terminal. – and data terminals. -D8
It is equipped with And among the address selection terminals, A
. ~ is connected to the address bus 2a of the 4Fi arithmetic unit 2, and serves as a data terminal.
〜 Ｄ８け演算装置２のデータバス２ｄ に接続されて
いる。またアドレス選択端子ムロは抵抗３を介して演算
装置２の電源Ｂに接続されると共にスイッチ４を介して
演算装置２のアースに接続されている。なおＦＲＯＭＩ
Ｖｉこの他の機能を有する端子もあるが、本発明の説
明には必要が無いので省略しである。~D8 are connected to the data bus 2d of the arithmetic unit 2. Further, the address selection terminal Muro is connected to the power source B of the arithmetic unit 2 via a resistor 3 and to the ground of the arithmetic unit 2 via a switch 4. Furthermore, FROMI
There are terminals with other functions than Vi, but they are omitted because they are not necessary for the explanation of the present invention.
当初、ＦＲＯＭＩを使用する時、スイッチ４をオンとし
て使用する。この結果、ＰＲｏＭｌのアドレス選択端子
人、け％□ｌレベルとなるので、Ｐ’ＲＯＭＩはアドレ
ス選択端子ム。〜＾、にょって、所定の部分即ち、零番
地から３１番地に対応する記憶素子が指定され、この部
分で書込み、および消去が行われる。Initially, when using FROMI, switch 4 is turned on. As a result, the address selection terminal of PRoMl becomes the level %□l, so P'ROMI becomes the address selection terminal. ~^ Accordingly, a predetermined portion, that is, a memory element corresponding to addresses 0 to 31, is designated, and writing and erasing are performed in this portion.
この零番地から３１番地に対応する記憶素子が寿命に達
したら、スイッチ４をオフとする。この結果、ＦＲＯＭ
Ｉのアドレス選択端子Ａ、はＪｌレベルとなるので、Ｆ
ＲＯＭＩは当初指定された番地を除いた番地、即ち３２
番地から６４．１１１−地に対応する記憶素子が指定さ
れ、この部分で１込み、および消去が行われる。When the memory elements corresponding to addresses 0 to 31 reach the end of their lifetime, the switch 4 is turned off. As a result, FROM
Since the address selection terminal A of I is at the Jl level, F
ROMI is an address other than the originally specified address, i.e. 32
The memory element corresponding to address 64.111- is specified, and 1-input and erasure are performed in this part.
このように、配憶すべき容ｉ１が少ない」烏合は、６４
ワード容法のＰＲＯＭＩの記憶答ｔ１を半分に分けて使
用すれば、従来は使用可能な部分が、ちるにもかかわら
ず、ＦＲＯＭＩの記憶素子のどれかが寿命に達した場合
、ＦＲＯＭＩのチップを交換しなければならなかったも
のが、同一チップを従来の２倍の期間にわカニって使用
することができイ、。In this way, there are fewer quantities i1 to store, which is 64
By dividing PROMI's memory answer t1 in word storage into two halves, the FROMI chip can be replaced when one of the FROMI memory elements reaches the end of its life, even though the usable part is reduced. Instead of having to replace the chips, the same chip can now be used for twice as long as before.
なお、ＰＲ，ＯＭｌの寿命を判断する方法としては、書
込回数をカラン）・しても良いし寿命に達したＥｉＡ、
ＩｔＯＭＩ Ｕ−正しい引込みが行えなくなる性質があ
るため書込内容をチェック１〜でも良い。丑だ、実施例
け３２ワードずつ使用したが、１６ワード毎に使用すれ
ば記憶容絹は更に倍加される。当然のことではあるが、
使用するＰ几ＯＭＩ／′１ｆｉ４ワードに限定されず、
記憶すべき拌栢に対応するものであれば良い。また、ス
イッチの切換を自動的に行うこともできる。In addition, as a method to judge the lifespan of PR and OMl, it is possible to check the number of writes, or to judge the lifespan of EiA when it has reached its lifespan.
ItOMI U-Since there is a property that it will not be possible to perform the correct pull-in, you may check the written contents from 1 onwards. In the example, I used 32 words at a time, but if I use every 16 words, the memory capacity will be further doubled. Of course,
Not limited to the P几OMI/'1fi4 word used,
It is sufficient if it corresponds to the stirrup to be memorized. Further, switching can also be performed automatically.
以上説明したように、本発明に係るメモリの制御方法は
当初ＦＲＯＭの記憶素子のうち所定の部分の記憶素子だ
けを使用し、この部分の記憶素子に寿命に達したものが
発生した時、当初使用していた部分の記憶素子以外の部
分の記憶素子を使用するものであるから従来の数倍の期
間にわたって同一の２８０Ｍを使用することができ、経
済性の良い使い方ができる優れた効果を有する。As explained above, the memory control method according to the present invention initially uses only a predetermined portion of the storage elements of the FROM, and when some of the storage elements in this portion reach the end of their lifespan, the memory control method according to the present invention initially Since the memory element in the part other than the memory element in the previously used part is used, the same 280M can be used for several times as long as conventional methods, and has an excellent effect of being used economically. .
図は本発明の一実施例を示す回路図である。
１・ ・・ＰＲＯＭ、 ２・・・・演算装置、２ａ・
・・・アドレスバス、２ｄ ・・・・データバス、３・
・・・抵抗、４・・・・スイッチ。
特許出願人 山武ノ＼ネウエル株式会社代 理 人 山
用政樹（ほか１名）The figure is a circuit diagram showing one embodiment of the present invention. 1...PROM, 2...Arithmetic unit, 2a...
... Address bus, 2d ... Data bus, 3.
...Resistance, 4...Switch. Patent Applicant: Yama Takeno / Newel Co., Ltd. Agent: Masaki Yama (and 1 other person)
Claims (1)
ーメモリにおいて、当初ｎ全記憶素子のうち所定部分の
記憶素子だけを使用し、その部分の記憶素子が寿命に達
した時は、当初使用した部分の記憶素子以外の記憶素子
を使用することを特徴とするメモリの制御方法。In a programmable read-only memory that has multiple memory elements, initially only a predetermined portion of the memory elements out of all n memory elements are used, and when that portion of the memory elements reaches the end of their lifespan, the memory elements of the originally used portion are used again. A method for controlling a memory, characterized in that a memory element other than the above is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158917A JPS5860490A (en) | 1981-10-05 | 1981-10-05 | Controlling method for memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158917A JPS5860490A (en) | 1981-10-05 | 1981-10-05 | Controlling method for memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5860490A true JPS5860490A (en) | 1983-04-09 |
Family
ID=15682161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56158917A Pending JPS5860490A (en) | 1981-10-05 | 1981-10-05 | Controlling method for memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5860490A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58215794A (en) * | 1982-06-08 | 1983-12-15 | Toshiba Corp | Non-volatile memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5637893B2 (en) * | 1977-11-17 | 1981-09-03 |
-
1981
- 1981-10-05 JP JP56158917A patent/JPS5860490A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5637893B2 (en) * | 1977-11-17 | 1981-09-03 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58215794A (en) * | 1982-06-08 | 1983-12-15 | Toshiba Corp | Non-volatile memory device |
| JPH0552000B2 (en) * | 1982-06-08 | 1993-08-04 | Tokyo Shibaura Electric Co |
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