JPS58215794A - Non-volatile memory device - Google Patents

Abstract

PURPOSE:To decrease the number of times of replacement of a memory and to improve the reliability, by splitting a non-volatile memory having a storage capacity of plural times of that of a system to each block and providing an exclusive location of the number of times of write for each unit block. CONSTITUTION:A storage area of an EEPROM having a capacity >=2 times the capacity requested to the system is splitted to blocks 1 and 2, and the direction of split is taken in the direction of word arrangement. Exclusive locations 3, 4 to store the number of times of program write to the corresponding memory are allocated to the blocks 1, 2 respectively, and the number of bits of each location corresponds to the limit value of the number of times of program write of the corresponding memory. When the number of times of program write of the block 1 reaches a specified value, the block is used switchingly. Whether or not the number of times of write reaches the specified value is discriminated with a count value stored to the locations 3, 4.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory devices, and more particularly to electrically programmable semiconductor non-volatile memory devices.

[Technical background of the invention and its problems]

Semiconductor nonvolatile memory uses MO8 type FETs to store binary information depending on the amount of accumulated charge, and has the characteristic that stored contents can be retained without applying power source heart pressure.

There are various types of such nonvolatile memory.

So far, so-called UV-EPROM (Ult
ra Vlolet-Erasable &+'Pro
gramable ROM) is often used in this [JV-EPROM], memory contents are erased by irradiation with ultraviolet rays, but this has the disadvantage of having to be removed from the circuit for erasing. be.

EEFROM (ELE) has recently been in the spotlight.
Critically Erasable & Prog
ramableROM). This KEPROM has the advantage of being able to be freely erased and written to using a separately provided eraser and eraser while it is in the mounted state, so it is suitable for systems where the memory contents are frequently changed.
For example, it is ideal for cash registers.

On the other hand, EEFROM is also used as a non-volatile RAM configured in combination with a normal static RAM.

This non-volatile RAM has the same capacity as static RAM.
It is composed of an EPROM and operates as a normal RAM while the power is turned on, and the contents stored in the static RA and M are transferred to the -fiEFPR before the power is turned off.
The data can be transferred to the OM and held as is, and after the power is turned on again, it can be returned from the EEPROM side to the static RAM to ensure non-volatility.

The problem with such F2EFROM is that it is necessary to apply high pressure when writing, so it is difficult to change the stored contents.
In other words, the number of times the program can be performed is limited. Currently, the limit for the number of programs is generally 1000 to 1
It is said to be about 0,000 times.

This limit must be strictly observed when using the product. This is because there is no guarantee of the reliability of the stored contents if the limit is exceeded.Here, the operating principle of the EEPROM and the reason why the number of programs can be limited will be explained. Figure 1 is a cross-sectional view of one cell of a typical EEPROM.
(a) shows the state when writing a program, and (b) shows the state when erasing. In FIG. 1, on a P-type St substrate IO, there are a first polarization 11 of the first layer polysilicon, a second polarization 11 of the first layer polysilicon,
A floating gate 12 made of layer polysilicon and a second electrode (for writing and erasing) made of third layer polysilicon are provided together with StO and an insulating layer 14. The floating gate 12 is arranged in a floating state between the first kicking pole 11 and the second kicking pole 13.

When programming (see FIG. 1(a)), the first electrode 11 is fixed at 0 (V:) or ground potential, and the second electrode 41
A positive voltage of 10 V is applied to t3. At this time, the 'I' position of the floating gate 17 is also the 2'1E pole 13.
Due to the electrostatic coupling with the positive voltage, the voltage rises to about 10 V. Then, the floating gate 12 and the first electrode 11
A high electric field is generated between the first electrode 11 and the floating gate 12, and electrons move from the first electrode 11 toward the floating gate 12 due to the tunnel effect, and the electrons are captured by the floating gate 12. When the electrons are sufficiently captured, the potential of the second electrode 13 is 1.
o (V) and completes the programming operation. In this state, the potential of the floating gate 12 is a negative potential because electrons are being captured.

Next, the case of erasing (see FIG. 1(b)) will be described. First, it is assumed that this cell has already been programmed and the floating gate 12 has captured electrons. The first polarization 11 is fixed at 0 [V], the floating gate 12 is set to o (V), and a voltage of +V is applied to the second electrode 13. Then, a high electric field is generated between the floating gate 12 and the second sleeping electrode 13, and the electrons captured by the floating gate 12 are expelled through the SI insulating layer 14 to the second electrode 13 due to the tunnel effect. It will be done. The erase operation ends when there are no captured electrons [7.
Return the electrode 13 to 0 [V].

As can be seen from the above, the state in which the floating gate 12 captures electrons and has a negative potential is the programmed state, and the opposite is the erased state. These two states correspond to signal logic types 1", '0" outside the memory. However, it is not univocally determined whether the programmed state is the logic type 1'' or the erased state is the logical type 10''. This is because it is determined by the relationship with peripheral devices.

In the EEPROM described above, the reason why the number of programs is limited is that a high voltage is applied to the second electrode 13 during programming, and electrons are moved from the first electrode 11 to the floating gate 12 by a tunnel effect. In other words, the electrons pass through the insulating layer between the first electrode 11 and the floating gate 12, causing stress and deteriorating the insulating layer. Note that even if an erase operation is performed on a cell that is in an erased state, or a pull-in operation is performed on a cell that is already in a written state, no significant stress is applied to the cell, so the rate of occurrence of deterioration is extremely low.

As mentioned above, if this flexible EEPROM is used in a system where programs are frequently changed, there is a risk that the stored contents may be lost. In the past, measures were taken to replace the EEFROM at an appropriate time based on the usage period of the system.
However, such usage leaves concerns about reliability and is not acceptable - replacing parts after the system has been shipped to the user is not desirable and may be difficult in some cases. It is also possible.

Moreover, the labor and cost required for replacement are expensive.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory device that reduces the number of times nonvolatile memory is replaced as much as possible and improves reliability.

[Overview of the invention]

In order to achieve the above object, a memory device according to the present invention prepares a non-volatile memory having a storage capacity multiple times the storage capacity required for the system in which the memory is used, and converts this memory into the required storage capacity. The storage area is divided into blocks for each unit, and when the - unit block reaches a predetermined number of program writes specified in the memory, it is sequentially switched to other unit blocks, and the number of program writes is reached. The system is characterized in that each unit block is provided with a dedicated location for storing the number of times a program has been written to the unit block.

〔Effect of the invention〕

According to the present invention having such a configuration, there is no need to replace the memory chip every time the number of program writes reaches a limited number of times, and since the limited number of times can be known from each dedicated location, it is possible to erase the stored contents. Reliability can be ensured without any problems.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail based on illustrated embodiments.

First, as a premise, recent semiconductor memory is EgPROM.
Not only that, but the capacity per chip has been increasing rapidly, and the price per chip is not proportional to the storage capacity per chip at the TT'T level, and the price per chip is not proportional to the storage capacity per chip. There is not much difference in unit price. Therefore, the available E
It is common for the capacity of one EPROM chip to be much larger. Therefore, it is possible to effectively utilize such extra capacity.

FIG. 2 shows an example in which an EEPROM having a crushing capacity of more than twice that of each paper required for the system is used. The storage area is divided into a first block 1 and a second block 2. The division direction is two divisions in the word direction. Therefore, the first block 1 and the second block 2, which are unit blocks, each have a capacity greater than the unit capacity required for the system.

Each of the first and second blocks 1.2 is assigned a dedicated location 3.4 for storing the number of times the program has been written to the memory. The number of bits in the dedicated location 3.4 is set to be the number corresponding to the limit value of the number of times the program can be written to the memory, and the corresponding memory cells are allocated to configure the dedicated location 3.4.The operation will now be described. First, to summarize, first block 1 is used, and when the number of program writes reaches a specified value, it is switched to use second block 2. Second
When the number of program writes in block 2 reaches a specified value, the EEPROM must be replaced.

Whether or not the number of times the program has been written has reached a specified value can be determined from the count value stored in the dedicated location 3.4. That is, an initial value (for example, "0") is set in the dedicated location 3 in advance. After that, every time a program is written to the first block 1, the dedicated location 2 is read and the stored value is incremented by 1. Then, the first shift is stored again in the dedicated location 3.

Next, the program is written to a storage area other than dedicated location 3. It should be noted that it is a design issue whether to perform the increment operation first or the casting operation first.

By the way, there is a first type in which EEPROMfC1d can be erased and written (that is, content can be changed) in units of one word, and a second type in which erasing can be performed only in whole words and writing can only be done in one chain position.

In the case of the first type of EEPROM, for example, the second block 2, which is an unused area while the first block 1 is in use, is not deteriorated at all because the contents can be changed at the first chain position. Assuming that the number of programs to be executed is 5000, the first block 1
5000 times in the second block 2, total 1
The program can be changed 0000 times.

In the case of the second type of EEPROM, when writing is performed at the 1st chain position, no deterioration occurs, but when erasing, all words are written (that is, both the first and second blocks 1.2 at the same time). Second block 2 which is unused area
Strictly speaking, there may be some deterioration since the erase operation is also performed. However, the deterioration during erasing J/'i is significantly less than the deterioration during writing. For example, the EEFR
Assuming that the number of programs specified in the OM is 5,000, the first block 1 is programmed 5,000 times, and the second block 2 is programmed 4,000 times considering the erase operation in the first block 1, for a total of 9,000 times. Program changes are possible.

FIG. 3 is a block diagram showing an example in which the present invention is applied to a nonvolatile RAM constructed by combining a normal RAM and an EEFROM. In FIG. 3, 5 indicates a RAM, which is divided into a first block 6 and a second block 7, each block 6 and 7 corresponding to the EEPROM+7) first block 1 and second block 2, respectively. It is assumed that the storage capacity is as follows. Each block 6.7 is also provided with a dedicated location 8.9. R.A.
M5 F1 In normal system operation, various information is written and read. For example, when the system's power is turned off, the contents are transferred from RAM5 to EEPR.
Close the door to the OM side and hold.

First, it is assumed that the first blocks 6 and 1 are used in relation to each other. Dedicated location 8 has an initial value (for example, %0
') is set. Now, when attempting to store the stored contents from the RAM 5 to the EEPROM side, the dedicated location 8 of the RAM 5 is read out immediately before the storage. The contents of the read exclusive location 8 are incremented by 1 and then written to the exclusive location 8 again. When dedicated location 8 is updated, the contents of RAM 5 are
It goes without saying that the contents of the dedicated location 8 are also written to the dedicated location 3 at this time.

Next, when using RAM5 again, EEPROM
The stored contents are written in their entirety to the RAM 5 side (referred to as recall).

When such a program change operation reaches a predetermined number of times, the area to be used next is switched from the relationship of the first block 6.1 to the relationship of 7.2, and the same operation as described above is performed. Also for non-volatile RAM, the EEPR used is
The cases where the OM is of the first type or the second type described above regarding erasure and transfer must be considered. Regarding the first type, since erasing and writing are performed at the first chain wheel level, no deterioration of unused areas occurs, so there is no need to consider this. In the case of the second type, there is some deterioration, but if the limit value of the number of programs is set to a small value, the problem is solved. The most problematic situation occurs when erasing and writing are performed using all words. In such a case, deterioration can be suppressed by writing the value 0" into the entire second block 6, which is an unused area of the RAM 5, and saving this 0# when storing. can.

[Modified example of the invention]

(1) In each of the embodiments described above, the contents of dedicated locations 3, 4, or 8.9 are sequentially changed to
Although the update is performed by incrementing, the maximum number of programs guaranteed for the EEPROM may be preset as an initial value, and the content may be decremented by 1 each time the program is changed. If this is done, the EEPROM will be able to tell whether the program can be changed for the remaining number of times.Also, when the specified number of programs has been reached, some kind of display (for example, display on the CRT display or lamp) will be displayed to let you know. Alternatively, changes to the program may be prohibited in order to proactively prevent the loss of information.

(2) Although the EE P ROM has been described as being divided into two parts, it may be further divided into three or four parts depending on the information to be stored and the storage capacity of the EEPROMI chip. In that case, the configuration of the above embodiment may be increased according to the number of divisions.
:The explanation was based on the assumption that P ROM is one chip, but
A plurality of independent EgPROMs may be used, and each chip may correspond to a block according to the present invention. In that case, since erasing and writing can be performed independently, it is possible to prevent unused areas from deteriorating.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of one cell of a typical FROM, in which (a) shows the program write state and (b) shows the erase state. FIG. 2 shows an embodiment of the memory device according to the present invention. FIG. 3 is a block diagram showing another embodiment. 1...first block, 2...second block, 3
... Dedicated location, 4... Dedicated location,
5... RAM, 6... First block, 7... Second block, 8... Dedicated location, 9... Dedicated location.

Claims (1)

[Claims] A programmable non-volatile memory device includes a plurality of unit block storage areas each having a storage capacity necessary for a system in which the memory device is used, and a - unit block stores a program program defined in the memory device. A non-volatile memory device characterized in that when the number of times a program has been written to the unit block is reached, the unit block is sequentially switched to another unit block, and each unit block is provided with a dedicated location for storing the number of times the program has been written to the unit block. .