JPH0140434B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a memory circuit.
This invention relates to a memory circuit that has versatility in setting addresses in ROM areas and RAM areas.

Memory ICs include ROM and RAM, and
RAM is made non-volatile rather than battery backup, and is also converted into ROM using a write-protect circuit.
There are also circuits. The memory circuit mounting board includes the above-mentioned ROM, RAM, and ROMized RAM.
However, in general, the address arrangement of each memory IC (for example, Fig. 1) differs depending on the individual model, so conventionally, a board with a pattern corresponding to the memory map of each model was individually created. In addition, if there is a common part of the memory map, the address can be changed by installing a depth switch or jumper line only in the part that needs to be changed, or by pattern cutting, but the range that can be changed is limited. The problem was that it was limited. In this way, conventional memory circuits have fixed address settings and write protection settings, resulting in dedicated memory circuits for each model.As a result, the number of types of memory circuits increases by the number of models. The drawback was that productivity could not be improved.

In view of the above-mentioned circumstances, the present invention provides a memory circuit that can cope with changes in the memory map with the same circuit configuration, thereby significantly improving productivity. a read-only memory mounting section and a random access memory mounting section; a non-volatile memory in which a plurality of memory maps having different memory map patterns of the read-only memory mounting section and the random access memory mounting section are written; A map mode selection switch selectively selects a desired one from each written memory map, and an output obtained by decoding an externally supplied address signal based on the memory map selected by the map mode selection switch. The present invention is characterized by comprising a memory control circuit that generates a control signal.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 1 is a bus driver for address buses (AB ₀ to AB ₁₅ ) that amplifies address signals A ₀ to A ₁₅ supplied from the CPU (central processing unit).
The amplified address signal A ₀ ~ A ₁₅ is 64K bytes
In addition to being supplied to the RAM circuit 2 and the 64K byte ROM circuit 3, the upper 8 bits of the address signal A ₈
~ _A15 is supplied to the map setting ROM4. RAM
Circuit 2 and ROM circuit 3 each consist of eight 8-bit x 8K IC memories, and each IC memory chip is selected using the upper 3 bits of the address signal.
This is done by decoding A ₁₃ to _{A 15} . Also, as you can see from the figure, RAM circuit 2 and
The same address is set in duplicate in the ROM circuit 3, so the printed patterns on the board are both set to address 0000 to FFFF (hexadecimal). Further, 5 is a bidirectional bus driver that is activated when writing or reading from the RAM circuit 2, and 6 is a unidirectional bus driver that is activated when reading from the ROM circuit 3.Here, the above-mentioned map setting ROM 4 will be explained. do. Map settings
ROM4 sets the address allocation for RAM circuit 2 and ROM circuit 3, and when viewed from the CPU side, ROM and RAM (or
This is to prevent duplication of ROMized RAM), and 16 types of address allocation patterns (hereinafter referred to as map modes) are set.
The selection of the map mode is performed by a selection signal supplied to the upper 4 bits of address input terminals _a8 to _a11 , and this selection signal is output from the map mode selection switch 7 consisting of a 4-bit dip switch. . And map settings
ROM4 receives address signals supplied to address input terminals _a0 to _a7 after map mode is selected.
Based on _A8 to _A15 , signals S, WE, and AE are output from output terminals _Q0 to _Q2 , respectively. This signal S is
RAM circuit 2 is a signal that specifies either one of ROM circuits 3, and when it is at “H” level, RAM
When the signal is at the "L" level, the circuit 2 is designated, and the ROM circuit 3 is designated. In addition, signals WE and AE are each write permission signal and address permission signal, both of which are “H”.
It is permitted when it is at level “L” and prohibited when it is at “L” level. 9 is an OR circuit, and when one or two of the two inputs of the WE and WE force switches are "H" (high), the output WEN becomes "H" and both inputs become "L". Output when ” (low)
WEN becomes “L”. Reference numeral 10 denotes a WE force switch, and the WE force switch is set to "H" only when writing data to a ROMized RAM portion to be described later, and is normally set to "L". 8 is a decoding circuit, which receives the above-mentioned signals S, WE, AE.
Based on the write pulse WP ₁ and the read pulse RP supplied from the CPU, a read signal R, a write signal W, and signals S ₁ to S ₃ for controlling the bus drivers 5 and 6 are output. Note that the functions of these signals will be described later.

Next, the operation of this embodiment will be explained.

First, by using the map mode selection switch 7,
Select the desired map mode. Assume that the map mode selected at this time is as shown in FIG. 3, for example.

The address signals A ₀ ~ A ₁₅ output by the CPU are (OOOO) _H ~ (8FFF) _H , (DOOO) _H ~ (DFFF)
If _H and (FOOO) _H (F7FF) _H. In this case, the signal S is at "L" level, the signal WE is at "L" level, and the signal AE is at "H" level.
As a result, when the decode circuit 8 is supplied with the read pulse RP, it outputs the signal _S1 to put the bus driver 6 into an operating state, and also outputs the read signal R to perform the ROM read operation. The data read from the ROM circuit 3 is then supplied to the CPU via the bus driver 6.
On the other hand, even if the write pulse WP is supplied to the decoding circuit 8, the write signal W is not output, nor are the signals S ₂ and S ₃ , so the bus driver 5 is in a non-operating state. Therefore, the address signal
When A ₀ to _{A 15} are within the above-mentioned range, neither reading nor writing is performed in the RAM circuit 2, and the circuit shown in FIG. 2 eventually functions as a ROM.

Address signal A ₀ ~ A ₁₅ is (9OOOO) _H ~
For (97FF) _H and (EOOO) _H ~ (EFFF) _H.
In this case, as shown in FIG.
WE and AE all go to "H" level, and as a result, when the read pulse RP is supplied, the decode circuit 8 outputs the read signal R to put the RAM circuit 2 in the read state, and also outputs the signal S ₂ . to start the bus driver 5. In this case, the bus driver 5 is activated in the direction of passing the data D ₀ to _{D 7} from right to left in the drawing. As a result, the RAM circuit 2 outputs address signals A ₀ to
The data at the address specified by _A15 is supplied to the CPU via the bus driver 5. At this time, since the signal _S1 is not output, the bus driver 6 is in a non-operating state, and as a result, the ROM
No data is supplied from circuit 3 to the CPU. On the other hand, when the write pulse WP is supplied to the decode circuit 8, the write signal W is output and the RAM circuit 2 enters the write state, and the signal _S3 is output and the bus driver 5 transfers the data D from left to right in the drawing. It is activated in the direction of passing ₀ to _D7 . As a result, address signals A ₀ to _{A 15}
Data D ₀ to D ₇ output from the CPU are written to the address specified by . Thus, in the above state, the circuit shown in FIG. 2 functions as a RAM.

Address signal A ₀ ~ A ₁₅ is (AOOO) _H ~
(CFFF) For _H. In this case, as shown in FIG. 3, the signals S and AE become "H" level and the signal WE becomes "L" level. As a result, when the decoding circuit 8 is supplied with the read pulse RP, it outputs the read signal R and also outputs the signal _S2 . Therefore, the read operation of the RAM circuit 2 is performed as described above. On the other hand, even if the write pulse WP is supplied to the decoding circuit 8, the write signal W
is not output, and signals S ₁ to _{S 3} are also not output. In other words, when address signals A ₀ to A ₁₅ are (AOOO) _H to (CFFF) _H , RAM circuit 2
It operates as a ROMized RAM, and the ROM circuit 3 becomes inactive.

Address signal A ₀ ~ A ₁₅ is (98OO) _H ~
For (9FFF) _H and (F8OO) _H ~ (FFFF) _H.
In this case, as shown in FIG. 3, the signals S and WE are at the "H" or "L" level (optional), and the signal AE is at the "L" level. As a result, the decoding circuit 8 receives the read signal R and the write signal W regardless of the presence or absence of the write pulse WP and read pulse RP.
, and also does not output signals S ₁ to _{S 3} .
That is, in this case, neither reading nor writing is performed in the circuit shown in FIG. Therefore, the address as seen from the CPU (AOOO) _H ~
Since (CFFF) _H and (F8OO) _H to (FFFF) _H are empty addresses, I/O etc. can also be set at these addresses.

As described above, in this embodiment, the address signal
Map the upper 8 bits of _A0 to _A15 , _A8 to _A15.
By decoding with ROM4, ROM and RAM (or
ROMized RAM) is distributed.
Furthermore, the map mode selection switch 7 allows the map mode to be changed.
Even if the model changes, the print pattern can be changed without any changes.

Note that it is extremely preferable to use an EP-ROM (erasable programmable ROM) as the map setting ROM because erasing and writing can be done easily. In addition, the output signals of the map setting ROM 4 include, for example, a ROM designation signal that designates which area the ROM belongs to when the ROM area is divided into multiple parts, or a parity detection permission signal that designates whether or not to set a parity bit. You can also set

In the example, 8K bytes of RAM and ROM are used.
Eight IC memory elements of 64K byte each are prepared, but memory elements that are not specified at all do not need to be mounted. Also, switching between RAM and ROM is possible.
In the case of 8K byte units (one memory element unit), the circuit portion of the ROM memory area in FIG. 2 may be removed. That is, the output S of the map setting ROM 4 is no longer needed (fixed at H), and the RAM and ROM elements coexist in the RAM memory area 2. Both the bus driver 6 and the ROM circuit 3 become unnecessary.

As explained above, according to the present invention, there is a plurality of read-only memory mounting sections and random access memory mounting sections set on a board, and a plurality of read-only memory mounting sections and random access memory mounting sections having different memory map patterns. a non-volatile memory in which a memory map has been written; a map mode selection switch that selectively selects a desired one from among the memory maps written in the non-volatile memory; and an address signal supplied from the outside to select the map mode. Equipped with a memory control circuit that creates a memory control signal from the output obtained by decoding based on the memory map selected by the switch, no matter how the memory map changes, the printed circuit board pattern etc. will not change in any way. You can respond without any problems. As a result, the same memory board can be manufactured regardless of the model, so productivity can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an example of a memory map, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing an example of the memory map in the same embodiment. 2...RAM circuit (random access memory mounting part), 3...ROM circuit (read-only memory mounting part), 4...Map setting ROM (non-volatile memory), 7...Map mode selection switch, 8...
Decode circuit (memory control circuit).

Claims (1)

[Claims] 1. A read-on memory mounting section and a random access memory mounting section set on a board, and a non-volatile memory in which a plurality of memory maps having different memory map patterns of the read-only memory mounting section and the random access memory mounting section are written. a map mode selection switch that selectively selects a desired one from among the memory maps written in the nonvolatile memory; and a map mode selection switch that decodes an address signal supplied from the outside based on the memory map selected by the map mode selection switch. 1. A memory circuit comprising: a memory control circuit that generates a memory control signal from an output obtained from the memory control circuit.