JPS6386049A - Microcomputer - Google Patents

Abstract

PURPOSE:To secure electrical protection of data written into a read-only memory EEPROM by setting the EEPROM into a specific address space and then controlling an EEPROM excepting for those set in the specific address space by the output of the EEPROM cell. CONSTITUTION:A microcomputer contains an EEPROM 21 mapped into a specific address space, a specific address selection decoder 20, and a control circuit 22 which functions to control an EEPROM cell 1 via the EEPROM 21. The circuit 22 produces a signal to inhibit the operation of an X address decoder 3. Under such conditions, an X address decoder 3 which selects the cell 1 does not function even though the control signals are inputted through terminals 36-38 to perform erasion and write/read actions to the cell 1. Thus these actions are impossible to the cell 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer incorporating an electrically erasable and programmable read-only memory (referred to as EEPROM).

[Conventional technology]

FIG. 4 shows an example of a microcomputer incorporating a conventional EEPROM. The EEPROM built into a conventional microcomputer (hereinafter referred to as a microcomputer) is an EE
PROM cell 1. Y address selector 2-a, write/read control circuit 2-a, X address decoder 3. Write/read data switching circuit 4. Address latch5. Address manual buffer 6, EEPROM data input/output buffer 7
゜EEPROM control buffer y8. It is composed of an EEPROM control circuit 9. 38 is an input terminal for signals that control writing, reading, and erasing in EEPROM cells; 36 is an EE terminal;
PROM address input terminal 37 is an input/output terminal for EEPROM data.

When any one of the erase signal, write signal, or read signal is a valid input to the terminal 38, the EEPROM control circuit 9 outputs the address latch 5. It controls the input circuit of the write/read data switching circuit 4 and invalidates the address signal and data from the central processing unit 10 (hereinafter referred to as CPU). Also, at this time, a signal from the address input terminal 36 is input to the X address decoder via the address input buffer 6 and the address latch, while the input/output terminal 37
A signal from the EEPROM data input/output buffer 7 connected to the EEPROM cell 1 is input as a valid signal to the Y address selector 2-a and the write/read control circuit 2-b via the data switching circuit, and the EEPROM cell 1 is erased or written, or The read operation is controlled.

[Problem that the invention seeks to solve]

The conventional microcontroller with built-in EEPROM mentioned above is E
Regardless of the content of data stored in the EPROM, erasing, writing, or reading operations can be performed by erasing, writing, or reading control signals and address signals input from external terminals. Therefore, with conventional microcontrollers, even when the instructions that command the execution of the CPU and the constants necessary for executing the instructions are stored in the EEPROM, there is no way to check whether the data exists or not. When a write operation or an erase operation is performed on the EEPROM that stores necessary information, the EE
This has the disadvantage that the information written in the PROM may be destroyed or erased.

[Means for solving problems]

The microcomputer of the present invention includes a writable read-only memory cell provided in a specific address space of an electrically erasable and writable read-only memory, and a group of control gates connected to the read-only memory cell. The control gate group includes a control circuit that generates a control signal for inhibiting erasing and writing of an electrically erasable and writable read-only memory mapped to an address space other than the specific address space.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microcomputer according to the present invention. The feature of this microcontroller is that the EEPROM 21.0 is mapped to a specific address space. E E by the specific address selection decoder 20 and EEPROM 21
It has a control circuit 22 for controlling PR'OM. FIG. 2 shows a specific logic circuit of the control circuit 22, and the operation of this embodiment will be explained. After writing data to the EEPROM cell 1 using the same means as in the conventional example described above, if the written data is to be protected, a specific address signal is input from the external address input terminal 36, and the specific address selection decoder 20 selects the specific address. By selecting one of the EEPROM cells 51 to 54 mapped in the space and inputting a write signal from the EEFROM control terminal 38, the EEPROM cell 51 is
Write to any one of 54 to 54.

In the example shown in FIG. 2, the data written to any of the EEPROM cells 51 to 54 is controlled by inputting the outputs of the EEPROM cells 51 to 54 and forming an even parity generation circuit using exclusive OR circuits 61, 62, and 63. The control circuit 22 generates a CST signal that inhibits the operation of the X address decoder 3. Therefore, from now on, the terminal 36,
Erase to EEPROM cell 1 by 37°38,
Even if a control signal for writing or reading is input, the BEP
Since the X address decoder 3 for selecting the ROM cell 1 does not function, it is not possible to erase, write, or read the EEPROM cell 1.

In addition, when the data protection function of EEPROM cell 1 is activated by the above-mentioned operation, in order to cancel the protection function, input a specific address signal from the address input terminal 36, and input the specific address signal to the EBPROM cell 1 mapped to the specific address space.
Cells 51 to 54 are selected, and a write signal from terminal 38 is used to write to cells other than the EEFROM cells that have achieved the protection function. In the case of Fig. 2, EEPROM cells 51~
Since the output of 54 is connected to the control circuit 22 as an even parity circuit, the above operation causes two EEPRO
The output of the M cell becomes "l", the outputs of the other two EEPROM cells become "0", the C3T signal that inhibits the operation of the X address decoder becomes "0", and the inhibit function of the X address decoder is released. . Therefore, from now on, terminal 3 (5, 37
, 38 make it possible to control erasing, writing, and reading from the EEPROM cell 1. These series of operations are mapped to a specific address space (in the example shown in Figure 2, E
(4) EPROM cells 51 to 54) Repeating as many times as the number of EEPROM cells is effective.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The first embodiment is an EE mapped to a specific address space.
The PROM cell protects or releases all erasing, writing, and reading of the EEPROM cell 1, and in FIG. 1 to the logic output circuit 33, and the individual cell outputs of the EEPROM cells 51 to 54 select the address line of the EEPROM cell 1.
This indicates that the output of the R circuit is prohibited.

To explain FIG. 3 in more detail, EEPROM cell 5
1 is an address decoder circuit that selects the address line of EEPROM cell 1. The outputs Xo and Xl of EEPROM cell 5
2, address decoder circuit outputs X2 to Xj that select the address line of EEPROM cell 1 are connected to EEPROM cell 5.
3 is an address decoder circuit that selects the address line of EEPROM cell 1. Outputs X, 41 to X, -4 are EEPROM
The M cell 54 prohibits the address decoder circuit outputs X, -3 to X, which select the address line of the EEPROM cell 1, from becoming active, and therefore the E
Protection of data in the EPROM cell 1 can be realized.

Note that EEPROM mapped to a specific address space
We have explained the case where the data is written to the cells 51-54 using the control signals from the terminals 36-38, but instead of the terminals 36-38, the CPU10 performs the same control for the EEPROM cells 51-54. It is obvious that this can be done and a similar effect can be obtained.

〔Effect of the invention〕

As explained above, the present invention provides EE in a specific address space.
By providing the PROM 21 and providing a circuit for controlling the EEPROM cells 1 other than the specific address space at the output of the cell, it is possible to electrically protect the data written in the EEPROM cells 1.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of FIG. 1, FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a block diagram of a conventional example. 1...EEPROM cell, 2-a...Y address selector, 2-b...write/read control circuit, 3...
・X address decoder, 4...Write/read data switching circuit, 5...Address latch, 6...Address input buffer, 7...EEPROM data input/output buffer, 8...EEPROM control buffer, 9.・EE
PROM control circuit, 10... CPU, 20... Specific address selection decoder, 21... EEPROM in specific address space, 22... Control circuit for EEPROM in specific address space, 36... Address input Terminal, 37... EEPROM data input/output terminal, 38.
. . EEPROM control terminals, 51-54 . . . EEPROM cells in a specific address space, 61-63 . . . exclusive OR circuit, CST .

Claims (1)

[Claims] A writable read-only memory cell provided in a specific address space of an electrically erasable and writable read-only memory, and a control gate group connected to the read-only memory cell, the control gate group being connected to the specific address. 1. A microcomputer comprising: a control circuit that generates a control signal for inhibiting erasing and writing of an electrically erasable and writable read-only memory mapped to an address space other than space.