JPS5858666A - デ−タ処理装置 - Google Patents
デ−タ処理装置Info
- Publication number
- JPS5858666A JPS5858666A JP56156193A JP15619381A JPS5858666A JP S5858666 A JPS5858666 A JP S5858666A JP 56156193 A JP56156193 A JP 56156193A JP 15619381 A JP15619381 A JP 15619381A JP S5858666 A JPS5858666 A JP S5858666A
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- memory
- cache
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56156193A JPS5858666A (ja) | 1981-10-02 | 1981-10-02 | デ−タ処理装置 |
US06/320,934 US4481573A (en) | 1980-11-17 | 1981-11-13 | Shared virtual address translation unit for a multiprocessor system |
CA000390161A CA1173567A (en) | 1980-11-17 | 1981-11-16 | Shared virtual address translation unit for a multiprocessor system |
EP81109719A EP0052370B1 (en) | 1980-11-17 | 1981-11-16 | A virtual storage data processing system |
DE8181109719T DE3176512D1 (en) | 1980-11-17 | 1981-11-16 | A virtual storage data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56156193A JPS5858666A (ja) | 1981-10-02 | 1981-10-02 | デ−タ処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5858666A true JPS5858666A (ja) | 1983-04-07 |
JPS6113261B2 JPS6113261B2 (enrdf_load_stackoverflow) | 1986-04-12 |
Family
ID=15622400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56156193A Granted JPS5858666A (ja) | 1980-11-17 | 1981-10-02 | デ−タ処理装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5858666A (enrdf_load_stackoverflow) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60221851A (ja) * | 1984-02-17 | 1985-11-06 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | メモリ・アクセス・コントローラを具えるデータ処理装置 |
JPH01280860A (ja) * | 1988-05-06 | 1989-11-13 | Hitachi Ltd | マルチポートキヤツシユメモリを有するマルチプロセツサシステム |
US4933835A (en) * | 1985-02-22 | 1990-06-12 | Intergraph Corporation | Apparatus for maintaining consistency of a cache memory with a primary memory |
US6230260B1 (en) | 1998-09-01 | 2001-05-08 | International Business Machines Corporation | Circuit arrangement and method of speculative instruction execution utilizing instruction history caching |
-
1981
- 1981-10-02 JP JP56156193A patent/JPS5858666A/ja active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60221851A (ja) * | 1984-02-17 | 1985-11-06 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | メモリ・アクセス・コントローラを具えるデータ処理装置 |
US4933835A (en) * | 1985-02-22 | 1990-06-12 | Intergraph Corporation | Apparatus for maintaining consistency of a cache memory with a primary memory |
JPH01280860A (ja) * | 1988-05-06 | 1989-11-13 | Hitachi Ltd | マルチポートキヤツシユメモリを有するマルチプロセツサシステム |
US6230260B1 (en) | 1998-09-01 | 2001-05-08 | International Business Machines Corporation | Circuit arrangement and method of speculative instruction execution utilizing instruction history caching |
Also Published As
Publication number | Publication date |
---|---|
JPS6113261B2 (enrdf_load_stackoverflow) | 1986-04-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4481573A (en) | Shared virtual address translation unit for a multiprocessor system | |
US5802582A (en) | Explicit coherence using split-phase controls | |
US4400770A (en) | Cache synonym detection and handling means | |
US6625698B2 (en) | Method and apparatus for controlling memory storage locks based on cache line ownership | |
JP3102495B2 (ja) | 仮想記憶管理方法 | |
US7620954B2 (en) | Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors | |
JPH0743670B2 (ja) | ストアスルーキャッシュ管理システム | |
WO1988006760A2 (en) | Central processor unit for digital data processing system including write buffer management mechanism | |
JP2004054931A (ja) | 分散メモリマルチプロセッサシステムにおけるメモリ移行のためのシステムおよび方法 | |
JP3814521B2 (ja) | データ処理方法および装置 | |
JP2007533014A (ja) | ライトバックキャッシュにおいてスヌーププッシュ処理やスヌープキル処理が同時発生しているときのライトバック処理をキャンセルするためのシステムおよび方法 | |
JPH0519176B2 (enrdf_load_stackoverflow) | ||
JPS5858666A (ja) | デ−タ処理装置 | |
CA1290861C (en) | Computer system architecture implementing split instruction and operand cache line-pair-state management | |
JP2813182B2 (ja) | マルチプロセッサコンピュータ複合装置 | |
JPH055137B2 (enrdf_load_stackoverflow) | ||
JPS5864690A (ja) | キヤツシユメモリ制御方法 | |
JPH0715667B2 (ja) | データ処理装置 | |
JPH056706B2 (enrdf_load_stackoverflow) | ||
JPH03230238A (ja) | キャッシュメモリ制御方式 | |
JPS6138504B2 (enrdf_load_stackoverflow) | ||
JPS6153747B2 (enrdf_load_stackoverflow) | ||
JP2844679B2 (ja) | アクセス制御方法及び情報処理装置 | |
JP3381080B2 (ja) | 処理の中断が可能な排他制御方式 | |
JP3532977B2 (ja) | キャッシュメモリ装置 |