JPS5857818A - Switching circuit - Google Patents

Switching circuit

Info

Publication number
JPS5857818A
JPS5857818A JP56157086A JP15708681A JPS5857818A JP S5857818 A JPS5857818 A JP S5857818A JP 56157086 A JP56157086 A JP 56157086A JP 15708681 A JP15708681 A JP 15708681A JP S5857818 A JPS5857818 A JP S5857818A
Authority
JP
Japan
Prior art keywords
potential
output
reference voltage
comparator
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56157086A
Other languages
Japanese (ja)
Other versions
JPH0365049B2 (en
Inventor
Yoshiyuki Yamamoto
義之 山本
Seiichi Hashimoto
清一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56157086A priority Critical patent/JPS5857818A/en
Publication of JPS5857818A publication Critical patent/JPS5857818A/en
Publication of JPH0365049B2 publication Critical patent/JPH0365049B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a stable output even with a minute AC component included in an input signal, by changing the 1st and 2nd reference voltage with the output of the 2nd comparator and picking up an output signal from the output of the 1st comparator. CONSTITUTION:When a signal applied to an input terminal 1 is changed from high to low potential, the signal is compared with the 1st reference voltage 5 at the 1st comparator 2, an output 4 changes from high to low potential, the output 4 and the 2nd reference voltage 7 are compared at the 2nd comparator 6 and the potential at the point C changes from high to low potential. Through the change of the potential at the point C, the 2nd reference voltage 7 is changed to a high voltage to lower the potential at the point C acceleratingly. Through the rapid change in the potential of the point C, the 1st reference voltage 5 is changed to a high value to bring the potential of the output 4 to a sufficiently stable low potential practically even if a minute AC signal such as noise is included in the input 1. When the input 1 changes from low to high potential, the 1st and 2nd reference voltages 5, 7 are changed to a low value, and the provision of excellent hysteresis characteristics as stated above can offer stable outputs.

Description

【発明の詳細な説明】 本発明は入力信号レベルがある値以上にある時に、出力
信号を発生するスイッチング回路に関するもので、入力
信号に雑音などの微小な交流成分が含まれていても安定
した出力が得られるよう構成したものである。
[Detailed Description of the Invention] The present invention relates to a switching circuit that generates an output signal when the input signal level exceeds a certain value, and the present invention relates to a switching circuit that generates an output signal when the input signal level exceeds a certain value. It is configured so that output can be obtained.

従来のスイッチング回路の1例のブロック図分第1図及
び第2図に示す。
A block diagram of an example of a conventional switching circuit is shown in FIGS. 1 and 2.

第1図に示すスイッチング回路において、比較器とき、
第3図に示す交流成分を含む入力信号が入力端1に印加
されると出力端4には第4図に示す様な不安定な出力が
現われる。
In the switching circuit shown in FIG. 1, when the comparator
When an input signal containing an alternating current component as shown in FIG. 3 is applied to the input end 1, an unstable output as shown in FIG. 4 appears at the output end 4.

次に第2図に示すスイッチング回路において、第3図に
示す交流成分を含む入力信号を入力端1に印加し、比較
器2の利得を無限大とし、基準電圧発生器6の出力を出
力端4が高電位から低電位に移ったときにはVlからv
5へ、低電位から高電位に移ったときにはv3からvl
に切換える様にすると出力端4には第5図に示す様な安
定した出力が得られる。この場合の入出力特性は第6図
に示す様ないわゆるヒステリシス特性を示す。△Vはヒ
ステリシス幅で為シ、スイッチング回路の出力端4に接
続される外部回路などに支配される条件から決定される
Next, in the switching circuit shown in FIG. 2, the input signal containing the AC component shown in FIG. 3 is applied to the input terminal 1, the gain of the comparator 2 is made infinite, and the output of the reference voltage generator 6 is applied to the output terminal 4 moves from high potential to low potential, from Vl to v
5, when moving from low potential to high potential, from v3 to vl
5, a stable output as shown in FIG. 5 can be obtained at the output terminal 4. The input/output characteristics in this case exhibit so-called hysteresis characteristics as shown in FIG. ΔV is a hysteresis width, which is determined based on conditions controlled by an external circuit connected to the output terminal 4 of the switching circuit.

ここで、現実にはスイッチング回路の利得が有限である
から第6図の入出力特性は第7図の様になる。ここで、
比較器2の利得は入力レベルと無関係に有限且つ一定と
し、基準電圧発生器6は入力がVa に達するとその出
力が切換わp比較器2とで形成している閉ループに正帰
還がかかつて出力端4の電位が非可逆的に変化するもの
と仮定する。
In reality, the gain of the switching circuit is finite, so the input/output characteristics shown in FIG. 6 become as shown in FIG. 7. here,
The gain of the comparator 2 is set to be finite and constant regardless of the input level, and when the input of the reference voltage generator 6 reaches Va, its output is switched and positive feedback is created in the closed loop formed with the p comparator 2. It is assumed that the potential at the output terminal 4 changes irreversibly.

第7図において、△v1あるいはΔ■3の領域では、比
較器2が線型増幅器として動作し、入力に含まれる微小
な交流成分が増幅されて出力に現われるので、出力端4
に接続される外部回路の検出レベルが丁度Vaに等しい
場合は問題ないが、検出レベルがVa  とは異なる場
合や検出レベルがI[を持つ場合が一般的であシ、△■
1あるいはΔ■3の領域の一部分で、外部回路が不安定
に動作する。
In FIG. 7, in the region of Δv1 or Δ■3, the comparator 2 operates as a linear amplifier, and the minute AC component included in the input is amplified and appears in the output, so the output terminal 4
There is no problem if the detection level of the external circuit connected to is exactly equal to Va, but it is common that the detection level is different from Va or the detection level is I[, △■
In a part of the region of 1 or Δ■3, the external circuit operates unstablely.

したがって、Δv1および△■5を極力小さくすること
が、安定した出力が得らnるスイッチング回路の条件で
あり、そのためには比較器2の利得を可能な限り大きく
することが当然要求されることであるが種々のマイナス
要因によって限度がある。本発明は、比較器2の利得を
最大限大きくした上でさらに△v1および△V3i小さ
くし、出力を安定化する回路を提供しようとするもので
ある。
Therefore, making Δv1 and Δ■5 as small as possible is a condition for a switching circuit that can obtain a stable output, and to that end, it is naturally required to make the gain of comparator 2 as large as possible. However, there are limits due to various negative factors. The present invention aims to provide a circuit that increases the gain of the comparator 2 to the maximum extent, further reduces Δv1 and ΔV3i, and stabilizes the output.

以下その内容を添付図面を用いて説明する。The contents will be explained below using the attached drawings.

本発明の一実施例のブロック図を第8図に示tすケわち
、出力端4の出力信号と第2の基準電圧発生冊子の出力
信号とを入力とする第2の比較器6の出力で基準電圧発
生器5および前記第2の基準電圧発生器7を駆動するも
のである。ここで第2の比較器6の利得は入力レベルと
は無関係に有限且つ一定であり、その出力は後記の具体
例と対応させるため入力に対して逆相と仮定するが、同
相であっても何ら問題はない。第2の基準電圧発生冊子
の出力は、第2の比較器6の出力である0点の電位が低
電位から高電位へ移ったときにl′ivbからVaへ、
高電位から低電位に移ったときにはvOからvbへ切換
える。ここでVb ) Va ) Voの関係が成立し
、出力端4に接続される外部回路の検出レベルは中心値
がVa にほぼ等しく且つその幅がVb −Vaに比べ
て充分小さいものと仮定すると、第8図に示すスイッチ
ング回路の入出力特性は第9図のようになる。第9図に
おいて、Dは第8図C点の電位を示し、線型動作の領域
はΔY’l  およびΔ≠と従来回路の△v1および△
V3に比べて大幅に小さくなっている。基準電圧発生器
7の出力であるvbとVaO差を可能な限り大きくすれ
ば、Δv1および△≠はさらに小さくなる。またヒステ
リシス幅△V′(= V’5−V’1 )は従来回路に
比べて小さくなっているが前述のように外的要因に支配
されるので、従来回路と同等の幅あるいは所望の幅にな
るように定数設定を行なえばよい。
A block diagram of an embodiment of the present invention is shown in FIG. The output drives the reference voltage generator 5 and the second reference voltage generator 7. Here, the gain of the second comparator 6 is finite and constant regardless of the input level, and its output is assumed to be in opposite phase to the input in order to correspond to the specific example described later, but even if it is in phase, There is no problem. The output of the second reference voltage generation booklet changes from l'ivb to Va when the potential at the 0 point, which is the output of the second comparator 6, moves from a low potential to a high potential.
When the potential changes from high to low, it switches from vO to vb. Here, assuming that the relationship Vb ) Va ) Vo holds true, and that the detection level of the external circuit connected to the output terminal 4 has a central value approximately equal to Va and that its width is sufficiently smaller than Vb - Va, The input/output characteristics of the switching circuit shown in FIG. 8 are as shown in FIG. 9. In FIG. 9, D indicates the potential at point C in FIG. 8, and the region of linear operation is ΔY'l and Δ≠, and Δv1 and Δ
It is significantly smaller than V3. If the difference between vb and VaO, which is the output of the reference voltage generator 7, is made as large as possible, Δv1 and Δ≠ will become even smaller. Also, the hysteresis width △V' (= V'5 - V'1) is smaller than that of the conventional circuit, but as mentioned above, it is controlled by external factors, so it may be the same width as the conventional circuit or the desired width. All you have to do is set the constants so that

第9図では、わかり易くするために比較器2および6の
利得を誇張して小さく記しているので、実際には△v1
およびへ盾は極めて小さいものであり、本発明によって
、入力に交流成分が含まれる場合でも、実用上充分に安
定した出力が得られるスイッチング回路を提供すること
が可能である。
In FIG. 9, the gains of comparators 2 and 6 are exaggerated and shown small for the sake of clarity, so in reality △v1
The present invention makes it possible to provide a switching circuit that can provide a sufficiently stable output for practical use even when the input contains an alternating current component.

第10図に本発明の具体回路例を示す。本回路はIC化
に適するように考慮して設計された例である。第10図
において、9〜16が第1の比較器2′lr:構成し、
16〜18が第1の基準電圧発生器6を構成し、21〜
24が第2の比較器6を構成し、26と26が第2の基
準電圧発生器8を構成し、27〜36は出力端4に接続
された外部回6 。
FIG. 10 shows a specific circuit example of the present invention. This circuit is an example designed to be suitable for IC implementation. In FIG. 10, 9 to 16 constitute a first comparator 2'lr;
16 to 18 constitute the first reference voltage generator 6, and 21 to 18 constitute the first reference voltage generator 6.
24 constitutes the second comparator 6, 26 and 26 constitute the second reference voltage generator 8, and 27 to 36 constitute the external circuit 6 connected to the output terminal 4.

路を構成し、36は正電源VC10である。細部を説明
すると、1は入力信号が印加される入力端で、バイアス
用抵抗9を介して接地されたトランジスタ10のペース
に接続する。トランジスタ10゜11は差動アンプを構
成し、互いの共通エミッタは定電流源12を介して接地
し、トランジスタ10のコレクタは正電源Vaaに接続
し、トランジスタ11のコレクタは負荷抵抗13を介し
て正電源VOOに接続し且つエミッタホロワトランジス
タ140ベースに接続する。トランジスタ11のペース
はバイアス抵抗16を介して正電源Vaaに接続し且つ
定電流源18を介して接地し且つ電位シフト用抵抗17
を介してスイッチングトランジスタ2oのエミッタに接
続する。トランジスタ14のエミッタはレベルシフト用
抵抗19を介してスイッチング回路の出力端4および定
電流源15を介して接地されたトランジスタ22のペー
スに接続する。トランジスタ22,23は差動アンプを
構成し、互いの共通エミッタは電流源21を介して正電
源VOOに接続し、トランジスタ22のコレフタは負荷
抵抗24を介して接地し且つトランジスタ2oのベース
に接続し、トランジスタ23のコレクタは接地し、ベー
スは電位シシト用抵抗25を介じて定電圧源26に接続
し且つトランジスタ2oのコレクタに接続する。
36 is a positive power supply VC10. To explain the details, 1 is an input terminal to which an input signal is applied, and is connected to the grounded transistor 10 via a bias resistor 9. Transistors 10 and 11 constitute a differential amplifier, their common emitters are grounded via a constant current source 12, the collector of the transistor 10 is connected to the positive power supply Vaa, and the collector of the transistor 11 is connected via a load resistor 13. Connected to the positive power supply VOO and to the base of the emitter follower transistor 140. The pace of the transistor 11 is connected to the positive power supply Vaa via a bias resistor 16, grounded via a constant current source 18, and connected to a potential shift resistor 17.
It is connected to the emitter of the switching transistor 2o via. The emitter of the transistor 14 is connected via a level shift resistor 19 to the output terminal 4 of the switching circuit and to the grounded terminal of the transistor 22 via a constant current source 15. Transistors 22 and 23 constitute a differential amplifier, and their common emitters are connected to the positive power supply VOO via a current source 21, and the collector of transistor 22 is grounded via a load resistor 24 and connected to the base of transistor 2o. The collector of the transistor 23 is grounded, and the base is connected to a constant voltage source 26 via a potential adjustment resistor 25 and to the collector of the transistor 2o.

トランジスタ31 ’、 32は差動アンプ全構成し、
互いの共通エミッタ(l−j:電流源33を介して接地
し、夫々のコレクタはそれぞれ負荷抵抗29.30i介
して正電源VOOに接続し且つ出力端34 、35に接
続する。トランジスタ31のベースはバイアス抵抗27
を介して定電圧源26に接続し且つバイアス抵抗28を
介して接地し、トランジスタ32のベースは前記出力端
4に接続する。
Transistors 31' and 32 constitute the entire differential amplifier,
Their common emitters (l-j: grounded via the current source 33, their respective collectors connected to the positive power supply VOO via the load resistors 29 and 30i, and connected to the output terminals 34 and 35. The base of the transistor 31 is bias resistor 27
The transistor 32 is connected to a constant voltage source 26 through a bias resistor 28 and grounded through a bias resistor 28, and the base of the transistor 32 is connected to the output terminal 4.

次に第10図および第11図に従東て、動作を説明する
。第10図D′点の電位が低いとき、スイッチングトラ
ンジスタ2oFi、オフしているので抵抗17および2
5における電圧降下はほとんど零である。このときのE
点およびF点の電位をそれぞれ第11図のvlおよびv
bに設定する。D′点の電位が高くなるとトランジスタ
20はオンし定電圧源26から抵抗26および17を介
して定電流源18へ電流が流れ、抵抗16牽流れる電流
が減少する。したがってE点の電位はvl  より高く
なり、F点の電位はvbより低くなる。
Next, the operation will be explained with reference to FIGS. 10 and 11. When the potential at point D' in FIG. 10 is low, the switching transistor 2oFi is off, so the resistors 17 and 2
The voltage drop at 5 is almost zero. E at this time
The potentials at point and F point are respectively vl and v in FIG.
Set to b. When the potential at point D' increases, transistor 20 is turned on, and current flows from constant voltage source 26 to constant current source 18 via resistors 26 and 17, and the current flowing through resistor 16 decreases. Therefore, the potential at point E becomes higher than vl, and the potential at point F becomes lower than vb.

このときのE点およびF点の電位をそれぞれ第11図の
■3およびVaに設定する。またG点の電位は第11図
のVoに近い値に設定する。なおE点の電位を変えるた
めに抵抗17を電流源18に結合し、電流源18の電流
を変化させるように構成することもできる。上記の様な
条件の下で、入力端1がvbより高いとき、トランジス
タ10.23゜32がオンし、トランジスタ11,22
.31がオフし、D′点の電位は低いのでE点およびF
点の電位はそれぞれvlおよびvbになっている。した
がって入力端1の電位がvb  まで低下しても出力端
4の電位は全く変化せず、入力端1の電位がV’1に近
い値まで低下すると、まず差動アンプ10゜11が動作
を始めて出力端4の電位が第11図Hに沿って低下し、
続いて差動アンプ22,23が動作を始めてD′点の電
位が第11図Iのように上昇する。入力端1の電位がv
l  になるとスイッチングトランジスタ2oがオンし
E点の電位を押し上げる。その結果、出力端4の電位は
、瞬間的に且つ非可逆的に最低電位VLに到達する。こ
の間、差動アンプ31.32は線型動作の領域が第11
図にの様な設定になっているので完全なスイッチング動
作を行ない出力端34の電位は第11図1のように変化
する。
The potentials at point E and point F at this time are set to 3 and Va in FIG. 11, respectively. Further, the potential at point G is set to a value close to Vo in FIG. Note that in order to change the potential at point E, the resistor 17 may be coupled to the current source 18, and the current of the current source 18 may be changed. Under the above conditions, when input terminal 1 is higher than vb, transistor 10.23°32 is turned on, and transistors 11 and 22 are turned on.
.. 31 is turned off and the potential at point D' is low, so points E and F
The potentials at the points are vl and vb, respectively. Therefore, even if the potential at input terminal 1 drops to Vb, the potential at output terminal 4 does not change at all, and when the potential at input terminal 1 drops to a value close to V'1, first differential amplifier 10°11 stops operating. For the first time, the potential at the output terminal 4 decreases along H in FIG.
Subsequently, the differential amplifiers 22 and 23 start operating, and the potential at point D' rises as shown in FIG. 11I. The potential of input terminal 1 is v
When the voltage reaches l, the switching transistor 2o turns on and raises the potential at point E. As a result, the potential at the output end 4 instantaneously and irreversibly reaches the lowest potential VL. During this period, the differential amplifiers 31 and 32 are in the 11th linear operation region.
Since the settings are as shown in the figure, a complete switching operation is performed and the potential at the output terminal 34 changes as shown in FIG. 11.

トランジスタ2oがオンするとF点の電位もvbからV
aへと押し下げられ、入力端1の電位が再び盾に上昇す
るまで待期する。入力端1の電位がvl  よりも低い
電位から上昇する場合も同様な説明が成立するのでここ
では省略する。また第10図のスイッチング回路が上記
の様な動作をより確実に行なうために、抵抗26と並列
に容量を接続しF点の電位変化をE点の電位変化より遅
らせる方法が効果的である。
When transistor 2o turns on, the potential at point F also changes from vb to V.
Wait until the potential at the input terminal 1 rises again. A similar explanation holds true even when the potential at the input terminal 1 rises from a potential lower than vl, so the explanation will be omitted here. In order for the switching circuit shown in FIG. 10 to more reliably operate as described above, it is effective to connect a capacitor in parallel with the resistor 26 so that the change in potential at point F is delayed from the change in potential at point E.

以上説明したように本発明によれば、入力に微小な交流
成分が含まれる場合でも、実用上充分に安定した出力が
得られるスイッチング回路を得ることが可能であり、さ
らに出力端4に接続する外部回路との組合わせによって
理想的なスイッチング回路ケ実現することが可能である
As explained above, according to the present invention, it is possible to obtain a switching circuit that can obtain a sufficiently stable output for practical use even when the input contains minute alternating current components. It is possible to realize an ideal switching circuit by combining it with an external circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はそれぞれ従来のスイッチング′回路の
ブロック図、第3図、第4図、第5図、第6図および第
7図は従来例の動作説明崗、第8図は本発明の一実施例
のブロック図、第9図は本発明の詳細説明図、第10図
は本発明の実施例に基づく回路図、第11図は同回路の
動作説明図である。 1・・・−・・入力端、2,6・・・−・・比較器、3
・・・・・・基準電圧源、4・・・・・・出力端、5,
7・・・・・・基準電圧発生器。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名@ 
1 図 2 第3図 第4図 第5図 第6図 第7図 “″3人カー 第8図 第9図
Figures 1 and 2 are block diagrams of conventional switching circuits, Figures 3, 4, 5, 6, and 7 are explanations of the operation of the conventional switching circuit, and Figure 8 is a block diagram of a conventional switching circuit. FIG. 9 is a block diagram of an embodiment of the invention, FIG. 9 is a detailed explanatory diagram of the invention, FIG. 10 is a circuit diagram based on the embodiment of the invention, and FIG. 11 is an explanatory diagram of the operation of the same circuit. 1...--Input end, 2, 6...--Comparator, 3
...Reference voltage source, 4...Output end, 5,
7...Reference voltage generator. Name of agent: Patent attorney Toshio Nakao and 1 other person @
1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 3-person car Figure 8 Figure 9

Claims (1)

【特許請求の範囲】[Claims] 入力信号と第1の基準電圧とを比較して出力を得る第1
の比較器と、その第一1の比較器の出力と第2の基準電
圧とを比較して出力を得る第2の比較器とから成り、第
2の比較器の出力で第1の基準電圧および第2の基準電
圧を変え、第1の比較器の出力から出力信号を取シ出す
ことを特徴とするスイッチング回路。
a first voltage source that compares the input signal with a first reference voltage to obtain an output;
and a second comparator that obtains an output by comparing the output of the first comparator and a second reference voltage, and the output of the second comparator is the first reference voltage. and a switching circuit that changes a second reference voltage and extracts an output signal from the output of the first comparator.
JP56157086A 1981-10-01 1981-10-01 Switching circuit Granted JPS5857818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56157086A JPS5857818A (en) 1981-10-01 1981-10-01 Switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56157086A JPS5857818A (en) 1981-10-01 1981-10-01 Switching circuit

Publications (2)

Publication Number Publication Date
JPS5857818A true JPS5857818A (en) 1983-04-06
JPH0365049B2 JPH0365049B2 (en) 1991-10-09

Family

ID=15641934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56157086A Granted JPS5857818A (en) 1981-10-01 1981-10-01 Switching circuit

Country Status (1)

Country Link
JP (1) JPS5857818A (en)

Also Published As

Publication number Publication date
JPH0365049B2 (en) 1991-10-09

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