JPS5857782A - Circuit board and method of producing same - Google Patents

Circuit board and method of producing same

Info

Publication number
JPS5857782A
JPS5857782A JP15666981A JP15666981A JPS5857782A JP S5857782 A JPS5857782 A JP S5857782A JP 15666981 A JP15666981 A JP 15666981A JP 15666981 A JP15666981 A JP 15666981A JP S5857782 A JPS5857782 A JP S5857782A
Authority
JP
Japan
Prior art keywords
wiring board
layer
conductor
hole
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15666981A
Other languages
Japanese (ja)
Inventor
野口 節生
五島 隆夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15666981A priority Critical patent/JPS5857782A/en
Publication of JPS5857782A publication Critical patent/JPS5857782A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は配線板およびその製造方法に関し、特に絶縁基
板上に絶縁被僚ワイヤの所望回路パターンを布?is固
着しズなる配線板およびその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring board and a method for manufacturing the same, and more particularly, the present invention relates to a wiring board and a method for manufacturing the same, and more particularly, to a wiring board and a method for manufacturing the same, and more particularly, to fabricate a desired circuit pattern of insulated wires on an insulated substrate. The present invention relates to a wiring board that does not stick and a method of manufacturing the same.

近年、絶縁基板上に必要に応じて銅箔などの導体パター
ンを形成した上に絶縁性を有する接着剤層(以下、接着
層と称す)を介して絶縁被覆ワイヤの所望回路パターン
を布線固着した後、所望位置に貫通孔を穿設し、その貫
通孔の壁面に金属導体層を形成し絶縁被覆ワイヤの芯線
と接続することKよりバター7間を電気的に接続した配
線板が用いられるようになってき九。
In recent years, a conductor pattern such as copper foil is formed on an insulating substrate as necessary, and a desired circuit pattern of insulated wire is fixedly wired via an insulating adhesive layer (hereinafter referred to as the adhesive layer). After that, a through hole is drilled at a desired position, a metal conductor layer is formed on the wall of the through hole, and it is connected to the core wire of the insulated wire.A wiring board is used in which the butter 7 is electrically connected. It's starting to look like this.

一般に、この種の配線板には次のような特徴がある。信
号回路として絶縁被覆ワイヤを使用するため信号回路を
同一平面で交差させることが可能であり、通常の印刷配
線板における表裏2面分のパターンを1面にて収容する
ことができる。このため表裏接続用のスルホール、いわ
ゆるバイアホールが不用となる。さらにバイアホールが
不用なために配線径路を決定する自動針手法において配
線可能なチャネル数が増加し、高い配線収容率と実装の
高密度化を計れる。また、回路パターンの原画および写
真類が不用となる。とくに回路パターンの変更を必要と
する場合には、絶縁被覆ワイヤを固着するためのワイヤ
布線枠のテークを部分的に変更するだけでよく、原画や
写真を作り直す費用と時間を削減できる。
Generally, this type of wiring board has the following characteristics. Since insulated wires are used as signal circuits, it is possible to intersect the signal circuits on the same plane, and patterns for two sides of a normal printed wiring board can be accommodated on one side. This eliminates the need for through holes, so-called via holes, for connecting the front and back sides. Furthermore, since via holes are not required, the number of channels that can be wired increases using the automatic needle method that determines wiring routes, allowing for higher wiring accommodation and higher packaging density. In addition, original circuit pattern drawings and photographs become unnecessary. In particular, if the circuit pattern needs to be changed, it is only necessary to partially change the take of the wire wiring frame for fixing the insulated wire, reducing the cost and time of recreating original drawings and photographs.

この種の従来配線板の代表的な一例をfjlc1図およ
び第2図を参照して説明する。第1図(a)の如く無電
解めっき用触媒を含む絶縁基板】の上に必要に応じて、
例えば電源層、接地島として使用することができるよう
にパターン化した銅箔層2を片面または両面に形成し、
次に第1図(b)の如く、絶縁基板1および銅箔層2に
接して無電解めっき用触媒を含む接着層3を形成した後
、第1図(C)の如く信号回路としての絶縁被横ワイヤ
4の所望回路パターンを、例えば数値IIJ御式自動布
線機により、接着層3に有数固着させ、さらに第1図(
d)の如く布線固着した絶縁被接ワイヤ4による回路パ
ターンを保護し、かつ固着を確実にするために無電解め
っき用触媒を含むプリプレグを積層接着することにより
無電解めっきに対して触媒性を有する絶縁層5を形成す
る。さらに外表面に無電解めっきに対して触媒性を有し
ない非整合マスク層(以下、マスク層と称す)6を形成
した後、第1図(e)の如く所望の位置に絶縁被覆ワイ
ヤおよび銅箔層2を横切るように貫通孔7を穿設し、絶
縁被覆ワイヤ4および銅箔層2の少なくとも一部を貫通
孔7の内面に繕出させた後、無1解めっき液に浸漬する
ことにより貫通孔7の壁面に金属導体層8を形成してス
ルホールとし、第1図(0の如く、マスク6を除去して
第2図に示すような配線板を形成するものであった。
A typical example of this type of conventional wiring board will be described with reference to FIG. 1 and FIG. If necessary, on the insulating substrate containing the electroless plating catalyst as shown in Fig. 1(a),
For example, a patterned copper foil layer 2 is formed on one or both sides so that it can be used as a power supply layer or a ground island,
Next, as shown in FIG. 1(b), after forming an adhesive layer 3 containing an electroless plating catalyst in contact with the insulating substrate 1 and the copper foil layer 2, as shown in FIG. A desired circuit pattern of the transverse wire 4 is adhered to the adhesive layer 3 using, for example, a numerical IIJ type automatic wiring machine, and then the pattern shown in FIG.
In order to protect the circuit pattern formed by the insulated wire 4 fixed to the wiring as shown in d), and to ensure the fixation, a prepreg containing a catalyst for electroless plating is laminated and bonded to make it catalytic for electroless plating. An insulating layer 5 is formed. Furthermore, after forming a non-conforming mask layer (hereinafter referred to as a mask layer) 6 that does not have catalytic properties against electroless plating on the outer surface, insulated wires and copper are placed at desired positions as shown in FIG. 1(e). A through hole 7 is bored across the foil layer 2, and at least a portion of the insulated wire 4 and the copper foil layer 2 are patched onto the inner surface of the through hole 7, and then immersed in a no-solution plating solution. A metal conductor layer 8 was formed on the wall surface of the through hole 7 to form a through hole, and the mask 6 was removed as shown in FIG. 1 (0) to form a wiring board as shown in FIG. 2.

一方、最近のIC,LSI等の電子デバイスの高密度化
に伴い、配線板に要求される配線密度すなわち単位面積
当たりの配線本数は急激に増加する傾向にある。このこ
とは、従来の配線板において貫通孔を穿設し、穴壁にめ
つき導体層を形成してスルホールとし、表裏面の導体パ
ターンを電気的に接続するという発想から表裏面の対応
する位置で貫通接続させずに表裏面の所望箇所に微小径
の穴部を設けて電気的接続を達成させるという発想に切
り替える必要がある。しかし、従来のこの稲の微小径例
えば0.1 瓢φの穴部を通常の穴あけ機によって穿設
加工することはドリル折れの問題があり非常に困難であ
った。
On the other hand, with the recent increase in the density of electronic devices such as ICs and LSIs, the wiring density required for wiring boards, that is, the number of wirings per unit area, is rapidly increasing. This is based on the idea that a through hole is drilled in a conventional wiring board, a conductive layer is plated on the hole wall, and the conductor patterns on the front and back sides are electrically connected. Therefore, it is necessary to switch to the idea of establishing electrical connections by providing micro-diameter holes at desired locations on the front and back surfaces, without making through connections. However, it has been extremely difficult to drill holes with a conventional hole diameter of, for example, 0.1 mm, using a conventional hole puncher due to the problem of drill breakage.

本発明の目的は、前述の如き従来欠点を除去した新規な
配線板およびその製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a new wiring board and a method for manufacturing the same, which eliminates the drawbacks of the conventional wiring board as described above.

本発明によれば、回路パターンを有する絶縁基板上に絶
縁複機ワイヤの所望回路パターンを布線し、絶縁被接ワ
イヤを被覆する絶縁樹脂層を形成してなる配線板におい
て、少なくとも絶縁被覆ワイヤの芯線導体表面まで到達
する穴部と、穴部の内壁面および芯線導体の表面に導電
体層を設けたことを特徴とする配線板が得られる。また
絶縁基板上に絶縁性接着層を被着する工程と、絶縁性接
着層上に絶縁被覆ワイヤを布線固着する工程と、絶縁被
接ワイヤを複核する絶縁樹脂層を設ける工程と、絶縁樹
脂層の表面に無電解めっきに対(7て触媒性を有しない
絶縁体からなる非整合マスク層を形成する工程と、非整
合マスク層上からレーザ光線を照射して非整合マスク層
、絶縁樹脂層の一部を貫通して絶縁被覆ワイヤの導体に
至る穴部を設ける工程と、穴部の内壁面および絶縁被覆
ワイヤの導体表面に無電解めっきにより導電体層を形成
する工程と、非整合マスク層を除去する工程とからなる
ことを特徴とする配線板の製造方法が得られる。
According to the present invention, in a wiring board in which a desired circuit pattern of insulated composite wires is laid on an insulated substrate having a circuit pattern and an insulating resin layer is formed to cover the insulated wires, at least the insulated wires There is obtained a wiring board characterized in that a hole reaches the surface of the core conductor, and a conductor layer is provided on the inner wall surface of the hole and the surface of the core conductor. In addition, there are a step of depositing an insulating adhesive layer on the insulating substrate, a step of wiring and fixing the insulating coated wire on the insulating adhesive layer, a step of providing an insulating resin layer in which the insulated wire is multinucleated, and a step of providing the insulating resin layer with the insulating bonded wire. A process of forming a mismatched mask layer made of an insulator without catalytic properties by electroless plating on the surface of the layer, and a step of forming a mismatched mask layer and an insulating resin by irradiating a laser beam from above the mismatched mask layer. The process of providing a hole that penetrates a part of the layer to reach the conductor of the insulated wire is inconsistent with the process of forming a conductor layer by electroless plating on the inner wall surface of the hole and the conductor surface of the insulated wire. A method for manufacturing a wiring board is obtained, which comprises a step of removing a mask layer.

以下、本発明を第3図および第4図を参照して説明する
。第3図は本発明の一実施例を示す断面図である。第3
図(a)は、前述した従来例の第1図(a)ないし第1
図(C)と同様にして製造した中間工程の配線板の状態
を示すものである。配線板の表裏両面に無電解めっきに
対して触媒性を有するプリプレグの所望枚数を重ねた構
成体の上下両面を十分な剛性を有する例えばステンレス
鋼で作った平面板(図示省略)にて挾持し、この平面様
を加熱。
The present invention will be explained below with reference to FIGS. 3 and 4. FIG. 3 is a sectional view showing one embodiment of the present invention. Third
FIG. 1(a) shows the conventional example shown in FIGS.
This figure shows the state of a wiring board manufactured in an intermediate process in the same manner as in Figure (C). The upper and lower surfaces of a structure in which a desired number of prepregs having catalytic properties for electroless plating are stacked on both the front and back surfaces of a wiring board are held between flat plates (not shown) having sufficient rigidity and made of stainless steel, for example. , heat this plane.

加圧して第3図(b)の如く無電解めっきに対して触媒
性を有する絶縁層5を形成する。次に、第3図(C)の
如く絶縁層5に接してマスク層6を例えば熱圧着により
形成する。次に、第3図(d)の如く、絶縁複機ワイヤ
4の導体の所望位置にレーザ光線を照射し、マスク層6
および絶縁層5を貫通し絶縁被覆ワイヤ4の芯線導体に
接する穴部9を設け、絶縁被覆ワイヤ4の芯線導体を露
出させる。この穴あけ加工に使用できるレーザ光線とし
ては、第一の実施例にYAGレーザがある。実施例に用
いたレーザ光線発生装置は、第4図に示すようなレーザ
光線の発生部21と、レーザ光束を被加工物24の近く
まで導くための導入経路22と、レーザ光束を絞り調整
するためのし/ズ23とからなる。連続状態にて発振し
ている例えば出力50WのYAGレーザをQスイッチを
用いて例えば1〜5 kHzの周波数に対し0.1〜1
ミリ秒のパルス幅を有するパルス光を照射し、内径的約
0108閣を有する前述の穴部9を得た。この穴あけ加
工に使用できる第二実施例のレーザとしては炭酸ガスレ
ーザがある。このレーザ光線発生装置の構成は、基本的
には第4図と同様であり、連続状態にて発振している例
えば出力60Wの炭酸ガスレーザから周期0.1〜1秒
、パルス幅0.1〜50秒のパルス光を照射し、内径約
0.13wamを有する前述と同様の穴部9を得た。
Pressure is applied to form an insulating layer 5 having catalytic properties for electroless plating as shown in FIG. 3(b). Next, as shown in FIG. 3C, a mask layer 6 is formed in contact with the insulating layer 5 by, for example, thermocompression bonding. Next, as shown in FIG. 3(d), a laser beam is irradiated onto a desired position of the conductor of the insulated composite wire 4, and the mask layer 6 is
A hole 9 is provided that penetrates the insulating layer 5 and contacts the core conductor of the insulated wire 4, so that the core conductor of the insulated wire 4 is exposed. As a laser beam that can be used for this drilling process, a YAG laser is used in the first embodiment. The laser beam generator used in the example includes a laser beam generator 21 as shown in FIG. 4, an introduction path 22 for guiding the laser beam close to the workpiece 24, and an aperture adjustment for the laser beam. It consists of 23 items. For example, a YAG laser with an output of 50 W, which is oscillating continuously, is oscillated by using a Q switch for a frequency of 1 to 5 kHz, for example, by 0.1 to 1.
Pulsed light having a pulse width of milliseconds was irradiated to obtain the aforementioned hole 9 having an inner diameter of approximately 0108 mm. A carbon dioxide gas laser is available as a laser of the second embodiment that can be used for this drilling process. The configuration of this laser beam generator is basically the same as that shown in FIG. 4, and starts with a carbon dioxide gas laser with a continuous oscillation of, for example, an output of 60 W, with a period of 0.1 to 1 second and a pulse width of 0.1 to 1. Pulse light was irradiated for 50 seconds to obtain the same hole 9 as described above having an inner diameter of about 0.13 wam.

次に、例えば30〜90kg/fflの圧力を有する高
圧水流にて穴部9内を清掃して不要の異物を除去する。
Next, the inside of the hole 9 is cleaned with a high-pressure water stream having a pressure of, for example, 30 to 90 kg/ffl to remove unnecessary foreign matter.

さらに、絶縁被覆ワイヤ4の被覆層がポリイミド系樹脂
を用いている場合には、水11に対し水酸化アルカリ例
えば水酸化ナトリウムを10〜50を含有する温[40
〜70℃、好ましくは温度50〜60℃に保持された溶
液中に全面を浸漬揺動させて穴部9の壁面を清浄にする
と同時に絶縁複機ワイヤ4の穴部9内に露出している被
覆材の残漬をすべて除去し、芯線導体を完全に露呈させ
る。次に配線板の全面を無電解めっき液に浸漬揺動させ
て穴部の壁面と露出された接着層30表面および絶縁被
榎を除去した芯線導体の表面にめっき被膜10が形成さ
れる。穴部9が絶縁被接ワイヤ4の交差部に設けられた
場合には、交差部においてそれぞれの芯線導体がめつき
被膜10を介して電気的に接続される。次いで、第3図
(e)の如く、不要となったマスク層6を例えば機械的
に引き剥し除去する。
Furthermore, when the coating layer of the insulating coated wire 4 is made of polyimide resin, a hydroxide alkali such as sodium hydroxide is added to the water 11 at a temperature [40
The entire surface is immersed and shaken in a solution maintained at a temperature of ~70°C, preferably 50~60°C to clean the wall surface of the hole 9 and at the same time expose the inside of the hole 9 of the insulated composite wire 4. Remove all remaining coating material to completely expose the core conductor. Next, the entire surface of the wiring board is immersed and shaken in an electroless plating solution to form a plating film 10 on the wall surface of the hole, the exposed surface of the adhesive layer 30, and the surface of the core wire conductor from which the insulation coating has been removed. When the hole 9 is provided at the intersection of the insulated wires 4, the respective core wire conductors are electrically connected through the plating film 10 at the intersection. Next, as shown in FIG. 3(e), the unnecessary mask layer 6 is removed, for example, by mechanically peeling it off.

以上、本発明により配線板に貫通孔を穿設することなく
配線板の表裏面に別々の触覚した電気的接続穴部を設け
るととKより配線密度を大幅に向上することができる。
As described above, according to the present invention, the wiring density can be significantly improved by providing separate tactile electrical connection holes on the front and back surfaces of the wiring board without drilling through holes in the wiring board.

さらに、電気的接続の穴部が貫通孔ではないため、配線
板の板厚とけ無関係に加工できるという利点がある。な
お、本発明は芯材に金属材料を使用する配線板について
も応用できることは勿論である。
Furthermore, since the electrical connection hole is not a through hole, there is an advantage that it can be processed regardless of the thickness of the wiring board. It goes without saying that the present invention can also be applied to wiring boards that use metal materials for the core material.

【図面の簡単な説明】[Brief explanation of drawings]

wJ1図は従来の配線板の製造工程を示す断面図、第2
図は従来の配線板の断面斜視図、第3図は本発明の実施
例による配線板の製造工程を示す断面図、第4図は本発
明の製造工程中に使用するレーザ穴あけ装置の訪明図。 図中の符号、1・・・・・・絶縁基板、2・・・・・・
銅箔層、3・・・・・・接着層、4・・・・・・絶縁被
横ワイヤ、5・・・・・・絶縁層、6・・・・・・マス
ク層、7・・・・・・貫通孔、8・・・・・・金属導体
層、9・・・・・・穴部、10・・・・・・めっき被膜
、 21・・・・・・レータ呪生部、22・・・・・・
レーザ導入経路、23・・・・・・レンズ、24・・・
・・・被加工物。 5 第 1 図 第2図 第3図 第4図
Figure wJ1 is a cross-sectional view showing the manufacturing process of a conventional wiring board.
The figure is a cross-sectional perspective view of a conventional wiring board, Figure 3 is a cross-sectional view showing the manufacturing process of a wiring board according to an embodiment of the present invention, and Figure 4 is a visit to the laser drilling device used in the manufacturing process of the present invention. figure. Codes in the diagram: 1...Insulating substrate, 2...
Copper foil layer, 3...Adhesive layer, 4...Insulated horizontal wire, 5...Insulating layer, 6...Mask layer, 7... ... Through hole, 8 ... Metal conductor layer, 9 ... Hole portion, 10 ... Plating film, 21 ... Rator cursed part, 22・・・・・・
Laser introduction path, 23... Lens, 24...
...Workpiece. 5 Figure 1 Figure 2 Figure 3 Figure 4

Claims (4)

【特許請求の範囲】[Claims] (1)絶縁基板上に絶縁被覆ワイヤの所望回路パターン
を布線してなる配線板において、少なく七も絶縁被覆ワ
イヤの芯線導体の表面まで到達する穴部を;、前記穴部
の内壁面および前記芯縁導体の表面に導電体層を設けた
ことを特徴とする配線板。
(1) In a wiring board formed by wiring a desired circuit pattern of insulated wire on an insulated substrate, a hole that reaches at least the surface of the core conductor of the insulated wire; A wiring board characterized in that a conductor layer is provided on the surface of the core edge conductor.
(2)絶縁基板上に絶縁性接着層を被着する工程と、前
記絶縁性接着層上に絶縁被接ワイヤを布線する工程と、
前記絶縁被覆ワイヤの露出表面を被覆するように絶縁樹
脂層を設ける工程と、前記絶縁樹脂層表面に無電解めっ
きに対して触媒性を有しない非整合マスク層を形成する
工程と、レーザ光線を照射して絶縁被覆ワイヤの導体表
面を部分的に露出させる穴部を設ける工程と、前記穴部
の内壁面および前記導体の表面に導電体層を形成する工
程と、前記非整合iスク層を除去する工程とからなる配
線板の製造方法。
(2) a step of depositing an insulating adhesive layer on an insulating substrate; a step of wiring an insulated bonded wire on the insulating adhesive layer;
a step of providing an insulating resin layer to cover the exposed surface of the insulating coated wire; a step of forming a non-conforming mask layer having no catalytic properties for electroless plating on the surface of the insulating resin layer; and a step of applying a laser beam. a step of providing a hole to partially expose the conductor surface of the insulated wire by irradiation; a step of forming a conductor layer on the inner wall surface of the hole and a surface of the conductor; A method for manufacturing a wiring board, comprising a step of removing the wiring board.
(3)前記レーザ光想にYAGレーザを用いることを特
徴とする特許請求の範囲第2項記載の配線板の製造方法
(3) The method for manufacturing a wiring board according to claim 2, characterized in that a YAG laser is used for the laser light source.
(4)前記レーザ光線に炭酸ガスレーザを用いることを
特徴とする特許請求の範囲第2項記載の配線板の製造方
法。
(4) The method for manufacturing a wiring board according to claim 2, wherein a carbon dioxide laser is used as the laser beam.
JP15666981A 1981-10-01 1981-10-01 Circuit board and method of producing same Pending JPS5857782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15666981A JPS5857782A (en) 1981-10-01 1981-10-01 Circuit board and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15666981A JPS5857782A (en) 1981-10-01 1981-10-01 Circuit board and method of producing same

Publications (1)

Publication Number Publication Date
JPS5857782A true JPS5857782A (en) 1983-04-06

Family

ID=15632710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15666981A Pending JPS5857782A (en) 1981-10-01 1981-10-01 Circuit board and method of producing same

Country Status (1)

Country Link
JP (1) JPS5857782A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979594A (en) * 1981-04-14 1984-05-08 コルモ−ゲン・テクノロジイズ・コ−ポレイシヨン Board for connecting electronic element and method of producing same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494232A (en) * 1972-04-28 1974-01-16
JPS4945359A (en) * 1972-09-08 1974-04-30
JPS5315050B2 (en) * 1973-06-27 1978-05-22

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494232A (en) * 1972-04-28 1974-01-16
JPS4945359A (en) * 1972-09-08 1974-04-30
JPS5315050B2 (en) * 1973-06-27 1978-05-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979594A (en) * 1981-04-14 1984-05-08 コルモ−ゲン・テクノロジイズ・コ−ポレイシヨン Board for connecting electronic element and method of producing same

Similar Documents

Publication Publication Date Title
US4931134A (en) Method of using laser routing to form a rigid/flex circuit board
JP3633252B2 (en) Printed wiring board and manufacturing method thereof
US5404637A (en) Method of manufacturing multilayer printed wiring board
US4965702A (en) Chip carrier package and method of manufacture
JP2000101245A (en) Multilayer resin wiring board and its manufacture
TWI223972B (en) Double-sided printed circuit board without via holes and method of fabricating the same
JPH0590756A (en) Production of rigid/flexible board
JP3492467B2 (en) Single-sided circuit board for multilayer printed wiring board, multilayer printed wiring board and method of manufacturing the same
US20030160035A1 (en) Method of forming an opening or cavity in a substrate for receicing an electronic component
US20050155957A1 (en) Method of forming an opening or cavity in a substrate for receiving an electronic component
WO1999026458A1 (en) Multilayer printed wiring board and method for manufacturing the same
JPS5857782A (en) Circuit board and method of producing same
JP3062142B2 (en) Method for manufacturing multilayer printed wiring board
JP2003198133A (en) Method for manufacturing flexible build-up printed wiring board
JP4244414B2 (en) Manufacturing method of multilayer printed wiring board
JP2000031649A (en) Manufacture of multilayer printed circuit board
JP3296274B2 (en) Multilayer electronic component mounting substrate and method of manufacturing the same
JP2003526205A (en) Method of making an opening or cavity in a substrate for receiving an electronic component
JPH0312792B2 (en)
JPS5810893A (en) Circuit board and method of producing same
JPH10117058A (en) Method for working printed board
JP2007208298A (en) Printed wiring board
JP3979086B2 (en) Semiconductor circuit inspection jig
JPH05277774A (en) Method for partially removing insulator layer of insulating substrate with conductor layer
JP2001284809A (en) Multilayer circuit board and its manufacturing method