JPS5856066A - Digital arithmetic device - Google Patents

Abstract

PURPOSE:To transfer data among a plurality of data processors and to speed up data processing by providing a switch which switches a flow of digital data at every connection points of a data bus from a data processor and a looped data bus. CONSTITUTION:Looped data buses 19-22 are provided with four switches 23- 26, and processors each consisting of an arithmetic logical unit 15, a register 17, a shifter 18, a selector 28, etc., are connected to the buses 19-22. When the signal line of this arithmetic device has logic 1, the switches 23 and 25 are opened to transfer the arithmetic result of an arithmetic circuit 14 to an RAM13 or the circuit 14 through the shifter 18, switch 26, selector 28, etc., and the arithmetic result of the unit 15 to the register 17 through the switch 24. When it has logic (0), the switches 24 and 26 are opened to transfer the arithmetic result of the unit 15 to the RAM13 or circuit 14 through the switch 23 and selector 28, and the arithmetic result of the circuit 14 to the register 17 through the shifter 18 and switch 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital arithmetic device having a loop-shaped data bus, and particularly to a digital arithmetic device suitable for continuously executing two or more types of arithmetic operations at high speed.

Conventionally, in a digital arithmetic device having multiple digital data processing devices (hereinafter referred to as processing devices),
As shown in FIG. 1, a plurality of processing devices are connected to one data bus, and a control signal selects one processing device to output data and one processing device to input data. Data was transferred via a data bus.

In this method, data transfer between unselected processing devices could not proceed until the data transfer currently being performed was completed. If data transfer was to be performed between two or more sets of processing devices, it was necessary to prepare the same number of data buses.

An object of the present invention is to provide a digital arithmetic device that enables data transfer between a plurality of sets of processing devices using a plurality of switches on a data bus having a loop structure.

The present invention focuses on the point that by opening two or more switches on a data bus having a loop structure, it is possible to obtain the same number of independent data buses as the opened switches.
By using one loop-shaped data bus, it is possible to simultaneously perform data transfer between multiple sets of processing units, and by selecting the switch to be opened, combinations of processing units that perform data transfer can be made. The reason for this is that we have made it possible to have a degree of freedom.

FIG. 2 shows a schematic diagram of a digital arithmetic unit having a loop-shaped data bus, using eight switches as an example. As shown in Figure 2, the switch 3
A single processing device 1 is connected to the small section data bus 2 that connects the switch 3 and the switch 3 . Small section data bus 2
has a loop structure as a whole. By turning the switch 3 on and off, data can be transferred between processing devices in various combinations. In the example in Figure 2, a maximum of 4
Simultaneous data transfer is possible between a set of processing devices.

FIG. 3 shows an example using four switches. The operation of the switch and the flow of data will be described below using the example shown in FIG.

First, an embodiment of the switches 9 to 12 shown in FIG. 3 is shown in FIG. 4. One common signal line is distributed to so-called gates of transfer gates provided on each of the plurality of data lines, and all of them operate in the same way. Assuming that the transfer gate is made of NMO8, when a high level (1) voltage is applied to the signal line, the transfer gate is turned on and the left and right data lines are brought into conduction.

In FIG. 4, since the left and right sides are symmetrical, there is no need to consider the direction in which data flows. On the other hand, when the voltage applied to the signal line is at a low level (0), the transfer gates are turned off and the data lines are electrically disconnected on the left and right sides.

Among the switches 9 to 12 shown in FIG. 3, the switch 1o.

11, the signal line is directly tangentially connected, but the signal line is inverted and connected to the switches 9 and 12 by an inverter 8. That is, when the signal line is ``1'',
Switches 10 and 11 are in the on state.

Switches 9 and 12 Ifi are in the off state. On the other hand, when the signal line is 10'', the slope is opposite to this. - The signal line in FIG. The data bus between switches 9 and 10 is connected to the data bus input to A L tJ 5, and when it is 1'', the data bus input to data line CFiA L U 5 is connected to the data bus input to A L tJ 5. data between switches 9 and 10 on the bus.
The bus is tangential to the data bus that is input to ALU4.

That is, in FIG. 3, when the signal line is '0', the data given to data MB and C is operated on by ALU4, and the result and the data on the data line input are operated on and calculated in ALU5. The result is output to data #D through register 7. On the other hand, when the signal line is “1”, data M
The data on A and C are operated on by the ALU5, and the results and the data on the data line B are operated on in the ALU4. This result is output as data #D through the register 7 as well.

An embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 5, data buses 19-22 include four
Two switches 23 to 26 are provided. The processing devices connected to the loop data bus are an arithmetic logical unit (hereinafter abbreviated as ALU) 15, a register 17, a chic 18, and a selector 28. In the embodiment shown in FIG. 5, there are two basic operations. Part 1
First, when the signal line is "1", the switches 23 and 25 are opened and the calculation result of the 1 multiplier circuit 14 is transferred to the shifter 18 and the switch 2.
6. A two-vote random access tomori (hereinafter abbreviated as FtAM) 13 is also configured via the selector 28 and selectors 29 and 30.

This is an operation in which transfer to the multiplication circuit 14 and transfer of the calculation result of the ALU 15 to the register 17 through the opening/closing 24 are performed simultaneously. The other one is that the signal line is o
”, the switches 24 and 26 are opened, and the calculation results of the ALU 15 are transferred to the switches 23, selector 28, and selector 29.
30, the RAMI 3 is also transferred to the multiplication circuit 14, and the calculation result of the multiplication circuit 14 is transferred to the shifter 18.
．． This is an operation in which data is transferred to the register 17 via the switch 25 at the same time.

FIG. 6 shows the arithmetic unit shown in FIG. 5 as one processor element (hereinafter abbreviated as PE) 33 to 36.
This is an arithmetic unit in which two ALUs 37 are connected in series and one ALU 37 is added.

Using the arithmetic device shown in FIG. 6, the operation of the arithmetic device shown in FIG. 5 will be explained by taking image processing as an example.

Now, assume that we are dealing with information on red, green, and 8 pixels per pixel (256 levels), and calculate the distance of each pixel from the standard color using the following formula.

L(i)=[(R-Ri)2+(G-Gi)2+(B
-B i12] However, L(i): standard color intertwining distance Ri, Qi, Bi: class i red, green,
Blue levels R, G, B: Red, green, and blue levels of the operand picture elements Prior to executing the above operation, the red, green, and blue levels of the standard colors of class i are 1%i, Qi, Bi is Ri
is in PE36, Gi is i in PE35 B' is PE
34 and is written to the RAM 13. Next, the red, green, and blue levels Tt, G, and B of the operand picture elements are also set to PE3, respectively.
6.35.34 is written to RAM13.

Rr written in RAM13 in PE36.

R is simultaneously transferred to the ALU 15 via selectors 31 and 32, and (R, 1-4) is calculated.

+R, -R, i) as the calculation results are connected to the loop data bus, switch 23. It is transferred to the multiplication circuit 14 via the selectors 28, 29 and 30, and (Ri-R)'' is calculated. 8 bits of the operation result (Ri-R)2 are selected by the shifter 18, and the loop data Bus, switch 25
The data is transferred to the register 17 via.

Similarly, for PE35 and 34, (G-Gi)2
°(B-Bi)2 is calculated. Then, L(i) is calculated in the ALU 38.

In the above calculation, once R, G, and B are written into the RAM 13, the data does not pass through the same processing device twice. Therefore, there are many standard colors? By keeping the signal line on when there is a
Pipeline processing is enabled by opening the switches 24, 26.

In this case, the calculation results for each class are compared in the ALU 3B, and the class with the minimum value is output as the final result.

As another example, consider a case in which a 4×4 spatial filter using a grayscale image as input data is executed using the arithmetic device shown in FIG. As shown in FIG. 7, the image data is cut out into a 4×4 window, and a sum-of-products calculation is performed with a sum-of-products weighting coefficient. In this case, the product-sum loading coefficient of MB is PE
+ M2j + M3J + M in RAM13 in 37
The product-sum load coefficients of 4J are written in advance in R and AM13 in PE36.35.34, respectively. The image data is DIIDI2D13D14D2ID22°”
"' D 43 D 44 is input to PE34. The data input to PE34 is sequentially written to the RAM 13, but when picture element data D2t is input to PE34, picture element data DIl is transferred from PE34 to PE35. In other words, the RAM 13 in each PEO stores only the latest four picture element data among the image data input to that PE, and the picture element data input before that is stored in the RAM 13 of each PEO. In this way, immediately before the picture element data D41 is input to the PE 34, the picture element data D u -D 14 is transferred to the RAM 13 in the PE 36.
The picture element data D21 to D24 and D3 to D34 are respectively stored in the RAM 13 of the PE35.36.

Now, consider executing the calculation of the 4×4 spatial filter shown in FIG. To keep things simple, let's focus only on PE34.

First, the picture element data D41 is stored in the register (fifth register) of the PE34.
At this time, the picture element data I>31 stored in the RAM (13 in FIG. 5) is written to 16) in the figure.
, and is transferred to the next stage via the selector (27 in FIG. 5). Next, the picture element data D41 written in the register 16 is transferred to the 1 multiplication circuit 14 via the selector 28, 30 shown in FIG.
3 is also stored in selector 29.
is transferred to the multiplication circuit 14 via D41 x M4
1 is calculated. Picture element data D41 in register 16
is written into the RAM 13 immediately after being transferred to the multiplication circuit 14. D41 x M4. The value is thick 18. It is transferred to the ALU 15 via the selector 31.

Similarly * D42 X M42 s D43X M2S
+ D44 x M44 is calculated by the multiplication circuit 14,
Transferred to ALUI5.

These values are accumulated in ALUI 5 and the result is.

It is written to the register 17 via the switch 24.

That is, register 17 contains 2041M4j j■! The value of will be stored. Similarly, PE34
dei:[)4. M4. is calculated at the same time.

j 禦l is accumulated in the ALU 38, and the calculation of the spatial filter for one picture element is completed.

In the above calculation as well, by keeping the signal line at 1'', pie return processing is possible.

According to the present invention, by selecting the signal that controls the switch, the configuration of the arithmetic device can be made suitable for each data process, and various data processes can be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a conventional configuration diagram of an arithmetic unit having a plurality of digital data processing devices. FIG. 2 is a conceptual diagram of a plurality of arithmetic units having a loop-shaped data bus. FIG. 3 is a basic configuration diagram of an arithmetic unit having four digital data processing units and a loop-shaped data bus. FIG. 4 is an embodiment of the switch in FIG. 3. FIG. 5 is a configuration diagram of an embodiment of the present invention. FIG. 6 is a configuration diagram of an arithmetic device using the arithmetic device of FIG. 5. FIG. 7 is a diagram showing calculation of a 4×4 spatial filter in image processing. DESCRIPTION OF SYMBOLS 1... Digital data processing device, 2... Data bus, 3... Switch, 4, 5... ALU, 6...
・Selector switch% 7...Resistor, 8...Inverter, 9゜10.11.12...Switch, 13...
2-bot FLAM.

Claims (1)

[Claims] 1. A loop-shaped data bus and the loop-shaped data bus.
Between two or more data processing devices connected to the bus and the loop-shaped data bus, for each connection point between the data bus from the data processing devices and the loop-shaped data bus, A digital computing device characterized by being provided with a switch that opens and closes the flow of digital data.