JPH1166033A - Pe array device and associated memory block - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add the data of all processing elements(PE) consisting of a PE array device at high speed even without providing any special additional hardware outside the PE array device. SOLUTION: This PE device is provided with (w) [(w) is an arbitrary natural number] pieces of PE 24, shift operation enabled hit flag register 25, function shared register 26 operable as pipeline register or counter, and (n) [(n) is a natural number >=2] pieces of associated memory blocks 20 having control circuits 27 and an inter-block dedicated bus 14 is provided for connecting the associated memory blocks 20. The control circuit 27 selects either a means for operating the function shared register 26 or a means for operating the function shared register 26 as the pipeline register for transferring data between the associated memory blocks 20 or as the counter for counting the number of hit flags.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a massively parallel processing element array device (PE array device) for configuring various massively parallel computing devices such as an image processing system.

[0002]

2. Description of the Related Art Visualization of network services,
The need for advanced image processing, sound processing, and knowledge processing is increasing due to the added value. By the way, the above-described processing generally requires enormous processing performance, and therefore, it is often difficult to execute the processing using an existing microprocessor or signal processing processor based on the Neumann architecture.

[0003] A super-parallel PE array device is known as an effective device for the above-described processing. This massively parallel P
The E-array device is a PE that performs various logic and arithmetic operations.
(Processing elements), a single instruction stream / multiple data stream system (SIMD) provides a single instruction sequence to each PE from one control circuit, thereby allowing each PE to perform the above-described arithmetic processing. Is a device having a mechanism capable of executing the same at the same time.

[0004] An associative memory is also known (reference: Ogura, T. et al. "A 20-kbit Associative Memory LS").
I for Artificial Intelligence Machines ", IEEE J.So
lid-State Circuits, Vol. 24, No. 4, pp. 1014-1020 Aug.
1989). This associative memory is a massively parallel PE as described above.
This is an integrated circuit that can realize an array device with an extremely small amount of hardware.

[0005] Also, a two-dimensional PE array device is known. This two-dimensional PE array device is a device in which hundreds of thousands of PEs are two-dimensionally mounted with the above-mentioned associative memory as a constituent element (Reference: Ikenaga, T. et al. "CAM ² : A High
ly-parallel 2-D Cellular Automata Architecture for
Real-time and Palm-top Pixel-level Image Processi
ng ", Euro-Par '96, Aug. 1996).

FIG. 4 is a diagram showing a conventional PE array device 40.

As shown in FIG. 4, a conventional PE array device 40 has a mask register 46, an address decoder 45,
It comprises a hit flag register 48, W PEs 47, and a control circuit 44. The PE array device 40
Is an address input / output port 41 like a normal memory.
Is provided with a predetermined address (value) so that data can be read from or written to any of the W PEs 47 via the data input / output port 42.

Further, the above-mentioned conventional PE array device 40
Search data provided from the data input / output port 42 and P
The content of E is checked in parallel, a mask search function for setting a hit flag for the matched PE, and the data supplied from the data input / output port 42 are written in parallel to the PE on which the hit flag is set. It has a parallel partial write function.

By using both of these functions, various data transfer, logic, and arithmetic operations can be performed in word parallel (wo
rd parallel), bit serial. Further, after performing a mask search (a process of setting a hit flag for a matched PE as a result of collating the search data and the contents of the PEs in parallel), shifting the hit flag register to perform parallel partial writing. Thus, data transfer can be performed between neighboring PEs (between words).

[0010]

However, in the above conventional example, when only the parallel processing function in each of the PEs or the data transfer function between neighboring PEs is used, the data of all the PEs constituting the PE array device 40 are used. Cannot be added, that is, global processing cannot be realized. For example, black-and-white image data is stored in the PE array device 40, and the total number of pixels (black pixels) in which each data of a predetermined PE is 1 is obtained for all the black-and-white image data stored in the PE array device 40. Can not do.

In the above conventional example, the PE array device 40
In order to add up the data of all the PEs constituting the data processing system, an additional circuit such as a processor or an adder is provided in advance outside the PE array device 40, and the data for each PE is provided via one data input / output port 42. Must be read out to the outside, added using the above processor or adder, and the reading and adding operations must be repeated.

Therefore, in the above conventional example, there is a problem that the amount of hardware is increased by providing the additional circuit, a problem that the system is complicated, and a problem that the processing time is lengthened. There is.

Among various massively parallel algorithms such as image processing, there are many which always execute a process of adding data of all PEs. For example, in the area calculation in the pattern spectrum calculation using morphology (reference: Obata, Morphology, Chapter 7, Corona), a process of adding the data of all PEs is always executed.

In recent years, image processing applications requiring real-time processing have increased, and to apply to these applications, the processing time of the entire algorithm needs to be within the video rate (33 milliseconds). For this reason, it is desired that the processing of adding the data of all the PEs can be realized in an extremely short time.

Furthermore, in recent years, there has been a strong demand for a compact and low-cost image processing system, and to realize this, a device with a simple configuration in which the amount of hardware of the system is as small as possible is desired. .

An object of the present invention is to provide a PE array device which can add data of all PEs constituting the PE array device at high speed without providing any special additional hardware outside the PE array device. It is intended for.

[0017]

According to the present invention, there are provided w (where w is an arbitrary natural number) PEs, a hit flag register capable of performing a shift operation, a function sharing type register capable of operating as a pipeline register or a counter, A PE array device provided with n (n is a natural number of 2 or more) associative memory blocks having a control circuit, and a dedicated bus between blocks for connecting the associative memory blocks; One of a means for operating the shared function register as a pipeline register for data transfer between memory blocks, and a means for operating the shared function register as a counter for counting the number of hit flags This is a PE array device which is a circuit for selecting a means.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a basic configuration of a PE array device 10 according to one embodiment of the present invention.

As shown in FIG. 1A, the PE array device 10 includes n (n is a natural number of 2 or more) associative memories (C
AM) blocks 20 ₍₁₎ , 20 ₍₂₎ ,..., 20 _(n) , and each associative memory block 20 ₍₁₎ , 20 ₍₂₎ ,.
.., 20 _(n) are connected by a dedicated bus 14 between blocks.

The associative memory block 20 ₍₁₎ is shown in FIG.
As shown in (2), w (w is an arbitrary natural number) PEs
(Word) 24 ₍₁₎ , 24 ₍₂₎ ,..., 24 _(n) , and this PE can be used as a single instruction stream / multiple data stream (SIMD) PE. The associative memory block 20 ₍₂₎ ,.
0 _(n) are associated with the associative memory block 20.
This is the same as the above configuration of ₍₁₎ . Therefore, the entire PE array device 10 has n × w PEs (processing elements).

The associative memory block 20 ₍₁₎ is shown in FIG.
As shown in (2), the address decoder 22, the mask register 23, and the PEs 24 _{( 1)} , 24 ₍₂₎ ,.
_(n) , a hit flag register 25, a function sharing type register 26, a control unit 27, a control line 28, and a path switching circuit 29.

As described above, associative memory block 20
_{The configuration of (2)} ,..., 20 _(n) is associative memory block 2
Since the configuration is the same as that of 0 ₍₁₎ , the following description will be made as an associative memory block 20 as a representative. Also,
PE24 ₍₁₎ , 24 ₍₂₎ ,..., P on behalf of 24 _(n)
This will be described as E24.

The associative memory block 20 stores the search data supplied from the data input / output port 11, the PE 24 ₍₁₎ ,
4 ₍₂₎ ,..., And 24 _(n) are matched in parallel, and a mask search function is set to set a hit flag for the PEs that match. Also, the associative memory block 2
0 also has a parallel partial write function of writing data given from the data input / output port 11 in parallel to the PE on which the hit flag is set. Both features,
The bits to be processed can be limited by the mask register 23. By using these functions,
Various data transfer, including addition, logic, and arithmetic operations are performed in word parallel and bit serial
l) Can be performed.

The associative memory block 20 counts the number of hit flags by operating the shared function register 26 as a counter and sequentially shifting the contents of the hit flag register 25 via the hit flag control line 21. It has a function to perform. The count function of the hit flag register 25 can be operated independently in each associative memory block 20.

The associative memory block 20 switches the path from the PE 24 to the shared function register 26 by the path switching circuit 29, and the shared function register 26
As a pipeline register. By using this function, P between adjacent associative memory blocks 20 via the inter-block dedicated bus 14
E data can be transferred.

Since the shared function type register 26 is a counter and shares a register portion, a pipeline register and a counter can be realized with a small amount of hardware. The function sharing type register 26 switches between a pipeline register and a counter by a control line and shares an F / F. When the amount of hardware is reduced, the following function description is realized.

That is, output = register; if control line = 0 register <= input; else if control line = 1 register <= register + hit flag data; (that is, the control line is 1 and the hit flag data ( Only when 0 or 1) is 1, the count is incremented).

The control signal output from the control circuit 27 and passed through the control line 28 allows the hit flag register 25 to perform a counting function and an inter-block data transferring function.
One function is controlled.

The PE array device 10 does not operate alone because it is not a processor. The control circuit 27 in the associative memory block 20 is a simple instruction decoder.
A sequencer (not shown) for giving the instruction sequence shown in FIG. 2 to the instruction input port 13 of the PE array device 10
It must be provided outside.

Next, all PEs in the PE array device 10
The (word) addition processing procedure will be described.

FIG. 2 is a flowchart showing a processing procedure for adding the contents of all the PEs constituting one associative memory 20 in the above embodiment.

All Ps constituting one associative memory 20
The addition process of E (word) is performed by adding in a block (S10).
And inter-block addition (S20).

First, in the intra-block addition processing (S10), a search mask is set (S11), whereby
The bits other than the bit position (1 bit) where the data to be added are stored in the PE bits are masked. Then, a mask search is performed (S12), and the data to be added stored in each PE is transferred to the hit flag register 25.

Next, the number of hit flags is counted by operating the function sharing type register 26 as a counter and shifting the hit flag register 25 (S
13). PE provided in the associative memory block 20
The above counting process is repeated the same number W times as the number W (S14). In each associative memory block 20, the above-described count processing is simultaneously executed. Finally, the addition result stored in the function sharing type register 26 is stored in a predetermined PE.
24 (S15). By the above series of processing,
An addition result of PE can be obtained for each associative memory block 20.

In the inter-block addition process (S20),
Inter-block transfer is performed (S21), bit-serial addition is performed (S22), and inter-block transfer (S21) and bit-serial addition (S22) are repeated, that is, repeated until the addition result is aggregated in one PE ( S23),
The result of addition for each of the associative memory blocks is added while being aggregated in a tree shape. Finally, the addition results aggregated in one PE are read out of the PE to read the PE array device 1
0 (S24).

Next, the inter-block addition processing (S20) will be described in detail.

FIG. 3 is a diagram showing an example of the inter-block addition processing (S20) when n = 4 in the above embodiment.

By the inter-block addition processing (S20),
Of the intra-block addition results A, B, C, and D stored in a predetermined PE (word) of each associative memory block 20, the addition results A and C are transferred to the right side of the associative memory block 20 by inter-block transfer. Are transferred to each of the PEs (words) storing the addition results B and D among the PEs included in.

In this case, the function sharing type register 26 is used as a pipeline register, and the dedicated bus 14 between blocks is used.
, The addition results A and C are transferred. Next, by repeating mask search and parallel partial writing, A + B (=
E), and addition of C + D (= F) is executed bit-serial. Note that the transfer processing and the addition processing may be performed simultaneously.

In the same manner as described above, the inter-block transfer of the addition result E is performed twice to transfer the addition result F to the PE in which the addition result F is stored, and the mask search and the parallel partial writing are repeated as described above. , The addition result E + F (=
G) is calculated bit-serial. This addition result G is
The result is the sum of all PEs that make up one associative memory 20.

Finally, PE read (word read)
Then, the addition result G is taken out of the PE array device 10. Even when the number n of the associative memories 20 increases, the inter-block addition processing (S20) can be executed by the same procedure as described above.

Incidentally, in the conventional PE array device 40, when performing the above-described addition processing of all PEs (words), a processor or the like is provided outside the PE array device 40, and there is only one system of data input / output. It is necessary to read out for each PE via the port 42 and repeatedly execute addition using the external processor or the like. Therefore, the same number of processing cycles as the total number of PEs are required, the processing time is long, and a special circuit for performing the addition is required.
It must be provided outside the PE array device 40.

However, in the above embodiment, all PE
The intra-block addition processing (S10) can be executed in (word) number / n cycles, and the inter-block addition processing (S20) is executed in a cycle in which block transfer and addition are repeated log ₂ n times. be able to. Therefore, when the number n of the associative memory 20 is increased, the addition processing can be completed in a processing time of about 1 / n of the processing time required in the conventional example.

That is, the associative memory block 2 shown in FIG.
In the example where the number of 0s is n = 4, if the inter-block transfer and the bit serial addition are repeated twice, the number of addition results for each block becomes 4 → 2 → 1. Similarly, n =
In the case of 8, if the inter-block transfer and the bit serial addition are repeated three times, the number of addition results per block becomes 8 →
4 → 2 → 1, and when n = 16, the inter-block transfer and the bit serial addition are repeated four times, so that the number of addition results per block is 16 → 8 → 4 → 2 →
Becomes 1. That is, the number of repetitions of the inter-block transfer and the bit serial addition is log ₂ n. That is, the inter-block addition processing can be performed in a logarithmic-order processing time for n, and when n is increased, the inter-block addition processing time becomes a negligible value.

In the above embodiment, the addition processing is performed on the data of all the PEs constituting the content addressable memory 20 using only the functions of the PE array device 10 without providing any external device in the PE array device 10. be able to.

In the above embodiment, the pipeline register (function-shared register 26) for transferring data between the associative memory blocks 20 is provided with a counter function, and the shift output of the hit flag register 25 is input. , The number of hit flags can be counted. Thus, for each associative memory block 20, an addition result of all the PEs constituting the associative memory block 20 can be obtained. The addition result for each of the associative memory blocks 20 is obtained by repeating the addition process while aggregating the data in a tree shape using inter-block transfer, so that one of the specific associative memory blocks 20 is finally obtained. In a word, the addition data of all PEs can be collected. By reading this addition data, the addition processing of the data of all the PEs constituting the PE array apparatus 10 can be performed without providing any special additional hardware externally.
0 can be executed.

Of the above processes, the hit flag counting process can be performed in parallel in all the associative memory blocks 20, and the addition between the associative memory blocks 20 is performed in a tree-like manner, thereby shortening the time. Can be processed. Therefore, as in the conventional case, each PE (word) is set to 1
Compared to the case of adding while reading one by one,
The addition processing of the data of all PEs can be executed in a short time.

[0048]

According to the present invention, it is possible to add the data of all the PEs constituting the PE array device without providing any special additional hardware outside the PE array device, and to perform the addition process. Is fast.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a PE array device 10 according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure for adding contents of all PEs constituting one associative memory 20 in the embodiment.

FIG. 3 is a diagram illustrating an example of an inter-block addition process (S20) when n = 4 in the embodiment.

FIG. 4 is a diagram showing a conventional PE array device 40.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... PE array apparatus, 14 ... Bus between blocks, 20 ... Associative memory block, 22 ... Address decoder, 23 ... Mask register, 24 ... PE (word), 25 ... Hit flag register, 26 ... Function sharing type register, 27 ... Control unit, 29 ... Path switching circuit.

Claims (4)

[Claims] 1. A semiconductor device comprising: w (where w is an arbitrary natural number) PEs; a shift flag-operable hit flag register; a function-shared register operable as a pipeline register or a counter; n is a natural number of 2 or more); an inter-block dedicated bus for connecting the associative memory blocks; and the control circuit serves as a pipeline register for data transfer between the associative memory blocks. A circuit for selecting one of the means for operating the shared function register and the means for operating the shared function register as a counter for counting the number of hit flags. PE array device. 2. w (where w is an arbitrary natural number) PEs; a hit flag register capable of a shift operation; a shared function register operable as a pipeline register or a counter; and a data transfer between associative memory blocks. A control circuit for selecting one of the means for operating the shared function register as a pipeline register and the means for operating the shared function register as a counter for counting the number of hit flags; and An associative memory block comprising: 3. A search mask setting step of masking a bit other than a bit position where data to be added is stored among the bits of the PE; and storing the data to be added stored in each PE in a hit flag register. A mask search step for transferring; a hit flag number counting step for counting the number of hit flags by operating the function sharing type register as a counter and shifting the hit flag register; and a P provided in the associative memory block.
A count repetition step of repeating the count step by the same number as the number of E, and simultaneously executing the count processing in each associative memory block; and adding the addition result stored in the shared function register to a predetermined PE. An addition result writing step for writing data to a block; a block transfer step for transferring data between blocks via a shared function register functioning as a pipeline register; and a bit serial executed by repeating mask search and parallel partial writing. By repeating the addition step,
An aggregation addition step of adding the addition results to the one PE while collecting them in a tree form; and an addition result extracting step of extracting the addition results aggregated in the one PE to the outside of the PE array device. An operation method using a PE array device. 4. A semiconductor memory device comprising w (where w is an arbitrary natural number) PEs, a hit flag register capable of performing a shift operation, a function-shared register operable as a pipeline register or a counter, and a control circuit (n is 2). A natural number) associative memory block, and an inter-block dedicated bus for connecting the associative memory blocks.
As a pipeline register for data transfer between the associative memory blocks, means for operating the function-shared register, and a counter for counting the number of hit flags,
A PE array device which is a circuit for selecting one of the means for operating the function-sharing type register; and controlling addition processing in the associative memory block and addition processing between the associative memory blocks. And a sequencer, wherein the PE array device and the sequencer are connected by an instruction input port.