JPS5854769A - Channel reset system - Google Patents

Abstract

PURPOSE:To reset a channel in a short time, by switching the clear/write control between inactive memory and a channel hold memory in response to the failure mode, in restart processing after the generation of a failure of a time division channel set. CONSTITUTION:A forward channel memory SPMF, a backward channel memory SPMB, an inactive memory IM controlling a busy idle of a channel performing the write control of each channel memory at each channel, and a channel storage memory HLM controlling the channel assignment, are provided in a titled system. The clear control for the memory IM, and write of the HLM and all addresses can be done. At the restart after the restoration of a failure, the clear and write control for the memory IM and the HLM are switched depending on a failure mode to reset the channel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a call route resetting method, and more particularly, to a call route resetting method after failure recovery in a time division electronic exchange.

(1) The call path network of a time-division electronic exchange includes a so-called time switch. This time switch has a call path memory and a call path holding memory. is set. In order to control whether a communication channel is busy or idle, a part of the communication path holding memory is designated as an inactive memory. Information indicating whether the communication channel is busy or idle is stored here. Prevents writing of call signals to memory and instructs busy call channels to write, thereby eliminating call signals from idle call channels and preventing inconveniences caused by unnecessary signals flowing to idle call channels. .

If a failure occurs in the time division electronic exchange, all the information in the inact memory indicating busy/idle in the communication path holding memory is cleared, thereby controlling all communication channels as idle, If the call signal does not flow, the call channel is stopped, and the fault is recovered. After the fault is recovered, the call path is completely reset.

Conventionally, the information in the enact memory indicating this busy/idle information was stored together in the communication path holding memory, so in order to stop the communication channel in the event of a failure, the busy/idle information in the enact memory must be cleared (cleared). (becomes idle information), the contents of the communication path holding memory are also all cleared. That is, the information for controlling the setting of the communication channel in the communication path holding memory is also cleared.

After the failure is recovered, the call path that was set before the failure is reset. In this case, the software refers to the entire call state map stored in the main memory and maintains the call path based on this map. Load the necessary information into memory. For this reason, complicated and large amounts of software processing must be performed, and therefore, it takes a long time to reset the communication path after failure recovery.

Conventionally, regardless of the mode of failure, regardless of whether the failure is in a mode that is not directly related to the communication path or is related to the communication path, resetting as described in (3) above must always be performed. Because.

Even if the failure is in a mode that is not related to the communication path and does not require modification of the contents of the communication path holding memory, the processing device performs a large amount of processing as described above to reset the communication path.
There was a drawback that it took a long time to reset the settings.

The object of the present invention is to improve the above-mentioned conventional drawbacks and to complete the re-establishment of the communication path in a short time after recovery from the failure in the case of a failure mode unrelated to the communication path.

Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a connection diagram of one embodiment of the present invention. In the figure, S
Mo, SM1 switch modules, each with a forward path memo IJ SPMF.

a forward time switch including a time slot counter T-CTR and a channel maintenance memory HLMi; a backward channel memory SPMB and the time slot counter T-CTR and a channel maintenance memory HLM-i;
Shared backward time switch and space switch S
-SW and a signal reception distribution device SRD are provided (4), and the signal reception distribution device SRD of each switch module SMo, SMi is connected to a common bus B, and the main processor MPR and the main processor Connected to storage device MM.

Note that MPX is a multiplexer, DMPX is a demultiplexer, and 1M inactive memory. Also, T is a telephone, LC is its subscriber circuit, T is a trunk line, and TRK is a trunk. Although it is normal to install a large number of telephones T and trunk lines, only one of each is illustrated in the figure.

The call signal arriving from telephone T and trunk line I7 is
2-wire and 4-wire conversion is performed in subscriber circuits ■ and C and trunk TRK, encoded (digitized), and sent to multiplexer M.
PX, where it is time-division multiplexed (frame configuration) with other call signals and stored in forward call path memory SP.
Enter MF.

Issei, 'Telephone T and relay episode &! To connect with L,
Assume that time slots 1-a and 1-b are assigned to each of them.

A speech signal from telephone T passes through multiplexer MPX and enters forward speech path memory SPMF at time slot 1-a. Time slot counter T-CT
R is the total count of clocks synchronized with the time slot, and 1
The number of time slots in a frame is configured as a cyclic counter that returns to O when it is fully counted, and outputs the same number as the time slot number input to the forward channel memo IJ SPMF in synchronization with the time slot. The count output of the time slot counter T-CTR is used as an address when writing the speech signal input from the multiplexer MPX to the forward speech path memory SPMF.

Therefore, the call signals from the telephone T and the trunk line in time slots a and b are written to addresses (a) and (b) of the forward call path memory SPMF', respectively.

The channel maintenance memory IJ HLM and the inact memory IM which controls all the busy/idle channels of the channel are circular memories having the same number of addresses as time slots in one frame.

Now, the communication path maintenance memo') HLM stores the address information of the forward communication path in the address [in this case, address (a)] of the address signal (ADD) sent from the signal reception and distribution device SRD at time slot a). □□□), the address 4' sent out in time slot b) is the address with the number (ADD) [in this case, address (b)], and address information (1) k is also sent from the signal reception distribution device〆tsRD. Written using signal (SP) i.

Communication route maintenance memo IJ The information sent from HLM is as follows:
Forward channel memo IJ Used as an address when reading SPMF. Therefore, time slot a
and at time b, forward channel memory S
The PMP is accessed by the path maintenance memo IJ l' (address read from LM) and (1) and reads its contents to the intermediate highway I HW + in time slots) k and l, respectively. That is, the speech signal from telephone T in time slot k and from the trunk line in time slot l is read out to intermediate highway I HW 1.

The signal read out to the intermediate highway IHW 1 is further read out to the intermediate highway IH-
W2 'fl Backward channel memory SPMH
Enter.

The communication path holding memories HT and M are also time slots)
At k, the address information (b) is sent to the address (address k) specified by the address information (ADD) sent from the signal reception distribution device SRD, and the address information (b) is also sent to the address l.
Address information (a) is written in the same manner as described above.

The information read from the channel holding memo IJ HLM is also used as an address when writing to the backward channel memory. Therefore, backward channel memory S PM
At H, a call signal from the telephone T input at time slot k is sent to the address (b) of the trunk TRK, l input at the alternate time slot A.
: J's call signal is written to its address (a).

Therefore, the information (8
) as an address, in time slot a, the call signal from the trunk TRK is read from the address (a), and in time slot b, the call signal from the telephone T is read out from the address (b), and the call signal is read out from the demultiplexer. Input to DMPX.

To summarize the above, the speech signal from telephone T is time-division multiplexed with other speech signals by multiplexer MPX, is carried by time slot a, enters the forward speech path memory S PMF, and is read out at time slot k. , Intermediate Ha Iwaye ■ (Wl.

It enters the backward path memory SPMB via I HW 2 and space switch 5-5w1, is read out in time slot b, and enters the demultiplexer DMPX. Similarly, the call signal from the trunk TRK is time-division multiplexed with other call signals by the multiplexer MPX, and the forward call path memory SPM is
input to F and read out at time slot l;
Intermediate highway II (W+, via IHW2 and space switch 5-5w'e, backward channel memory S
It is input to PMB, further read out at time slot a), and input to demultiplexer DM-px.

The demultiplexer DMP X separates all of the input time-division multiplexed signals and sends the signal of time slot a to the telephone T and the signal of time slot b to the trunk TRK.

In the subscriber circuit LC and trunk TRK, the call signal sent from the demultiplexer DMPX is fully decoded, and further sent to the receiving terminal on the 4-line side of the 2-wire 4-wire converter, and sent to the telephone T and trunk line. do.

As mentioned above, by writing the above data in the communication path maintenance memo IJ HLM, the telephone T and trunk TR
A communication channel with K is set up.

In addition, in the above, the address read out in the time slot of the inact memory IM and in the intermediate highway I HW 1. Information P1'' indicating that the communication channel set by the time slot of I HW 2 is busy is written by the signal (B/I) from the signal reception and distribution device SRD.

Therefore, "1" is read from the inact memory IM at the time slot /, and this information is given to the backward path memory S PMI3, and the corresponding time slot (i.e., l (and l ), it instructs writing of a call signal into the backward call route memo IJ SPMB.Therefore, as described above, a call channel between the telephone T and the trunk TRK is set.

However, the intermediate high level of the inact memory IM is 1. I HW 2 An address read in an idle time slot that is not used for a call contains information indicating that it is idle.
'0''' is the signal CB/I from the signal reception distribution device SRD
) is written by. Therefore, in an idle time slot, It OI is sent from the inact memory IM.
I is read and this information KOII is given to the backward channel memo IJ SPMH, which becomes a write block indication, in which the writing of the signal carried by that timeslot is blocked in the backward channel. Note IJ SPMB does not carry out any signal transmission (11), and therefore no one-talk channel is set up using idle time slots. In this way, writing control is performed based on the contents of the inact memory IM.

A communication channel between two lines housed in the same switch module, for example SMo, is set as described above. Note that the intermediate highway IHWt output from the forward communication path memory SPMP is branched and input to the space switch 5-SW of another switch module, so that the communication channel between lines accommodated in different switch modules is can be set.

Suppose that a fault occurs in the switching equipment. If the fault is in a mode directly related to the communication path, the main processor MPR sends a control signal to the signal reception and distribution device SRD, and the signal reception and distribution device SRD sends a communication path clear signal (SP-C
LR), and the content of the communication route maintenance memo address is “θ”.
'', which is the information (12) indicating idle. Therefore, as mentioned above, the writing of communication signals for all time slots is stopped in the backward communication path memory SPMB, and all communication channels are In this state, the fault recovery process is performed, and once the fault is recovered, the call status map held in the main memory MM is referred to and this call status map is disconnected. Based on the map, necessary information is written in the communication path holding memory HLM and inact memo IJIM to reset the communication path.

However, if this failure is in a mode not related to the communication path, the main processor MPR
In this case, the signal reception distribution device SRD
does not send out the channel clear signal (SP-CLR), but instead sends out the inact memory clear signal (I-CLR) t- to clear only the inact memory IM. As a result, all communication channels are disconnected in the same manner as described above in p1.In this state, failure recovery processing is performed, and when the failure is recovered, the data at the time of failure occurrence is written in the inact memo IJ IM. Since the contents of the communication path maintenance memo IJ HLM remain as they were at the time of the failure, there is no need to perform any processing. As described above, according to the present invention, in response to a failure in this type of mode, the main processor MPR can re-establish the communication path with an extremely small amount of processing.

The present invention is not limited to the above embodiments, and can be modified in various ways.

As explained above, in this type of time-sharing electronic exchange, conventionally, even if a failure occurs in a mode that is not directly related to the communication path, the contents of the communication path holding memory are cleared once to handle the failure. At the time of failure recovery, all the data for setting the call path was rewritten in the call path holding memory by referring to the map of the call status held in the main memory, so the amount of processing by the main processor was large, and the call However, according to the present invention, in this type of failure mode, that is, failure in a mode that is not directly related to the communication path, resetting the communication path at the time of failure recovery is the main task. By placing an extra burden on the processor, the effect can be achieved in a short period of time.

[Brief explanation of the drawing]

The figure is a connection diagram of one embodiment of the present invention. T...telephone, LC...subscriber circuit, L...relay line, TRK...trunk, SMo, SMi...switch module, MPX...multiplexer, DM
PX... Demultiplexer, SPMF... Forward channel memory, SPMB... Backward channel memory, 'I'-CTR... Time slot counter, I(LM... Channel holding memory , Engineering M...Inact memory, 5-SW... Space switch, I HW
1. I HW 2... Intermediate Highway, SRD...
- Signal reception distribution device, B...common bus, MM...main memory, MPR...main processor. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Hisashi Tamamushi (3 others) (15)

Claims (1)

[Claims] Occurrence of a failure in a time-division communication path that includes a communication path memory, an inact memory that controls writing to the communication path memory for each communication path channel and controls busy/idle status of the communication channel, and a communication path holding memory that controls communication path allocation. In the resetting method in the subsequent restart processing, the inact memory is provided independently from the communication path holding memory and is capable of writing and clearing control of all addresses, and when restarting after failure recovery, the inact memory and the communication path are A call route resetting method characterized in that the call route is reset by switching the clearing control and write control of the holding memory depending on the failure mode.