JPS632194B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method between a processing device in a distribution stage in a time division switch and a control processing device in a terminal such as a subscriber line concentrator or a switchboard processing device.

The time division electronic exchange has a configuration as shown in FIG. In this figure, NW is the network, which connects and disconnects communication paths and forms the main body of the exchange. Since it is an electronic exchange, the network NW is also equipped with memory, call processor CPR, etc.
This network NW is controlled. L.C.
is a line concentrator for multiple telephone calls
NW via line l ₀ (internal connection line of the exchange with signal format, timing, etc. similar to PCM line)
Connect to. LPR is a line processor that controls LC. RLC is a remote line concentrator and has almost the same functions as LC, but this line is connected to the network NW via PCM line _l1 . RPSC is a remote position controller that controls position (switchboard for international calls, etc.) POS.
Connect to PCM line _l2 . PPR controls RPSC with a position processor. DT is a digital terminal. In addition, a trunk TRN, tone generator TG, etc. are also connected to the network NW. As shown in the figure, in such an exchange, terminal processing and distribution stage processing are carried out by each processing device.
It takes the form of so-called distributed processing using LPR, PPR, and CPR. The present invention relates to data transfer between this terminal and the processors LPR, PPR, and CPR of the distribution stage.
This data transfer is done on a time-sharing basis over the same line as the call.

The input and output of the distribution stage of the time division switching system is PCM
Generally, each port has 32 time slots, of which 30 channels (a channel is equivalent to a time slot) are used for voice communication, and the other 2 channels are used for transmitting maintenance information for the PCM line and for terminals. Used for communication. Figure 2 shows the form of communication information between the distribution stage CPR and the terminal processing units LPR and PPR. 32Ts indicates 32 time slots, which constitute one frame, and 16 such frames make up one multiframe. 1 to 15 slots in one frame
Thirty channels consisting of slots 17 to 31 (the latter are referred to as channels 16 to 30) are for voice calls. Therefore, 30 calls can be made with one PCM line. The 16th time slot is for communication of information between processing units, and 16 timeslots of these are sent, thus one multiframe is transmitted and one communication is performed. Note that one multiframe period is 2 mS. The 0th time slot is used for transmitting fault information and the like. One time slot consists of 8 bits, and in a voice call, the amplitude of the audio analog signal at one sampling point is represented by an 8-bit binary signal, which is accommodated in one time slot and transmitted. Since 16 time slots are used for communication, 128 bits is 1
It becomes a block. The CB in Figure 2 is 16 for this communication.
Shows a time slot and 128 bit information group.

The PCM line only transmits data; no synchronization clocks are sent. Instead, part of the data is set into a fixed pattern, which is detected and synchronized. For example, if 00001011 is detected, that frame is promised to be F0 (frame 0). This F0 pattern 00001011 is called a multi-frame alignment signal (MFAS).
As mentioned above, 16 time slots are used for communication, but one is reserved for MFAS, so the information that can actually be transmitted is 120 bits. Only after 120 bits have been sent does it become valid information, and it takes one multi-frame period of 2 mS to obtain this valid information. Therefore, if the information is read in the middle without waiting 2 mS, the processing device on the receiving side will malfunction based on the incorrect information.

Now, as shown in Figure 3, the line processor
Consider the case where the LPR sends to the call processor CPR a change in an event in the remote line concentrator RLC, such as the assignment of a certain subscriber to a certain time slot. When the LPR creates data to be sent to the CPR, it writes the contents to the memory SSM (send signal memory) for loading onto the 16Ts of highway _l1 from LPR to CPR. The contents of the SSM are read out in synchronization with the highway clock, loaded onto the 16Ts of each frame, and sent to the CPR via the highway, where the 16Ts extraction memory RSM
(receive signal memory), which is also written in synchronization with the highway clock. In this way, the contents of the LPR SSM are changed to the CPR RSM for each multiframe, regardless of whether there is a change in the contents.
is always forwarded to The CPR program usually reads the contents of this RSM at its own program cycle (asynchronous to the highway clock) of several tens to hundreds of milliseconds, and when there is a change in the contents, it indicates that a new event has occurred on the CPR side. Recognize and process. However, this conventional processing scheme requires reading and checking every word of the RSM for every terminal response, which impacts throughput.

Therefore, for example, the first bit of the 16th slot of each frame indicates whether the information of this frame is valid or invalid (content-wise meaning: valid or not: even when there is no information to be sent, there is some data in 16Ts. “1”, “0” indicates that the
bit flag (signal present bit)
A method is being considered in which the CPR reads this SPB, and if it is "1", it looks at the bit again after 2 mS or more, and if it is also "1", it reads the memory RSM. However, simply "1" is valid and "0" is not valid, it is not possible to tell whether the information in the RSM is the same or different from the information at the previous reading timing, so in CPR, the previous reading information (8 bits x 16 words ) is stored in a buffer, compared with the current information, and if it differs, the required processing is performed as new information, which is complicated and cumbersome.

The present invention improves these points and is highly efficient.
The aim is to create a data transfer system that can process data quickly, and its features include a processing device that controls the distribution stage that exchanges calls, and a PCM line that connects directly to the input/output port of the communication path of the distribution stage. Data in a time-division switching system that uses specific channels to send and receive information to and from terminal control processors that are included in and control communication path concentrators or switchboard controllers that are connected via In the transfer method, a part of the specific channel is used as a flag, and the flag includes a first value indicating that the information is being transmitted, and a second value indicating that the information has been transmitted. The second and third values have a function of indicating whether or not the information is the same as the previous one, and the processing device on the receiving side has a value of 3. The purpose is to monitor the flag in the memory and determine whether the memory is readable, necessary, or unnecessary, and then performs processing.

That is, the present invention makes the flag 2 bits, 00, 01,
This flag can take on 11 three values, and indicates that writing is currently in progress and reading is not possible, and that writing has been completed and reading is possible. For example, flag 2 is assigned to the former, flags 1 and 3 are assigned to the latter, and it is displayed whether or not the information in 1 and 3 is different from each other. In this example, flag 2
Assign 00 to flag 3, 01 to flag 1, and its inverted bit 10 to flag 1. Figures 4 and 5 illustrate how these flags are used. First, to explain with reference to Fig. 4, when a certain information A has been written, the flag is 1 at the left end of Fig. 4, and in this state, when information changes to B and begins to be sent, the flag becomes 2.
The flag becomes 3 when the transfer is completed. While the information to be transmitted is B, the memory RSM is repeatedly rewritten, but the flag remains at 3. When the information to be transmitted becomes C, the flag changes to 2, and when the transmission ends, the flag changes to 1. The same applies below.

Figure 5 is a diagram that explains this in a little more detail.
When the transmission of new information A begins, the aforementioned MFAS is first placed on 16Ts of F0 (in this figure, MFAS=
00001011 is denoted by A ₀ ), which is written to the first 8 bits of the 16Ts receptacle of the memory RSM. next
A flag F= is placed on the first two bits of 16Ts of F1, indicating that R (reading) is not possible. _A1 in the figure shows 8-bit information of 16Ts of F1, the first two bits of which are flag 2. Also, the underline added to this _A1 etc. indicates that this Ts information is currently being written. There is no flag in 16Ts of F2, and all 8 bits thereof are information (part of A information). The same is true for F3, and the information of these 16Ts is
Indicated by A ₂ , A ₃ .... When one multiframe ends and the next multiframe is sent, if the information to be transmitted is still A, the memory RSM will be rewritten with the same contents, but in this state, the memory RSM will be filled with new information. Since it has been rewritten and can be read, the flag is set to 3 on the LPR side (since the previous flag was 1), and this is written to the RSM by F1 transmission. The next information to be transmitted is B.
, the first frame F0 of the transmission period simply sends MFAS (in this figure, this is called B ₀ , but the content is the same as A ₀ ), but F1
_{Thereafter, the information B is transmitted in small pieces as B 1 ,} B ₂ . The same applies below.

The processor CPR on the receiving side uses memory RSM A ₁ ,
We are looking at only the second 8 bits where B ₁ ... is written, and if the first 2 bits are flag 2, it is unreadable, and if it is 1 or 3, it is readable, and the flag is different between the previous read and the current read. 1 or 3
If it is unchanged, the contents are the same, so there is no need to read it. In this way, there will be no malfunction caused by reading the data when it should not be read, and there will be no need to read the same content repeatedly, which is very effective in reducing the software load on the receiving processor and preventing malfunction.

As described above, according to the present invention, information transmission and processing between processors performing distributed processing can be carried out extremely efficiently and reliably, and is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the signal format, FIG. 3 is an explanatory diagram of the transmission and reception mode between processors, and FIGS.
The figure is a diagram illustrating how the flags are changed. In the drawing, CPR is the distribution stage processing equipment, LPR, PPR
is the terminal control processing unit, l ₀ to _{l 2} are the lines, 1, 2, 3
is a flag.

Claims (1)

[Scope of Claims] 1. A processing device that controls a distribution stage that performs call exchange, and a communication path concentrator or switching board control device that is connected directly or via a PCM line to the input/output port of the communication path of the distribution stage. In a data transfer method in a time division switching system that uses a specific channel to send and receive information to and from the terminal control processing unit that is included in the terminal and controls them, a part of the specific channel is used as a flag. , a first flag indicating that the information is being transmitted.
and second and third values indicating that the information has been transmitted, and the second and third values have a function of indicating whether the information is the same as the previous one. The data is characterized in that the processing device on the receiving side monitors the flag in the information written to the memory, determines whether the memory can be read, needs to be read, or is not necessary, and performs processing. Transfer method.