JP2705507B2 - Signal transit exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION It is used for 7 common channel signaling system signal exchanges. In particular, the No. 1 configured with a loosely-coupled multiprocessor system has the same configuration. The present invention relates to a distributed processing system for a signal switching and exchange system using a common line signaling system.

[0002]

2. Description of the Related Art FIG. It is a block diagram of a common line signal network of 7 common line signal systems. Integrated Services Digital Network (I
In the case of SDN) as an example, the signaling system is mainly used for setting and releasing calls between exchanges such as a subscriber line exchange directly connected to a user and an exchange such as a transit exchange in a network. This is a protocol intended to be used for call control. In particular, in the common channel signaling system, a signal for controlling a call and a signal for talking are transmitted on different lines. The common channel signaling system is used for transferring service processing data and the like between a service control node in a network having a database related to communication service processing and an exchange. The service control node database contains number translation information and location information of mobile units (vehicles, etc.), and service processing messages are used for number translation and mobile location search between the exchange and the service control node. Be exchanged. FIG.
As shown in (1), when the common channel signaling method is used, a signal link is prepared separately from a communication path for transferring voice and data between users. In addition, a signal relay exchange having a function of relaying a signal link and a signal message (signal relay station, S
A common line signal network composed of TP (Signal Transfer Point) is configured. Through this common line signaling network, call control messages between exchanges and service processing messages between exchanges and service control nodes are transferred.

[0003] Conventionally, a signal relay exchange has a distributed processing system in which each signal processor has a loosely coupled multiprocessor system having its own local memory and no shared memory and performing distributed signal processing. When sending a signal to a signal line of another signal processor (signal processing device), a signal is sent to another signal processor using an inter-processor communication path, and a signal is sent to a target signal line via the signal processor. Was sent out.

[0004]

However, in such a conventional signal transit exchange, when a signal is transmitted to a signal line of another signal processing processor, the signal is transmitted to another signal processor using an interprocessor communication path. This is a distributed processing system that sends signals and sends the signals to the target signal line via the signal processor, so the signal delay increases and the load for communication between the processor of the signal processor increases. there were.

[0005] Software is stored in a shared memory accessible by all processors constituting the loosely coupled multiprocessor system, and management data when the software runs is also stored in the shared memory. A method of performing distributed processing and failure processing of software based on the state indicated by the provided processor state determination device to reduce local memory usage and take measures against processor failure (Japanese Patent Laid-Open No. 2-287)
No. 667) or a method of balancing the load of a plurality of processors by using another calculation center site from a terminal of another calculation center site in a calculation center site having a loosely-coupled multiprocessor configuration (Japanese Patent Laid-Open No. 62-189548). However, none of these methods is a method in which a signal from a signal line of the own signal processing device is signal-processed, routed, and transmitted to a signal line of another signal processing device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and a signal relay exchange which can reduce a signal delay when transmitting a signal processed from a signal line of another signal processing apparatus and can reduce a load on a signal processor. The purpose is to provide.

[0007]

SUMMARY OF THE INVENTION The present invention provides a plurality of signal processing devices connected to a plurality of signal lines, respectively, for routing a signal received from one of the plurality of signal lines and transmitting the signal to another signal line. Each of the signal processing devices is connected to each other via a communication path between processors, and constitutes a loosely coupled multiprocessor system. 7. In the signal switching exchange of the common line signaling system, each of the signal processing devices routes a signal received from one of a plurality of signal lines connected to the own signal processing device and transmits the signal from another signal processing device. In this case, means for directly transmitting the received signal to a signal line of another signal processing device via the inter-processor communication path is included.

Further, according to the present invention, each of the above signal processing devices includes:
A signal processor for routing a received signal, a main memory connected to the signal processor, a communication line controller connected to a plurality of signal lines, the main memory, and the communication line controller And an inter-processor communication device connected to the central processing system bus and controlling signal transmission and reception between the own signal processing device and another signal processing device. It can be connected to another signal processing device via the inter-processor communication path.

Further, according to the present invention, each of the communication line system line controllers includes a communication line system interface processor connected to its own central processing system bus for controlling signal transmission and reception between its own signal processing processor and its own signal line. The communication system may include a communication path bus connected to the communication path interface processor and a plurality of communication path apparatuses connected to the communication path bus and accommodating a plurality of signal lines, respectively.

[0010]

When routing a signal received via a signal line connected to its own signal processing device and transmitting the signal from a signal line of another signal processing device, the received signal is transmitted via an inter-processor communication path. By directly transmitting the signal to the signal line without passing through the signal processor of another signal processing device, the signal delay is reduced when the signal processed from the signal line of another signal processing device is transmitted, and the signal processing is performed. The load on the processor can be reduced.

[0011]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a signal exchange according to an embodiment of the present invention. FIG. 2 is a detailed block diagram of the signal processing device of the signal relay exchange of the present invention. In FIG. 1 and FIG. 2, a signal transit exchange is connected to a plurality of signal lines 5 and is configured to route a signal received from one of the plurality of signal lines 5 and transmit the signal to another signal line 5. The signal processing devices 20 are connected to each other by the inter-processor communication path 3 to form a loosely-coupled multiprocessor system.

A feature of the present invention is that each signal processing device 20 routes a signal received from one of the plurality of signal lines 5 and transmits the signal from the signal line 5 of another signal processing device 20. The received signal is transmitted to the signal line 5 of another signal processing device 20 through the inter-processor communication path 3.
In other words, it includes a means for directly sending the information to the user.

Each of the signal processing devices 20 includes a signal processor 1 for routing a received signal, a main memory 2 connected to the signal processor 1, and an SP system line controller connected to a plurality of signal lines 5. The device 4, the CP bus 9 as a central processing bus connecting the main memory 2 and the SP circuit controller 4, and the connection between the own signal processor 20 and the other signal processor 20 connected to the CP bus 9 And an inter-processor communication device 10 that controls the transmission and reception of signals.
Is connected to another signal processing device 20 via the.

Further, each communication path system line controller 6 includes a communication path system interface processor 6 which is connected to the own CP system bus 9 and controls transmission and reception of signals between the own signal processing processor 1 and the own signal line 5. An SP bus 7 serving as a communication path bus connected to the SP interface processor 6
And a plurality of SP devices 8 connected to the SP bus 7 and sharing and accommodating the plurality of signal lines 5 respectively.

The operation of the thus configured signal relay exchange will be described. In FIG. 1, the SP line controller 4
Receives the signal from the signal line 5 and notifies the signal processor 1 by writing the signal on the main memory 2. When the processor 1 knows that a signal has been written on the main memory 2, it routes the signal and determines a signal line 5 to be transmitted next. When the signal line 5 to be transmitted is in the own signal processor 1, the signal is transmitted to the signal line 5 via the SP-system line controller 4 by writing in the main memory 2. When the signal line 5 to be transmitted is not in the own processor, the signal is transmitted to the signal line 5 of another signal processor 1 via the inter-processor communication path 3.

Referring to FIG. 2 in more detail,
In the route A, the signal processor 1 uses its own signal processor 20
This is a route for transmitting and receiving signals to and from the signal line 5 in the inside. The SP interface processor 6 functions like a channel. That is, signals are transmitted and received between the signal processor 1 and the signal line 5 via the main memory 2. Route B is a route B in which the signal processor 1 communicates with the signal processors 1 of the other signal processors 20.
Comprising _1, and a route B ₂ to the signal processor 1 transmits a signal to the signal line 5 of the other signal processing unit 20. The route B ₁ and the route B ₂ have the same physical address of the signal processing device 20, but are identified by logical address information (service access point, SAP) added to the signal by the signal processor 1. . Therefore, the root B1 and Route B ₂ has a queue for transmission and reception separately (Route B ₂ is transmitted queues only).

The route C is a signal transmission route (one-way, transmission only) to the own signal line 5 requested by the signal processor 1 of the other signal processing device 20. Request from another signal processing apparatus 20 is received by the inter-processor communication device 10 by the route B _2, the inter-processor communication device 10 C
A signal is sent to the SP interface processor 6 via the P bus 9.

As described above, the interprocessor communication device 10
Is obtained by adding a route for transmitting a signal to the signal line 5 of another signal processing device 20 to a general interprocessor communication function. In this case, a normal inter-processor communication signal is identified by a logical address called SAP.

In FIG. 2, the SP system device 8 is connected to the signal line 5
Is notified that the signal has been received, the SP interface processor 6 is notified, and the interface processor 6 writes the signal to the main memory 2. Signal processor 1
Knows that the signal has been written to the main memory 2,
The signal line 5 to which the signal is to be routed and transmitted next
To determine.

When the signal line 5 to be transmitted is in the own signal processing unit 20, the signal line 5 is written to the main memory 2 to be transmitted to the signal line 5 by the SP unit 8 via the SP interface processor 6. Send a signal.

The signal line 5 to be transmitted is the own signal processor 2
If it is not within 0, a signal is transmitted to the interprocessor communication device 10 by writing to the main memory 2. The inter-processor communication device 10 transmits a signal to the inter-processor communication device 10 of another signal processing device 20 via the inter-processor communication path 3, and the inter-processor communication device 10 of the other signal processing device 20 adds a signal to the received signal. By sending a signal directly to the SP interface processor 6 without passing through the signal processor 1 based on the obtained logical address information, the signal is sent to the signal line 5 of another signal processing device 20.

[0023]

As described above, the present invention has an excellent effect that a signal delay can be reduced when a signal processed from a signal line of another signal processing device is transmitted, and a load on a signal processor can be reduced. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal exchange according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of the signal processing device of the signal relay exchange of the present invention.

FIG. FIG. 2 is a configuration diagram of a common line signaling network of a 7 common line signaling system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal processor 2 Main memory 3 Inter-processor communication path 4 SP system line controller 5 Signal line 6 SP system interface processor 7 SP system bus 8 SP system device 9 CP system bus 10 Inter-processor communication device 20 Signal processing device 30 Signal relay Exchange 40 exchange 41 switch 42 control unit 50 common channel signaling network 60 service control node

Claims (3)

(57) [Claims] A plurality of signal processing units connected to a plurality of signal lines for routing a signal received from one of the plurality of signal lines and transmitting the signals to another signal line; Nos. That are connected by a communication path between processors to form a loosely coupled multiprocessor system. 7. In the signal switching exchange of the common line signaling system, each of the signal processing devices routes a signal received from one of a plurality of signal lines connected to the own signal processing device and transmits the signal from another signal processing device. And a means for directly transmitting the received signal to a signal line of another signal processing device via the inter-processor communication path. 2. Each of the signal processing devices includes a signal processor for routing a received signal, a main memory connected to the signal processor, and a communication line control device connected to a plurality of signal lines. A central processing system bus for connecting the main memory to the communication channel control device, and a processor connected to the central processing system bus for controlling signal transmission and reception between the own signal processing device and another signal processing device. 2. The signal exchange according to claim 1, further comprising a communication device, wherein the inter-processor communication device is connected to another signal processing device via the inter-processor communication path. 3. A communication path interface processor which is connected to an own central processing system bus and controls transmission / reception of signals between its own signal processing processor and its own signal line. 2. The signal exchange according to claim 1, further comprising: a communication path system bus connected to the processor; and a plurality of communication path system devices connected to the communication path system bus to respectively share and accommodate a plurality of signal lines.