JPS5854458A - Controlling system for history memory - Google Patents

Abstract

PURPOSE:To perform write and read-out of history data concurrently by collecting information in each part of a system and recording the collected information in a history memory as history data. CONSTITUTION:On the assumption that a history memory 12-1 is selected by a write memory selecting circuit 13, history data are successively written in the history memory 12-1. When a prescribed event takes place, the memory selecting circuit 13 selects the succeeding history memory 12-2. As the result, the history data are successively written in the history memory 12-2. When the history data are to be read out from the history memory 12-1, the history memory 12-1 is selected by a read memory selecting circuit 14. After changing the contents of a read address register 15, the whole contents of the history memory 12-1 are read out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for writing and reading history data in a busy history database so that writing history data and reading history data can be performed in parallel.
This relates to a memory control method.

It has been conventional practice to store information about each part of a computer in memory as history data. FIG. 2 shows an example of a conventional history memory device, where 1 indicates a memory address counter and 2 indicates a history memory. The memory artless φ counter 1 is incremented by 1 every time a synchronization clock is generated.

Memory address counter 1 provides an address for history memory 2, and history data is written to the address specified by memory 1 address counter 1. History data is composed of information about each part of the computer.

In a history memory device as shown in Fig. 1,
When reading the history data in the history memory 2, it is necessary to stop writing the history data to the history memory 2.

When performing computer tests or troubleshooting, you may want to read history data while recording it.

SUMMARY OF THE INVENTION The present invention meets the above requirements and aims to provide a control method for a busy history memory so that writing of history data and reading of history data can be performed in parallel. . Therefore, the control method for the memory of the present invention collects information from each part of the system and stores it as history data.
In a history memory device configured to record in memory, multiple history memories and any history
a write address generation circuit whose contents are updated each time history data is written to the memory or a gold finger is generated;
A read memory selection circuit that specifies which history memory to read history data from, a read address register that specifies a read address, and a write address to the history memory specified by the write memory selection circuit. write gate means for supplying write control information including a read address; and successive gate means for supplying read control information including a read address to the history memory specified by the read memory selection circuit. It is characterized by: Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 11 is a memory address counter;
12-1 to 12-4 are history memories, 13 is a write memory selection circuit, 14 is a read memory selection circuit, 15 is a read address register, G11 to G
14 and G! 1 to 0.4 indicate gates, respectively.

The memory address counter 11 specifies the writing address of history data.

Each time a synchronization clock is generated, its contents are incremented by one.

The write memory selection circuit 13 specifies which of the history memories 12-1, 12-2, 12-3, and 12-4 to write the history data into. For example, when the write memory selection circuit 13 selects the history memory 12-1 as a write target, the gate G
1. is opened, and the write address and write control signal output from memory address counter 11 are supplied to history memory 12-1. The read address register 15 specifies the read address of history data. The read memory selection circuit 14 stores the history data in the history memories rJ12-1 to 12-4.
This specifies which of the following is to be read. For example, the read memory selection circuit 14 selects the history memory 1
When 2-2 is selected as the read target, the game) G- is fogged and the read address 1 is output by the read address.
address and read control signals to the history memory 12-
2.

Assume now that the write memory selection circuit 13 selects the history memory 12-1. Then, the history data is stored in the history memory 12-IK.
Sequential writing When a predetermined event occurs, such as the state of the computer moving to the next state, the write memory selection circuit 13 selects the next history memory 12-
Select 2l-1t. As a result, the history data is sequentially written to the history memory 12-2. History・
When it is desired to read history data from the memory 12-1, the read memory selection circuit 14 selects the history memory 12-1, and the contents of the read address register 15 are sequentially changed. , history memory 12
-Read all contents of 1 O As is clear from the above description, according to the present invention, it is possible to record history data and read history data in parallel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of a conventional history memory device. 11...Memory address counter, 12-1 to 12-4...History memory, 13...Write memory selection circuit, 14...Read memory 1 selection circuit, 15...Read -Address register, G. Or G14 and G! 1 or G□...Gate. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] A history memory device that collects information about each part of a V stem and records this as history data in a history memory, comprising a plurality of history memories;
A write memory selection circuit that specifies which history memory to write history data to, a write address generation circuit whose contents are updated every time a synchronous clock is generated, and a write address generation circuit that specifies which history memory to write history data to.・
A read memory selection circuit that specifies whether to read data, a read address register that specifies a read address, and a write control information that is specified by the write memory selection circuit and includes a write address is supplied to the history memory. A control method for a history memory, comprising a write gate means and a read gate means for supplying read control information including a read address to the history memory specified by the read memory selection circuit. .