JPS5854117U - modulation circuit - Google Patents

modulation circuit

Info

Publication number
JPS5854117U
JPS5854117U JP14949381U JP14949381U JPS5854117U JP S5854117 U JPS5854117 U JP S5854117U JP 14949381 U JP14949381 U JP 14949381U JP 14949381 U JP14949381 U JP 14949381U JP S5854117 U JPS5854117 U JP S5854117U
Authority
JP
Japan
Prior art keywords
switch
terminal
modulation circuit
switches
ground terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14949381U
Other languages
Japanese (ja)
Inventor
吹抜 敬彦
松井 一征
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP14949381U priority Critical patent/JPS5854117U/en
Publication of JPS5854117U publication Critical patent/JPS5854117U/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Amplitude Modulation (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は振幅変調波の波形図、第2図は従来のスイッチ
ドキャ/くシタ回路による変調回路、第3図は本考案に
よる変調回路の一実施例の回路図、第4図は上記実施例
の動作説明のためのタイムチャート図、第5図は上艷実
施例におけるスイッチ7の変形例を示す図である。 1・・・・・・入力端子、2・・・・・・出力端子、3
−1. 3−2.3−3.14・・・・・・スイッチド
キャパシタ、4、 5. 6. 7. 11. 12.
 15・・・・・・スイッチ、8・・・・・・帰還コン
デンサ、9・・・・・・演算増幅器、13・・・・・・
スイッチ駆動回路。
Fig. 1 is a waveform diagram of an amplitude modulated wave, Fig. 2 is a modulation circuit using a conventional switched capacitor circuit, Fig. 3 is a circuit diagram of an embodiment of a modulation circuit according to the present invention, and Fig. 4 is a circuit diagram of an embodiment of the modulation circuit according to the present invention. FIG. 5 is a time chart diagram for explaining the operation of the example, and is a diagram showing a modification of the switch 7 in the upper embodiment. 1...Input terminal, 2...Output terminal, 3
-1. 3-2.3-3.14...Switched capacitor, 4, 5. 6. 7. 11. 12.
15... Switch, 8... Feedback capacitor, 9... Operational amplifier, 13...
Switch drive circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 演算増幅器および単一のスイッチドキャパシタと、上記
キャパシタの一端に少なくとも入力端子、アース端子、
取出し端子を切換る第1のスイッチと、他の一方の端子
を少なくともアース端子と取出し端子を切換える第2の
スイッチと、上記スイッチを駆動するスイッチ駆動回路
とで構成された・ことを特徴とする変調回路。
an operational amplifier and a single switched capacitor, with at least an input terminal, a ground terminal, and a ground terminal at one end of the capacitor;
The device is characterized in that it is comprised of a first switch that switches the output terminal, a second switch that switches the other terminal between at least the ground terminal and the output terminal, and a switch drive circuit that drives the switch. Modulation circuit.
JP14949381U 1981-10-09 1981-10-09 modulation circuit Pending JPS5854117U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14949381U JPS5854117U (en) 1981-10-09 1981-10-09 modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14949381U JPS5854117U (en) 1981-10-09 1981-10-09 modulation circuit

Publications (1)

Publication Number Publication Date
JPS5854117U true JPS5854117U (en) 1983-04-13

Family

ID=29942260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14949381U Pending JPS5854117U (en) 1981-10-09 1981-10-09 modulation circuit

Country Status (1)

Country Link
JP (1) JPS5854117U (en)

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