JPS5853777B2 - Common bus control method in multiprocessor systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control method in a multiprocessor system, particularly a multiprocessor system suitable for common bus monitoring.

FIG. 1 shows a block diagram of a multiprocessor system.

Each of the processors 3 has an individual bus C, and controls an input/output circuit 4 connected to the individual bus C.

Data transfer between each processor 3 is performed using a common bus A.

That is, the processor 3 requesting data transfer transfers the data to the affiliated passport 2 via the communication bus B.

After the passport 2 takes possession of the common bus A, it outputs data to the common bus, and each passport 2 receives the data and transfers the data to each processor 3 through the communication bus B.

Furthermore, since a failure in the common bus A will result in a system down, the status of the common bus A is constantly monitored, and when a failure is detected, an alarm is immediately displayed to indicate the details of the failure, and if necessary, the system is connected to the failed processor 30. A bus monitoring control circuit 1 that performs configuration control to disconnect the passport 2 is connected to the common bus.

FIG. 2 shows an internal configuration diagram of the common bus A mentioned above.

The common bus A consists of a command/data identification signal line A1, a message signal line A2, a timing signal line A3, a bus occupancy identification signal line A4, and an interface reset signal line A5.

FIG. 3 shows a diagram of the data structure carried on the signal lines A2 and A1.

The signal line A2 consists of an 8-bit configuration of DIO to DIγ.
Signal line A1 consists of one bit of command/data identification signal ATN.

When the command/data identification signal ATN is 1'', there are four command formats as shown in the figure, depending on the data structure of the 8-bit message signal.

That is, they are a polling command POL, a status report request command STC, a bus connection command GTR, and a bus disconnection command GTL.

PNO displayed in these four command forms indicates a port number.

When the command/data identification signal ATN is +o+'', there are two types of commands: status report data STS and transfer data DATA.

That is, the command/data identification signal ATN is used to distinguish between data signals and non-data signals.

The timing signal on the timing signal line A3 is for reliably transmitting the above-mentioned message signal and command/data identification signal ATN.

Bus occupancy identification signal IDY on bus occupancy identification signal line A4
is a bus occupancy declaration signal for polling command POL.

The interface reset signal IFC on the reset signal line A5 is a signal that resets all bus ports 2 and returns the state of the common bus A to the same state as at the initial time.

Next, the contents of the message signal and data will be explained.

The polling command POL uses port number PNO (third
In the example shown in the figure, the command uses 5 pure binary bits to ask whether there is a bus occupancy request for bus port 2 specified by 0 to 31). If there is a bus occupancy request, the bus occupancy identification Passport 2 outputs Shinshin IDY.

If there is no bus occupancy request, the bus occupancy identification signal IDY is not output, so a timeout is detected and the next passport 2
A polling command PQL is issued to.

The above-mentioned bus occupancy control is performed by the passport 2 that currently has the bus occupancy right, and the bus occupancy right is sequentially transferred.

The procedure is shown in FIG. The figure shows that bus occupancy is accepted at port Aj.

The status report request command STC is a command that requests the passport 2 specified by the port number PNO to transmit the status report data STS.

This status data STS is used to report to the bus monitoring control circuit 1 a processor failure, an input/output circuit failure, etc. that can be recognized within the bus port 2.

The status report request command STC is a command used only by the bus monitoring control circuit 1, and its procedure is shown in FIG.

In this figure, when the passport 2 itself fails, the status data STS cannot be returned in response to the status report request command STC, so this is detected as a timeout, and the failure is detected.

The bus connection command GTR and bus disconnection command GTL are
This is a command used by the bus monitoring control circuit 1 during configuration control, and is a command for instructing whether or not to connect each passport 2 to the common bus A.

Next, 20 examples of bus ports are shown in FIG.

The bus port shown in this figure has a processor 21 for processing inside the bus port.

An internal bus D is connected to this processor 21.

The message signals and command/data identification signal ATN on the signal lines A2 and A1 are temporarily stored in the message signal buffer register 23 by a signal from the timing signal control circuit 24, taken into the processor 21, decoded, and conversely sent from the processor 21. Message signal buffer register 23
The timing signal is temporarily stored by outputting commands and data to the timing signal control circuit 24, and a timing signal is outputted via the signal line A3 by turning on the timing signal control circuit 24.

The bus occupancy identification signal IDY via the signal line A4 is taken into the processor 21 by the buffer gate 25 and output from the processor 21.

The data signal relay buffer register 26 is a temporary buffer register for data transfer with the processor 3 via the signal line B1, and the timing of the transfer is determined by the timing signal control circuit 27 via the signal line B2.

Data transfer processing, bus occupancy control processing, and status reporting processing of the passport 2 are performed by the processor 21 according to a program stored in the memory 22.

The details of the failure in the processor 3 and the input/output circuit 4 communicated through the failure communication signal on the signal line B3, and the failure detected in the passport 2 are recognized by the failure recognition circuit 28 and taken into the processor 21.

The interface reset signal IFC obtained via the signal line A5 is input as a reset signal to the processor 21.

FIG. 7 shows an example of the configuration of the bus monitoring control circuit 1.

The bus monitoring control circuit 1 shown in the figure is also provided internally like the bus port 2, and is controlled by a processor 11 to which an internal bus E is connected.

The operations of the message signal buffer register 13 and the timing signal control circuit 14 are the same as in the passport 2.

The difference from Passport 2 is that it has a function to output an interface reset signal IFC via signal line A5, and it has a timing signal monitoring circuit 16 that monitors the timing signal of signal line A3 and detects bus congestion. Display alarm circuit 1 that displays and alarms system abnormalities
7.

Now, the bus monitoring control circuit 1 detects an abnormality in the entire system,
Identifies the faulty part, displays an alarm, and automatically disconnects the faulty part as necessary, or the processor 3
Switch to the standby system when the system is overloaded.

However, as an abnormality detection means within the bus monitoring and control circuit 1, there is a method of detecting congestion on the common bus A using the timing signal monitoring circuit 16, but it is not possible to detect abnormalities in the input/output circuit 4, and the processor 3 An abnormality can only be detected when another processor transfers data to the abnormal processor, and the abnormality detection ability is insufficient.

Therefore, it is necessary to periodically read the contents of the failure recognition circuit 28 in the bus port 2 and check the status of the entire system at all times.

As a method of reading the contents of the failure recognition circuit 28 in the passport 2, there are the above-mentioned status report request command STC and status report data STS, and when the response cannot be received, each input/output is determined to be abnormal in the passport 2. Abnormalities in the circuit 4, each processor 3, and each passport 2 can be identified.

Therefore, the bus supervisory control circuit 1 intermittently takes possession of the bus in the same manner as the passport 2, sequentially issues status report request commands STC to the passport 2, and constantly monitors the system.

However, if this method is adopted, if an abnormality occurs in the bus supervisory control circuit 1 when the bus supervisory control circuit 1 takes possession of the bus, the common bus will go down, that is, the system will go down, even though it is a single failure. turn into.

In order to avoid this, the bus monitoring control circuit 1 should be duplicated,
One possible method is to have them monitor each other, but as the amount of birds increases, circuits at the same level will monitor each other, and if a considerable abnormality is detected, they will be disconnected.
This was extremely difficult because it was technically contradictory as to whether it was really the other party's abnormality or whether it was my own abnormality that led to such recognition.

SUMMARY OF THE INVENTION An object of the present invention is to provide a common bus control method in a multiprocessor system that reduces system downtime due to a single failure of a bus supervisory control circuit.

The gist of the present invention is that when the failure recognition circuit in each bus port detects an abnormality, the bus monitoring control circuit inquires of each passport as to whether there is a failure.

Examples of the present invention are shown below.

In this embodiment, recognition of processor failure is detected on the bus port, and the result is sent to the bus monitoring control circuit through a newly provided signal line on the common bus.

FIG. 8 shows an embodiment of a common bus signal line according to the present invention.

Compared to the conventional common bus signal line, a bus supervisory control circuit activation signal line A6 for carrying a bus supervisory control circuit activation signal (SVC') is added.

This signal is output from the failure recognition circuit 28 as shown in the block diagram of the passport 2 in FIG. be done.

On the other hand, in the bus monitoring control circuit 1, as shown in FIG. 10, the abnormal output signal of the timing signal monitoring circuit 16 and the signal line A6
The start signal is ORed by the OR gate 18, and the interrupt signal E1 is input to the processor 11 in the bus monitoring control circuit 1.

In the bus monitoring control circuit 1, the output circuits of each signal are normally locked so as not to cause disturbance to the common bus due to an abnormality, and when the interrupt signal E1 is input to the processor 11, the processing according to the flowchart shown in FIG. 11 is performed. I do.

First, acquire the right to occupy the bus. When the common bus A is normal (for example, the common bus is not disturbed when the input/output circuit 4 is abnormal), a bus occupancy identification signal ( IDY), but if the passport 2 malfunctions during data transfer, the polling command POL will not be issued.

Therefore, in that case, a timeout is detected and an interface reset signal IFC is output via the signal line A5.
Reset all bus ports 2 and forcibly take possession of the bus.

After acquiring bus occupancy, as before, the status report request command STC is issued to each bus port 2, status report data STS is received, and initial status data or collected at the time of previous abnormality detection is collected for each passport. After identifying the part where the abnormality has occurred by comparing it with the status data obtained, a display warning is issued, and configuration control such as disconnection processing is performed as necessary depending on the degree of failure.

For example, in this configuration control, when processor 3 is abnormal, a bus disconnection command GTL is sent to its passport, but even if port number (PNO) 3 is abnormal, if the abnormality is input/output circuit 4, common bus A Leave it connected to.

Also, when Passport 2 is abnormal, it outputs an interface reset signal (IFC), disconnects all passports from the common bus, and issues a bus connection command (G
TR) is sent.

In addition, in the case of duplication, even if any part of the regular system, including the input/output circuit, fails, the bus disconnection command GTL is sent to the regular system and the bus connection command GTR is sent to the backup system.
Performs automatic separation of heavy loads.

After completing the series of processes described above, bus occupancy control processing is performed in the same way as for Passport 2, and occupancy rights are transferred to Passport.

If this method is adopted, the bus supervisory control circuit 1 will output to the common bus A only in the event of an abnormality, thereby avoiding system down due to a single failure.

However, even with this method, there is a risk that the data may be erroneously output to the common bus A due to runaway of the processor 11 in the bus monitoring and control circuit 1.

For this purpose, a runaway check circuit 19 is provided as shown in FIG.

A specific example of the circuit is shown in FIG.

That is, the one-shot multi-circuit 51 is activated by the interrupt signal E1, and while the output signal is being output, the start signal E is activated.
3 is input, the DT flip-flop 52 is set, the output lock signal E2 obtained by inverting its output signal by the inverter 53 is released, and the output circuit lock to the common bus A by the hardware is released.

When the process of the bus supervisory control circuit for giving bus occupancy to the passport 2 is completed, a stop signal E4 is output, the DT flip-flop 52 is reset, and the output circuit is locked again.

By adopting this method, it is possible to prevent a common bus disturbance when the processor 11 runs out of control and is activated without the interrupt signal E1.

Even in this method, if the bus monitoring control circuit 1 is activated by mistake due to a failure in the timing signal monitoring circuit 16, there is still a possibility that it will be connected to the common bus incorrectly, but the amount of hardware in the timing signal monitoring circuit 16 is small. In addition, if the processor 11 is normal even if an interrupt occurs, there will be no change in the status in the status report data STS received from each passport, and normal processing can be performed and the failure of the timing signal monitoring circuit 16 will be detected. This is not a problem because it is localized and a warning is displayed.

According to the present invention, only when an abnormality is detected in the system (recognizing a fault in the processor or detecting an abnormality in the common bus), the bus monitoring control circuit inquires of each passport about the presence or absence of a fault through each common bus. Since the output of the bus supervisory control circuit is locked, the possibility of system failure due to a single failure of the bus supervisory control circuit is reduced.

[Brief explanation of the drawing]

Figure 1 is a diagram of a conventional example of a multiprocessor system, Figure 2 is a diagram of its common bus configuration, Figure 3 is a diagram of an example data configuration on the common bus, Figures 4 and 5 are illustrations of operation, and Figure 6 7 is a diagram showing a configuration example of a conventional passport, FIG. 7 is a diagram showing a configuration example of a conventional bus monitoring control circuit, FIG. 8 is a diagram showing an example of a common bus configuration applied to the present invention, and FIG. FIG. 10 is an embodiment of the bus monitoring and control circuit used in the present invention, FIG. 11 is an explanatory diagram of its operation, and FIG. 12 is an embodiment of the bus monitoring and control circuit of the present invention. Figure, 13th
The figure is a concrete example diagram of a part of FIG. 12. 1...Bus monitoring control circuit, 2...Passport, 3...Processor, A...Common bus, A6...Bus monitoring control Circuit start signal line.

Claims (1)

[Claims] 1. A plurality of processors are each connected to a common bus via a bus port, and each passport has a failure recognition circuit that recognizes a failure of the processor connected to the bus port I. In a multiprocessor system in which a bus monitoring control circuit provided monitors the common bus and queries each passport via the common bus to see if there is a failure when a bus abnormality is detected, each passport recognizes a failure. , has a means for outputting a start signal to a bus monitoring control circuit, and the bus monitoring control circuit receives the start signal and inquires of each passport as to whether there is a failure or not, and the passport that received the inquiry A common bus control system in a multiprocessor system, characterized in that a failure state recognized at the bus port is reported to the bus monitoring control circuit. 2. A signal line for activating the bus supervisory control circuit is provided on the common bus, and the failure recognition circuit outputs a activation signal to the bus supervisory control circuit through the signal line when a failure is recognized. A common bus control method in a multiprocessor system according to claim 1. 3. Claims characterized in that the bus monitoring and control circuit has an abnormality detection means that constantly detects abnormalities in the common bus, and when an abnormality is detected, an inquiry is made to each passport as to whether or not there is a failure. A common bus control method in the multiprocessor system according to item 1.