JPH0520251A - Switching system for duplexed process input/output device - Google Patents

Abstract

PURPOSE:To allow respective boards to mutually execute status monitoring in a duplexed processing I/O device and to normally and quickly switch respective boards. CONSTITUTION:An abnormality detecting circuit 23 in each of the boards 3a, 3b executes self-diagnosis, forms a status signal indicating a normal state, an abnormal state, an abnormality restored state, or communication disabled state, transmits the formed status signal to the opposite board, stores the status signals of the self-board and the opposite board in a control/status register 18 in the self-board, and then informs a CPU which is not shown of the contents of the register 18, so that initialization for operating one board with higher priority, allowing the board to input/output data from/to the external and making the other board standby. If the active board is an abnormal state or a communication disabled state and the active board is a normal state or an abnormality restored state, setting the active and standby of these boards are immediately switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual process input / output device switching system for performing mutual switching between an active process input / output device and a standby process input / output device.

[0002]

2. Description of the Related Art In the fields of so-called device industry and manufacturing industry, the process is often extremely complicated, and therefore it is usual to perform process control by an electronic computer system.
In this case, since the reliability of the electronic computer system directly influences the productivity or the product quality, conventionally, the entire system including an electronic computer for process control (hereinafter, abbreviated as CPU) and an interface with an external terminal, or Process downtime for external I / O with the CPU Duplication of only the process I / O device, and when an error occurs in one system or device, immediately detect this and switch to the other system, etc. Is made as short as possible (JP-A-48-74146, etc.).

[0003]

However, the conventional duplex system has an abnormality detecting function for each system or device, but does not have a mutual status monitoring function. Therefore, when an abnormality occurs in one of the systems and the switching is performed, the state of the other must be confirmed each time, and there is a problem that the operating rate and reliability are poor.

In recent years, in order to carry out efficient maintenance management of the system, attention has been paid to a hot-plugging / unplugging system in which a defective part or a board is exchanged in a powered state. The applicant of the present invention has also proposed, in Japanese Patent Application No. 3-48525, a method of performing hot-plugging and unplugging while preventing disturbance of a data bus, destruction of mounted components, and malfunction. However, for example, when hot-swapping is performed on one of the redundant process input / output devices, the fact that the hot-swap start, process, and end cannot be known on the other process input / output device or CPU side by the conventional duplexing method. Therefore, if the CPU accidentally accesses it,
In some cases, switching was performed without returning to normal.

The present invention was devised in view of the above problems, and it is possible to improve reliability and operating rate, and to perform hot-swap and CPU access normally. An object is to provide a switching system of the device.

[0006]

In order to achieve the above object, the present invention provides a dual process input / output device comprising two process input / output devices capable of simultaneously accessing one electronic computer and communicating with each other. External I / O by switching to one of the process I / O devices, and performing a self-diagnosis on each process I / O device, and a status signal indicating at least a normal state, an abnormal state, an abnormal recovery state, or an unconnectable state. For generating the status signal, the status signal passing means for passing the status signal of the other party and the status signal of the other party, and the state memory for storing the status signal of the other party and the own status signal received by the status passing means. Means is provided, and by notifying the computer of the contents of the state storage means, one of the process input / output devices is operated and external input / output is performed. And volume, with the initial setting to wait for the other, the process input and output device in operation is in an abnormal state or contact disabled state, and, when the process input and output devices are waiting in a normal state or abnormal return state,
The process I / O device operation and standby settings can now be switched.

[0007]

In the state storage means of each process input / output device, the state signal of the other party is stored together with its own state signal by the state signal passing means. Therefore, by reading the stored contents of the state storage means of either one of the process input / output devices, the CPU can immediately know the states of both process input / output devices, and can perform appropriate access and quick switching. Further, even when hot-plugging and unplugging is being performed in one of the devices, the status signal sent to the other device can immediately inform the start, process, and end facts, so that the CPU erroneously accesses the device. There is no need to switch or switch.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram of a system including a dual process input / output device of this embodiment. In the figure, 1 is a CPU, 2
Is a CPU bus, 3 is a dual process input / output device (hereinafter,
4 is a status signal transfer signal cable, 5 is an external input / output cable, and 6 is a single process input / output device (hereinafter abbreviated as PIO).

The CPU 1 inputs data from a large number of PIOs 6 via the CPU bus 2 and performs a predetermined calculation,
The result is output to each PIO 6.

The duplicated PIO 3 is configured exclusively for duplication, and can simultaneously access the CPU 1 and can communicate with each other by a cable between the status signal passing signal cable 4, the external input / output cable 5 and the CPU bus 2. It is equipped with two PIOs. For each PIO,
Furthermore, self-diagnosis is performed and at least normal state, abnormal state,
Both PIOs have means for generating a status signal indicating an abnormal recovery state and an uncontactable state, and status storage means for storing the status signal of the other party received by the status signal transfer cable 4 and the status signal of its own. Except when they fail at the same time
In the case of normal or one-sided failure, it guarantees that the access from the CPU 1 and the external input / output are always normal. Also, in the case of a one-sided failure, it is possible to perform insertion / extraction on a hot line.

FIG. 2 is a diagram showing a concrete example of the structure of the duplicated PIO 3, which is composed of two PIOs (boards) 3a and 3b having exactly the same structure. 10a, 10b in each board
Is an input connector, 11a and 11b are output connectors, 12
Reference numerals a and 12b denote status signal input / output connectors.

For example, for one board 3a, 1
Reference numeral 3 is a reference voltage, 14 is a multiplexer, 15 is an A / D converter, 16 is a local CPU, 17 is a local CPU bus, 18 is a control / status register as a status signal storage means, 19 is a data register, 20 is a bus buffer, 21 is a bus lock circuit, 22 is a D / A conversion circuit,
23 is an abnormality detection circuit, 24 is an output control circuit, and 25 is V /
An I conversion output buffer, 26 is an I / V conversion circuit, and 27 is a status buffer.

In this dual PIO 3, an analog signal is handled as an external input / output signal, and the input signal is DC 1-5 [V],
The output signal is 4 to 20 [mA].

External input signals are input to the input connectors 10a and 10b of both boards 3a and 3b, respectively, and external output signals are output connectors 11a and 11 of the boards 3a and 3b, respectively.
It is output from either one of b. That is, one of the boards 3a and 3b is "active" and the other is "standby", and the input / output signals from the "active" boards are valid.
The status signal generating means is composed of an abnormality detection circuit 23 and a status buffer, and further includes two boards 3
The status signal input / output connectors 12a and 12b of a and 3b are connected by the status signal transfer cable 4 to form a status signal transfer means.

A control / status signal and a data signal are exchanged between the CPU 1 and both boards 3a and 3b via the CPU bus 2.
The basic function of is that the CPU 1 can input these signals from any of the boards 3a and 3b, and
Each signal guided from 1 to both boards 3a and 3b is output from only one of the boards to the outside, and when an abnormality occurs in the one board, the other board automatically outputs the external signal. Is to be output. Below, duplicated P
The operation of IO3 will be specifically described.

(Operating conditions) (1) An external input signal is led from the "working" board to the CPU 1. Further, the signal from the CPU 1 is output to both the "operating" and "standby" boards. However, when an error occurs, the board on the error side is not accessed. Also, the external output signal is output only from the "working" board.

(2) "Operating" / "standby" can be confirmed from both boards 3a and 3b by a status signal.

(3) There is no master / slave setting on each board 3a, 3b, and the initial setting of "operating" / "standby" is CPU1.
Do.

(At power-up) (1) Both the boards 3a and 3b of the dual PIO 3 have their own ROM, RAM, and reference voltage inputs of the A / D conversion circuit 15 in their own board, which the local CPU 16 does not show. Etc. are checked, and the normal / abnormal results are written in the control / status register 18 for self-diagnosis.

(2) The CPU 1 reads the self-diagnosis result of the redundant PIO 3 from the control / status register 18 and judges normality / abnormality. If either one or both boards are normal, "operation" / "standby" Set "" for each board, and perform signal input from the "working" board and signal output to both boards.

(3) The redundant PIO 3 operates according to the above setting, and the board set to "active" outputs the signal from the CPU 1 to the outside (external output ON).

(In normal operation) External input / output signal and C
The exchange of control / status signals and data signals with PU1 is executed according to a predetermined procedure, and redundant P
The basic functions of IO3 are executed.

Next, a method of detecting an abnormality in each of the boards 3a and 3b will be described.

1. The local CPU 16 of each board, that is, checks the input of the reference voltage 13 of the A / D conversion circuit 15 and the D / A conversion circuit 22, and notifies the abnormality detection circuit 23 of the result. Further, a watchdog timer (not shown) for checking the abnormality of the local CPU 16 itself is provided, and the abnormality detection circuit 23 is accessed within a fixed time to detect the timeout.

These results are notified to the other board through the status signal passing cable 4 and also to the CPU 1 through the control / status register 18. The status signal and the status of the control / status register 18 at this time are shown below.

(A) Status signal 1,0 ..... abnormal recovery state (startup state: CPU
No access from 1 to each board 3a, 3b) 0,1 ........ Normal state 0,0 ........ Abnormal state 1,1 .. State (cable disconnected state: state in which the cable side connector is removed from the board connector) This signal is a bidirectional signal consisting of 2 bits, and is exchanged between the boards. The reason why 2 bits are set is that in addition to the normal / abnormal notification between the boards (1 bit), the information is accurately notified to the mating board when the cable-side connector is removed by hot plugging / unplugging. In addition, when the board on the removed side is inserted by hot line, the startup state is notified to the partner board, and the information is notified to the CPU1 via the control / status register 18 of the partner board and accessed from the CPU1. This is to encourage

Note that the 2-bit logical combination may be one other than the above, and the number of bits may be increased to obtain more detailed information.

(B) Control / status register 1, 0, 1, 0 ・ ・ ・ ・ ・ ・ Abnormal recovery state 0, 1, 0, 1 ・ ・ ・ ・ ・ ・ Normal state 0, 0, 0 , 0 ・ ・ ・ ・ ・ ・ Unusual state 1,1, 1,1 ・ ・ ・ ・ ・ ・ Unable to contact (other board) (own board) In this way, the control / status register 18 Be able to read not only the state of the board but also the state of the other board. This is because when an abnormality occurs in any of the boards, the access from the CPU 1 is stopped, and the abnormal board is hot-swapped, the control / control of the other board is performed when the board returns to normal due to replacement or the like. This is because the signal can be read through the status register 18. This makes CP
Access of U1 can be started without any trouble.

By devising the status signal and control / status register 18 as described above, the status of the mating boards can be monitored by each other, and the status of both boards can be known from the CPU 1 even if one board is removed. Therefore, it is possible to access according to normality / abnormality.

On the other hand, external output is performed as follows.

(After power-up) In the processing at the time of power-up, the CPU 1 sets "operating" / "standby" for both boards 3a and 3b. Each board follows the setting, and turns on the output control circuit 24 when it is "operating".
Turn on the external output. In the "standby" state, the output control circuit 24 is turned off and the external output is turned off, that is, the external output is not output.

(In normal operation) Based on the status signal of the own board and the status signal from the partner board, it is determined which board is to output. The results are shown in Table 1.

[0034]

[Table 1]

Referring to Table 1, when both boards are normal, the "operating" board is turned on and external output is performed.
When one board is abnormal, the other board becomes "active" and outputs externally. If both boards are faulty, neither board outputs.

It is preferable to provide an interlock circuit having the structure shown in FIG. 3, for example, in order to prevent simultaneous output from both boards.

2. Next, a method of replacing the abnormal board by hot-plugging will be described.

When an abnormality occurs on the board, the CPU 1
Can be found by reading the control / status register 18 or by the operation monitor LED of the duplicated PIO 3. At this time, the external input / output is performed on the normal side board, and the abnormal board stops the access of the CPU 1.

In the abnormal board, first, the status signal passing cable 4 is removed, and then the external input / output cable is set by the above-mentioned hot-line insertion / removal method by the applicant of the present invention.
It is removed without disturbing the local CPU bus 17 and the CPU bus 2. The fact that these cables have been removed can be seen by the other board monitoring the status signal of its own board.

When inserting a repaired board or spare parts, first, the external input / output cable is connected to the board by the hot-swap method, and then the status signal passing cable 4 is connected. At this time, the other board (the "operating" board) is informed that the board has been started up by the status signal sent from the status signal passing cable 4. The CPU1 reads the control / status register 18 of the "operating" board,
After knowing that the abnormal board has become normal, normal processing can be performed thereafter.

[0041]

As described above, according to the present invention, the switching of the duplex process input / output device which can improve the reliability and the operating rate and can normally perform the hot-swap and the CPU access can be performed. A scheme can be provided.

[Brief description of drawings]

FIG. 1 is a system conceptual diagram of a duplex process input / output device to which the present invention is applied.

FIG. 2 is a specific configuration diagram of a redundant process input / output device used in this embodiment.

FIG. 3 is a configuration diagram of an interlock circuit used in this embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electronic computer (CPU), 2 ... CPU bus, 3 ... Redundant process input / output device, 3a, 3b ... Process input / output device (board), 4 ... Status signal transfer cable, 5 ...
External input / output cable, 6 ... Single process input / output device, 10a, 10b ... External input terminal, 11a, 11b ...
External output terminals, 12a, 12b ... Status signal input / output terminals,
13 ... Reference voltage, 14 ... Multiplexer, 15 ... A / D
Conversion circuit, 16 ... Local CPU, 17 ... Local CP
U bus, 18 ... Control / status register (state signal storage means), 19 ... Data register, 20 ... Bus buffer, 21 ... Bus lock circuit, 22 ... D / A conversion circuit, 23 ... Abnormality detection circuit, 24 ... Output control Circuit, 25 ...
V / I conversion output buffer, 26 ... I / V conversion circuit, 27
… Status buffer.

Claims (1)

Claims: What is claimed is: 1. A dual process input / output device comprising two process input / output devices capable of simultaneously accessing one electronic computer and communicating with each other, in any one of the process input / output devices. A method of switching external input / output, a means for performing self-diagnosis on each process input / output device, and generating a status signal indicating at least a normal status, an abnormal status, an abnormal recovery status, and an unconnectable status, and its own status. A state signal passing means for passing a signal and a state signal of the other party, and a state storing means for storing the state signal of the other party and the own state signal received by the state passing means are provided. By notifying the computer of the contents of the above, the initial setting for operating one of the process input / output devices to allow external input / output and waiting for the other If the process I / O device that is operating is in an abnormal state or cannot be contacted, and the process I / O device that is waiting is in the normal state or abnormal recovery state, set the operation and standby of the process I / O device. A dual process input / output device switching method characterized by switching the input and output.