CN103150224A - Electronic equipment and method for improving starting reliability - Google Patents
Electronic equipment and method for improving starting reliability Download PDFInfo
- Publication number
- CN103150224A CN103150224A CN2013100773560A CN201310077356A CN103150224A CN 103150224 A CN103150224 A CN 103150224A CN 2013100773560 A CN2013100773560 A CN 2013100773560A CN 201310077356 A CN201310077356 A CN 201310077356A CN 103150224 A CN103150224 A CN 103150224A
- Authority
- CN
- China
- Prior art keywords
- cpu
- daughter board
- mainboard
- bootstrap memory
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses electronic equipment and a method for improving starting reliability. According to the electronic equipment and the method, when a daughter board CPU (central processing unit) of a module daughter board fails to load a bootstrap program from a bootstrap memory, a mainboard CPU can be automatically triggered to master control power of the bootstrap memory of the module daughter board, and refreshes the bootstrap program in the bootstrap memory of the module daughter board; in addition, after the mainboard CPU completes refreshing, the daughter board CPU can load the bootstrap program from the bootstrap memory in the module daughter board again. Therefore, incapable starting of the module daughter board due to damage or mismatching of the bootstrap program can be effectively relieved; outage and manual refreshing are not required to be conducted on the electronic equipment; and the starting reliability of the electronic equipment can be improved.
Description
Technical field
The present invention relates to start-up technique, particularly a kind of for improving the electronic equipment that starts reliability and being used for improving the method that starts reliability.
Background technology
Electronic equipment need to load and move one section Boot(guiding by CPU after CPU powers on, before operating system brings into operation) program.The Boot program is all to be kept in the Boot storer usually, and after CPU powered on or resets, it can load Boot program and operation from the Boot storer, thereby realized normal the startup; If but be kept at the executable code damage of the Boot program in the Boot storer or do not mate with operating system, will cause CPU to move mistakenly the Boot program, thereby cause electronic equipment normally to start.
In practical application, the Boot storer can be selected the flash memory such as Flash() etc. nonvolatile memory, common Boot storer comprises Nor(or non-) Flash, Nand(and non-) Flash, SPI(Serial Peripheral Interface Serial Peripheral Interface (SPI)) Flash.By contrast, the data access difficulty of Nor Flash is minimum, number of pin maximum, cost is the highest, the data access difficulty of Nand Flash is the highest, cost is moderate, number of pin is moderate, the data access difficulty of SPI Flash is moderate, number of pin is minimum, cost is minimum, therefore, SPI Flash is used as the Boot storer more and more at present.
The core of electronic equipment due to CPU, and the code that the Boot program is carried out after to be CPU power at first, so can CPU successfully load from SPI Flash the basis that the Boot program is reliability of electronic equipment.
Correspondingly, if select SPI Flash as the Boot storer, the addressing mode due to SPI Flash is indirect addressing, can't realizes backup logic in the sheet of Boot program, therefore, is all usually to realize physical backup to the Boot program by two SPI Flash are set.
At the electronic equipment of the certain module that is used for network service, usually can be used for realizing that the mainboard of master control function arranges the physical backup mode of two SPI Flash; But for be used for realizing the module daughter board of modular functionality such as interface board etc., due to its PCB(Printed Circuit Board, printed circuit board (PCB)) area is less, thereby can not adopt the physical backup mode of two SPI Flash.
Thereby, for the module daughter board that adopts single SPI Flash, when the executable code of the Boot program in its SPI Flash damages or do not mate with operating system, will cause the module daughter board normally to start, thereby affect the overall operation of electronic equipment; And, damage or the executable code of unmatched Boot program if need to refresh in SPI Flash, must outage and manual refreshing.
Summary of the invention
In view of this, the invention provides a kind of a kind of electronic equipment and method for improving the startup reliability for improving the startup reliability.
Provided by the invention a kind of for improving the electronic equipment that starts reliability, mainboard and module daughter board, mainboard has mainboard CPU, the module daughter board has daughter board CPU and bootstrap memory and logic chip, and this bootstrap memory is the nonvolatile memory of indirect addressing and the boot of depositing daughter board CPU;
Be connected with reseting signal line between logic chip and daughter board CPU, control daughter board CPU for logic chip after the module daughter board powers on and enter the start-up loading state;
Be connected with an I/O bus between logic chip and daughter board CPU, detect daughter board CPU for logic chip after daughter board CPU enters the start-up loading state and whether load successfully;
Reseting signal line between logic chip and daughter board CPU also is used for logic chip and loads unsuccessfully afterwards that control daughter board CPU enters the hold reset state detecting daughter board CPU;
Be connected with between logic chip and mainboard CPU and report signal wire, be used for logic chip and load unsuccessfully and report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU afterwards detecting daughter board CPU;
Reseting signal line between logic chip and daughter board CPU also is used for logic chip to be completed at mainboard CPU and again enters the start-up loading state to controlling daughter board CPU after the refreshing of bootstrap memory;
And, be connected with between logic chip and bootstrap memory the first interface bus, and daughter board CPU between be connected with the second interface bus, be connected with the 2nd I/O bus between logic chip and mainboard CPU; Wherein, as daughter board CPU during from bootstrap memory bootload program, logic chip is first interface bus and the second interface bus conducting, with allow daughter board CPU under the start-up loading state from bootstrap memory bootload program; When mainboard CPU send to be used for refreshing boot to bootstrap memory, logic chip with first interface bus and the 2nd I/O bus conducting, and realize in the indirect addressing of first interface bus to bootstrap memory, so that mainboard CPU refreshes boot by logic chip to bootstrap memory afterwards extremely receiving to report.
Daughter board CPU further represents to load successful notice to the logic chip write-back after loading successfully, logic chip receives in the schedule time after daughter board CPU enters the start-up loading state that according to whether this notifies to detect daughter board CPU and whether load successfully.
Mainboard CPU further has the interrupt pin that connection reports signal wire, and logic chip reports to mainboard CPU with interrupt mode extremely.
Be connected with the business transfer bus between mainboard CPU and daughter board CPU.
Logic chip comprises startup monitoring logic circuit, cpu reset logical circuit, switch control logic circuit and access control logic circuit, wherein:
Start the monitoring logic circuit, when the module daughter board powers on or mainboard CPU completes after the refreshing of bootstrap memory, trigger the start-up loading state of daughter board CPU, and detect the stress state of daughter board CPU by an I/O bus; After detecting daughter board CPU and loading unsuccessfully, trigger daughter board CPU and enter the hold reset state, and by reporting signal wire to report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU;
The cpu reset logical circuit after the start-up loading state that starts monitoring logic circuit triggers daughter board CPU, is controlled at the start-up loading state by reseting signal line with daughter board CPU; After the hold reset state that starts monitoring logic circuit triggers daughter board CPU, by reseting signal line, daughter board CPU is controlled at the hold reset state;
The switch control logic circuit is when mainboard CPU refreshes bootstrap memory, with first interface bus and access control logic circuit turn-on; All the other are constantly with first interface bus and the second interface bus conducting;
The access control logic circuit, when receiving the boot that mainboard CPU refreshes to bootstrap memory from the 2nd I/O bus, the boot that receives is transmitted from the first interface bus to bootstrap memory and realized that logic chip is to the indirect addressing of bootstrap memory by the switch control logic circuit.
Further be provided with the startup that connects an I/O bus in logic chip and complete register; Wherein, the default configuration that register is completed in startup loads not successful invalid value for expression daughter board CPU, and when daughter board CPU was successfully completed loading, startup was completed register and is set to effective value by daughter board CPU;
And, in the schedule time after the start-up loading state that triggers daughter board CPU, if completing register, startup is set to effective value by daughter board CPU, and start the monitoring logic circuit and confirm that daughter board CPU loads successfully; Otherwise, start the monitoring logic circuit and confirm that daughter board CPU loads unsuccessfully.
Further be provided with refreshing of the 2nd I/O bus of connection in logic chip and complete register, wherein, refresh the default configuration of completing register and complete for the expression bootstrap memory effective value that refreshes; When start the monitoring logic circuit report to mainboard CPU abnormal after, refresh and complete register and be activated the monitoring logic circuit and be set to expression and do not complete the invalid value that refreshes; When mainboard CPU is successfully completed when rear to refreshing of bootstrap memory, refreshes and complete register and reverted to effective value by mainboard CPU;
And to complete register be effective value if refresh, start monitoring logic circuit triggers daughter board CPU and enter the start-up loading state, otherwise, start monitoring logic circuit triggers daughter board CPU and enter the hold reset state and report extremely to mainboard CPU.
Further be provided with the adapter status register that connects the 2nd I/O bus in logic chip; Wherein, the default configuration of taking over status register is the invalid value that mainboard CPU does not take over, when mainboard CPU refreshes bootstrap memory, take over status register and be set to by mainboard CPU the effective value that expression mainboard CPU takes over, when mainboard CPU completes after the refreshing of bootstrap memory, take over status register and reverted to invalid value by mainboard CPU;
And, if the switch control logic circuit when taking over status register and be effective value with first interface bus and the 2nd I/O bus conducting, when the adapter status register is invalid value with first interface bus and the second interface bus conducting.
Further be provided with the data buffer storage and the memory address register that connect the 2nd I/O bus in logic chip, wherein, data buffer storage is used for depositing the boot that mainboard CPU refreshes to bootstrap memory, and memory address register is used for mainboard CPU and writes the address that bootstrap memory is deposited boot;
And the access control logic circuit transmit by the switch control logic circuit boot in data buffer storage and according to the address the memory address register realization indirect addressing to bootstrap memory from the first interface bus to bootstrap memory.
Bootstrap memory is SPI Flash, and first interface bus and the second interface bus are spi bus.
Provided by the invention a kind of for improving the method that starts reliability, the method is applied to comprise in the electronic equipment of mainboard and module daughter board, the module daughter board has daughter board CPU and bootstrap memory and logic chip, and this bootstrap memory is the nonvolatile memory of indirect addressing and the boot of depositing daughter board CPU; And the method comprises:
After the module daughter board powers on, with bootstrap memory and daughter board CPU conducting, and control that daughter board CPU enters the start-up loading state so that daughter board CPU under the start-up loading state from bootstrap memory bootload program;
After daughter board CPU enters the start-up loading state, detect daughter board CPU and whether load successfully;
After detecting daughter board CPU and loading unsuccessfully, control daughter board CPU and enter the hold reset state, and report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU;
, bootstrap memory is switched to and mainboard CPU conducting, and realize indirect addressing to bootstrap memory according to extremely sending of reporting during be used to the boot that refreshes to bootstrap memory as mainboard CPU;
When mainboard CPU completes after the refreshing of bootstrap memory, bootstrap memory is switched back and daughter board CPU conducting, and control daughter board CPU and again enter the start-up loading state.
Daughter board CPU further after loading successfully write-back represent to load successful notice, the method receives in the schedule time after daughter board CPU enters the start-up loading state that according to whether this notifies to detect daughter board CPU and whether load successfully.
Mainboard CPU further has interrupt pin, and the method reports with the interrupt pin of interrupt mode to mainboard CPU extremely.
The method further arranges to start completes register; Wherein, the default configuration that register is completed in startup loads not successful invalid value for expression daughter board CPU, and when daughter board CPU was successfully completed loading, startup was completed register and is set to effective value by daughter board CPU;
And, in the schedule time after the start-up loading state that triggers daughter board CPU, if completing register, startup is set to effective value by daughter board CPU, and the method confirms that daughter board CPU loads successfully; Otherwise the method confirms that daughter board CPU loads unsuccessfully.
The method further arranges to refresh completes register, wherein, refreshes the default configuration of completing register and completes for the expression bootstrap memory effective value that refreshes; When the method report to mainboard CPU abnormal after, refresh and complete register and be set to expression by the method and do not complete the invalid value that refreshes; When mainboard CPU is successfully completed when rear to refreshing of bootstrap memory, refreshes and complete register and reverted to effective value by mainboard CPU;
And to complete register be effective value if refresh, and the method triggers daughter board CPU and enters the start-up loading state, otherwise the method triggers daughter board CPU and enters the hold reset state and report extremely to mainboard CPU.
The method further arranges the adapter status register; Wherein, the default configuration of taking over status register is the invalid value that mainboard CPU does not take over, when mainboard CPU refreshes bootstrap memory, take over status register and be set to by mainboard CPU the effective value that expression mainboard CPU takes over, when mainboard CPU completes after the refreshing of bootstrap memory, take over status register and reverted to invalid value by mainboard CPU;
And, the method when taking over status register and be effective value with bootstrap memory and mainboard CPU conducting, when the adapter status register is invalid value with bootstrap memory and daughter board CPU conducting.
The method further arranges data buffer storage and memory address register, wherein, data buffer storage is used for depositing the boot that mainboard CPU refreshes to bootstrap memory, and memory address register is used for mainboard CPU and writes the address that bootstrap memory is deposited boot;
And the method realizes indirect addressing to bootstrap memory with the boot in data buffer storage to bootstrap memory transmission and according to the address in memory address register.
Bootstrap memory is SPI Flash.
This shows, the present invention is at the daughter board CPU of module daughter board during from bootstrap memory bootload procedure failure, can automatically trigger mainboard CPU and control to the control of the bootstrap memory of module daughter board and by the boot in the bootstrap memory of mainboard CPU refresh module daughter board; And, when mainboard CPU complete refresh after, daughter board CPU is the bootstrap memory bootload program from the module daughter board again.Thereby the present invention can effectively be alleviated the module daughter board due to the damage of boot or not mate and can't start, and need not electronic equipment outage and manual refreshing, and then can improve the reliability that electronic equipment starts.
Description of drawings
Fig. 1 is used for improving the structural representation of the electronic equipment that starts reliability in the embodiment of the present invention;
Fig. 2 is the mainboard CPU in electronic equipment and the logical organization schematic diagram of module as shown in Figure 1;
Fig. 3 is the logical organization schematic diagram of the logic chip in electronic equipment as shown in Figure 1;
Fig. 4 is used for improving the schematic flow sheet of the method that starts reliability in the embodiment of the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Referring to Fig. 1, be used for improving the electronic equipment that starts reliability in the present embodiment, comprise mainboard 100 and module daughter board 200, mainboard 100 has mainboard CPU10, module daughter board 200 has daughter board CPU20, SPI Flash30 and logic chip 40, wherein, deposit the Boot program (be to select SPI Flash30 as example take bootstrap memory in the present embodiment, but applicable too for other the nonvolatile memory of indirect addressing) of daughter board CPU20 in this SPI Flash30.
Be connected with reseting signal line Rst_signal between logic chip 40 and daughter board CPU20, be connected with I/O bus in plate between logic chip 40 and daughter board CPU20, be connected with between logic chip 40 and mainboard CPU20 and report signal wire Abnor_signal.
Correspondingly, after module daughter board 200 powered on, logic chip 40 can be controlled daughter board CPU20 by reseting signal line Rst_signal and enter the start-up loading state; After daughter board CPU20 entered the start-up loading state, whether logic chip 40 can detect daughter board CPU20 by I/O bus in plate and load successfully; After detecting daughter board CPU20 and loading unsuccessfully, logic chip 40 can be controlled daughter board CPU20 by reseting signal line Rst_signal and enter the hold reset state, and by reporting signal wire Abnor_signal to report extremely (for example with interrupt mode), refresh SPI Flash30 to trigger mainboard CPU10 to mainboard CPU10.
And, be connected with between logic chip 40 and SPI Flash30 spi bus, and daughter board CPU20 between be connected with another spi bus (if the nonvolatile memory of indirect addressing of selecting other is as bootstrap memory, spi bus need to change to the interface bus that matches), be connected with I/O bus between plate between logic chip 40 and mainboard CPU10.
Correspondingly, when daughter board CPU20 loaded the Boot program from SPI Flash30, logic chip 40 loaded Boot program from SPI Flash30 to allow daughter board CPU20 with two sections spi bus conductings under the start-up loading state; When mainboard CPU10 send to be used for refreshing Boot program to SPI Flash30, logic chip 40 with I/O bus conducting between one section spi bus between logic chip 40 and SPI Flash30 and plate, and realize in the indirect addressing of this section spi bus to SPI Flash30, so that mainboard CPU20 can refresh the Boot program to SPI Flash30 by logic chip 40 after abnormal receiving to report.
As seen, in above-mentioned electronic equipment, when the daughter board CPU20 of module daughter board 200 loads the Boot procedure failure from SPI Flash30, can be detected by logic chip 40, also automatically trigger mainboard CPU10 control to the control of the SPIFlash30 of module daughter board 200, thereby by the Boot program in the SPI Flash30 of mainboard CPU10 refresh module daughter board 200; And, when mainboard CPU10 completes after the refreshing of SPI Flash30, logic chip 40 can control daughter board CPU20 again the SPI Flash30 from module daughter board 200 load the Boot program.Thereby the above-mentioned electronic equipment that the present embodiment provides can effectively be alleviated module daughter board 200 due to the damage of Boot program or not mate and can't start, and need not electronic equipment outage and manual refreshing, and then can improve the reliability that electronic equipment starts.
please in referring to Fig. 1 in conjunction with Fig. 2, when the above-mentioned electronic equipment of specific implementation, daughter board CPU20 is after being successfully completed loading, can represent to load successful notice to logic chip 40 write-backs, logic chip 40 receive daughter board CPU20 write-back according to whether in the schedule time after daughter board CPU20 enters the start-up loading state this notify to realize to detect, namely, in the schedule time after the start-up loading state that triggers daughter board CPU20, if logic chip 40 has been received the notice of daughter board CPU20, think that daughter board CPU20 loads successfully, otherwise think that daughter board CPU20 loads unsuccessfully.Correspondingly, in order to realize the above-mentioned informing function of daughter board CPU20, can move one section write-back program in the processing kernel of daughter board CPU20, process kernel by this write-back program can drive CPU20 the I/O controller, and by I/O bus in plate to the logic chip 40 above-mentioned notices of write-back, process kernel and can also drive the SPI controller and realize the program from SPI Flash30 loading Boot by spi bus.
Please in referring to Fig. 1 in conjunction with Fig. 2, when the above-mentioned electronic equipment of specific implementation, mainboard CPU10 can have and connects the interrupt pin report signal wire Abnor_signal; Correspondingly, logic chip 40 can adopt the mode of interruption to report extremely to mainboard CPU10.
Please in referring to Fig. 1 in conjunction with Fig. 2, when the above-mentioned electronic equipment of specific implementation, for realize that mainboard CPU10 response logic chip 40 reports abnormal, and carry out the refreshing of SPI Flash30, can move one section to report extremely the refurbishing procedure as trigger condition in mainboard CPU10.in addition, can be connected with the business transfer bus between mainboard CPU10 and daughter board CPU20, namely, between the plate between mainboard CPU10 and logic chip 40, the I/O bus is a hardware access passage that is independent of outside the business transfer bus, therefore, be different from mainboard CPU10 corresponding to this refurbishing procedure of I/O bus between plate and be used for master routine with daughter board CPU20 service data transmission, thereby, even if when daughter board CPU20 successfully loads Boot program and normal operation, mainboard CPU10 also can visit SPI Flash30 by the hardware access passage based on I/O bus between plate, and can not affect the normal operation of daughter board CPU20.
Please in referring to Fig. 1 in conjunction with Fig. 3, for above-mentioned logic chip 40, the present embodiment also provides a kind of preferred implementation, as shown in Figure 3, the inside of this logic chip 40 has the monitoring logic of startup circuit 41, cpu reset logical circuit 42, switch control logic circuit 43 and access control logic circuit 44.
Start monitoring logic circuit 41 after module daughter board 200 powers on, trigger daughter board CPU20 the start-up loading state, and the stress state by I/O bus detection daughter board CPU20 in plate (be daughter board CPU20 whether within the predetermined time write-back previously described notice); Correspondingly, after the start-up loading state that starts monitoring logic circuit 41 triggering daughter board CPU, cpu reset logical circuit 42 is controlled at the start-up loading state by reseting signal line Res_signal with daughter board CPU.
Start monitoring logic circuit 41 also after detecting daughter board CPU20 and loading unsuccessfully, start monitoring logic circuit 41 triggering daughter board CPU20 and enter the hold reset state, and by reporting signal wire Abnor_signal to report extremely (for example with interrupt mode), refresh SPI Flash30 to trigger mainboard CPU10 to mainboard CPU10; Correspondingly, cpu reset logical circuit 42 is controlled at the hold reset state by reseting signal line Res_signal with daughter board CPU20.
When switch control logic circuit 43 refreshes SPI Flash30 at mainboard CPU10, mainboard CPU10 take over SPI Flash30 during in, with access control logic circuit 44 conductings of I/O bus between one section spi bus between logic chip 40 and SPI Flash30 and web joint, so that mainboard CPU20 can refresh the Boot program to SPI Flash30 by logic chip 40 after abnormal receiving to report; All the other constantly, be mainboard CPU10 do not take over SPI Flash30 during in, with the conducting of two sections SPI interface buss, load Boot program from SPI Flash30 to allow daughter board CPU20 under the start-up loading state.
When access control logic circuit 44 I/O bus between slave plate receives the Boot program that mainboard CPU10 refreshes to SPI Flash30, by I/O bus conducting between one period spi bus this moment between switch control logic circuit 43(logic chip 40 and SPI Flash30 and plate) with the Boot program that receives transmit from one section SPI between logic chip 40 and SPI Flash30 to SPI Flash30, the also indirect addressing of realization to SPI Flash30.
Start monitoring logic circuit 41 and also complete after the refreshing of SPI Flash30 at mainboard CPU10, again trigger daughter board CPU20 the start-up loading state, and the stress state by I/O bus detection daughter board CPU20 in plate (be daughter board CPU20 whether within the predetermined time write-back previously described notice); Correspondingly, after startup monitoring logic circuit 41 triggered the start-up loading state of daughter board CPU again, cpu reset logical circuit 42 was controlled at the start-up loading state by reseting signal line Res_signal with daughter board CPU again.
If after this startup monitoring logic circuit 41 still detects daughter board CPU20 and load unsuccessfully, each logical circuit in logic chip 40 need to repeat said process; If after this startup monitoring logic circuit 41 detects daughter board CPU20 and load successfully, each logical circuit in logic chip 40 can quit work, and only needs to keep the conducting of two sections SPI interface buss to get final product by switch control logic circuit 43.
In order to support daughter board CPU20 to support the detection of logic chip 40 in the write-back mode, can complete register 51 in the interior startup that I/O bus in web joint further is set of logic chip 40; Wherein, start the default configuration of completing register 51 and load not successful invalid value for expression daughter board CPU20, and when daughter board CPU20 was successfully completed loading, register 51 is completed in startup will be set to the successful effective value of expression daughter board CPU20 loading by write-back by daughter board CPU20.Correspondingly, in the schedule time after the start-up loading state that triggers daughter board CPU20, be set to effective value by daughter board CPU20 by write-back if register 51 is completed in startup, start monitoring logic circuit 51 and confirm that daughter board CPU20 load successfully; Otherwise, start monitoring logic circuit 51 and confirm that daughter board CPU20 loads unsuccessfully.
Can know in time for the ease of logic chip 40 whether mainboard CPU10 refreshes SPI Flash30 complete, can refreshing of I/O bus further is set between web joint complete register 52 logic chip 40 is interior; Wherein, refresh the default configuration of completing register 52 and complete for expression SPI Flash30 the effective value that refreshes, namely logic chip 40 acquiescence daughter board CPU20 load the Boot program from SPI Flash30; When start monitoring logic circuit 51 report to mainboard CPU10 abnormal after, refresh and complete register 52 and be activated monitoring logic circuit 51 and be set to expression and do not complete the invalid value that refreshes; When mainboard CPU10 is successfully completed when rear to refreshing of SPI Flash30, refreshes and complete register 52 and reverted to effective value by mainboard CPU10.Correspondingly, complete register 52 and be effective value if refresh, start monitoring logic circuit 51 triggering daughter board CPU20 and enter the start-up loading state, otherwise, start monitoring logic circuit 52 triggering daughter board CPU20 and enter the hold reset state and report extremely to mainboard CPU10.
Can know for the ease of logic chip 40 whether mainboard CPU10 takes over SPI Flash30, can be at the interior adapter status register 53 that I/O bus between web joint further is set of logic chip 40; Wherein, the default configuration of taking over status register 53 is the invalid value that mainboard CPU10 does not take over, when mainboard CPU10 refreshes SPI Flash30, take over status register 53 and be set to by mainboard CPU10 the effective value that expression mainboard CPU10 takes over, when mainboard CPU10 completes after the refreshing of SPI Flash30, take over status register 53 and reverted to invalid value by mainboard CPU10.Correspondingly, if switch control logic circuit 43 when taking over status register 53 and be effective value with I/O bus conducting between one section spi bus between logic chip 40 and SPI Flash30 and plate, when adapter status register 53 is invalid value with two sections spi bus conductings.
The Boot program that refreshes for the ease of logic chip 40 transmission mainboard CPU10 and to the indirect addressing of SPI Flash30, can be at interior data buffer storage 54 and the memory address register 55 that I/O bus between web joint further is set of logic chip 40, wherein, data buffer storage 54 is used for depositing the Boot program that mainboard CPU10 refreshes to SPI Flash30, and memory address register 55 is used for mainboard CPU10 and writes the address that SPI Flash30 deposits the Boot program.Correspondingly, access control logic circuit 44 can pass through the Boot program in data buffer storage 54 the one section spi bus of switch control logic circuit 43 between logic chip 40 and SPI Flash30 to SPI Flash30 transmission and according to the indirect addressing of the realization of the address memory address register 55 to SPI Flash30.
More than to being used for improving the detailed description of the electronic equipment that starts reliability in the present embodiment.Be used for improving based on this electronic equipment the ultimate principle that starts reliability, the present embodiment also provides a kind of method for improving the startup reliability, and the method can be applied to comprise in the above-mentioned electronic equipment of mainboard and module daughter board.
Referring to Fig. 4, be used for improving the method that starts reliability in the present embodiment and comprise:
Step 401, after the module daughter board powered on, with bootstrap memory and daughter board CPU conducting, and control daughter board CPU entered the start-up loading state so that daughter board CPU loads the Boot program from bootstrap memory under the start-up loading state.
Whether step 402 after daughter board CPU enters the start-up loading state, detects daughter board CPU and loads successfully.
In practical application, daughter board CPU can be further after loading successfully write-back represent to load successful notice, at this moment, this step can receive in the schedule time after daughter board CPU enters the start-up loading state that according to whether this notifies to realize to detect.
Step 403 after detecting daughter board CPU and loading unsuccessfully, is controlled daughter board CPU and is entered the hold reset state, and reports extremely, refreshes bootstrap memory with triggering mainboard CPU to mainboard CPU.
In practical application, mainboard CPU can further have interrupt pin, and at this moment, this step can interrupt mode reports to the interrupt pin of mainboard CPU extremely.
Step 404, switches to bootstrap memory and mainboard CPU conducting, and realizes indirect addressing to bootstrap memory according to extremely sending of reporting during be used to the Boot program that refreshes to bootstrap memory as mainboard CPU.
Step 405 when mainboard CPU completes after the refreshing of bootstrap memory, is switched back bootstrap memory and daughter board CPU conducting, and controls daughter board CPU and again enter the start-up loading state, then returns to step 402 and continues to detect.
In above-mentioned flow process, as long as step 402 detects daughter board CPU and loads successfully, the startup of representation module daughter board complete, also can process ends.
As seen, based on above-mentioned flow process, when the daughter board CPU of module daughter board loads the Boot procedure failure from bootstrap memory, can automatically trigger mainboard CPU control to the control of the bootstrap memory of module daughter board and by the Boot program in the bootstrap memory of mainboard CPU refresh module daughter board; And, when mainboard CPU complete refresh after, the daughter board CPU bootstrap memory from the module daughter board again loads the Boot program.Thereby the present invention can effectively be alleviated the module daughter board due to the damage of Boot program or not mate and can't start, and need not electronic equipment outage and manual refreshing, and then can improve the reliability that electronic equipment starts.
In order to support daughter board CPU to support the detection of step 402 in the write-back mode, said method can further arrange to start completes register.Wherein, the default configuration that register is completed in startup loads not successful invalid value for representing daughter board CPU, and when daughter board CPU was successfully completed loading, startup was completed register and is set to the successful effective value of expression daughter board CPU loading by daughter board CPU.Correspondingly, in the schedule time after the start-up loading state that triggers daughter board CPU, be set to effective value if register is completed in startup by daughter board CPU, the step 402 of the method confirms that daughter board CPU loads successfully; Otherwise the step 402 of the method confirms that daughter board CPU loads unsuccessfully.
Can know in time for the ease of said method whether mainboard CPU refreshes bootstrap memory complete, the method can further arrange to refresh completes register.Wherein, refresh the default configuration of completing register and complete for the expression bootstrap memory effective value that refreshes; When the method report to mainboard CPU by step 403 abnormal after, refresh and complete a step that register further comprised by step 403, the method and be set to expression and do not complete the invalid value that refreshes; When mainboard CPU is successfully completed when rear to refreshing of bootstrap memory, refreshes and complete register and reverted to effective value by mainboard CPU.Correspondingly, to complete register be effective value if refresh, the method powers on by step 401(module daughter board) or step 405(mainboard CPU refresh complete) trigger daughter board CPU and enter the start-up loading state, otherwise the method triggers daughter board CPU by step 403 and enters the hold reset state and report extremely to mainboard CPU.
Can know for the ease of said method whether mainboard CPU takes over bootstrap memory, the method can further arrange the adapter status register.Wherein, the default configuration of taking over status register is the invalid value that mainboard CPU does not take over, when mainboard CPU refreshes bootstrap memory, take over status register and be set to by mainboard CPU the effective value that expression mainboard CPU takes over, when mainboard CPU completes after the refreshing of bootstrap memory, take over status register and reverted to invalid value by mainboard CPU.Correspondingly, the method when taking over status register and be effective value by step 404 with bootstrap memory and mainboard CPU conducting, when the adapter status register is invalid value with bootstrap memory and daughter board CPU conducting.
The Boot program that refreshes for the ease of transmission mainboard CPU and to the indirect addressing of bootstrap memory, the method can further arrange data buffer storage and memory address register.Wherein, data buffer storage is used for depositing the Boot program that mainboard CPU refreshes to bootstrap memory, and memory address register is used for mainboard CPU and writes the address that bootstrap memory is deposited the Boot program.Correspondingly, the step 4014 of the method can be with the Boot program in data buffer storage to the bootstrap memory transmission and according to the indirect addressing of the realization of the address in memory address register to bootstrap memory.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (17)
1. one kind is used for improving the electronic equipment that starts reliability, it is characterized in that, comprise mainboard and module daughter board, mainboard has mainboard CPU, the module daughter board has daughter board CPU and bootstrap memory and logic chip, and this bootstrap memory is the nonvolatile memory of indirect addressing and the boot of depositing daughter board CPU;
Be connected with reseting signal line between logic chip and daughter board CPU, control daughter board CPU for logic chip after the module daughter board powers on and enter the start-up loading state;
Be connected with an I/O bus between logic chip and daughter board CPU, detect daughter board CPU for logic chip after daughter board CPU enters the start-up loading state and whether load successfully;
Reseting signal line between logic chip and daughter board CPU also is used for logic chip and loads unsuccessfully afterwards that control daughter board CPU enters the hold reset state detecting daughter board CPU;
Be connected with between logic chip and mainboard CPU and report signal wire, be used for logic chip and load unsuccessfully and report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU afterwards detecting daughter board CPU;
Reseting signal line between logic chip and daughter board CPU also is used for logic chip to be completed at mainboard CPU and again enters the start-up loading state to controlling daughter board CPU after the refreshing of bootstrap memory;
And, be connected with between logic chip and bootstrap memory the first interface bus, and daughter board CPU between be connected with the second interface bus, be connected with the 2nd I/O bus between logic chip and mainboard CPU; Wherein, as daughter board CPU during from bootstrap memory bootload program, logic chip is first interface bus and the second interface bus conducting, with allow daughter board CPU under the start-up loading state from bootstrap memory bootload program; When mainboard CPU send to be used for refreshing boot to bootstrap memory, logic chip with first interface bus and the 2nd I/O bus conducting, and realize in the indirect addressing of first interface bus to bootstrap memory, so that mainboard CPU refreshes boot by logic chip to bootstrap memory afterwards extremely receiving to report.
2. electronic equipment according to claim 1, it is characterized in that, daughter board CPU further represents to load successful notice to the logic chip write-back after loading successfully, logic chip receives in the schedule time after daughter board CPU enters the start-up loading state that according to whether this notifies to detect daughter board CPU and whether load successfully.
3. electronic equipment according to claim 1, is characterized in that, mainboard CPU further has the interrupt pin that connection reports signal wire, and logic chip reports to mainboard CPU with interrupt mode extremely.
4. electronic equipment according to claim 1, is characterized in that, logic chip comprises startup monitoring logic circuit, cpu reset logical circuit, switch control logic circuit and access control logic circuit, wherein:
Start the monitoring logic circuit, when the module daughter board powers on or mainboard CPU completes after the refreshing of bootstrap memory, trigger the start-up loading state of daughter board CPU, and detect the stress state of daughter board CPU by an I/O bus; After detecting daughter board CPU and loading unsuccessfully, trigger daughter board CPU and enter the hold reset state, and by reporting signal wire to report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU;
The cpu reset logical circuit after the start-up loading state that starts monitoring logic circuit triggers daughter board CPU, is controlled at the start-up loading state by reseting signal line with daughter board CPU; After the hold reset state that starts monitoring logic circuit triggers daughter board CPU, by reseting signal line, daughter board CPU is controlled at the hold reset state;
The switch control logic circuit is when mainboard CPU refreshes bootstrap memory, with first interface bus and access control logic circuit turn-on; All the other are constantly with first interface bus and the second interface bus conducting;
The access control logic circuit, when receiving the boot that mainboard CPU refreshes to bootstrap memory from the 2nd I/O bus, the boot that receives is transmitted from the first interface bus to bootstrap memory and realized that logic chip is to the indirect addressing of bootstrap memory by the switch control logic circuit.
5. electronic equipment according to claim 4, is characterized in that, further is provided with the startup that connects an I/O bus in logic chip and completes register; Wherein, the default configuration that register is completed in startup loads not successful invalid value for expression daughter board CPU, and when daughter board CPU was successfully completed loading, startup was completed register and is set to effective value by daughter board CPU;
And, in the schedule time after the start-up loading state that triggers daughter board CPU, if completing register, startup is set to effective value by daughter board CPU, and start the monitoring logic circuit and confirm that daughter board CPU loads successfully; Otherwise, start the monitoring logic circuit and confirm that daughter board CPU loads unsuccessfully.
6. electronic equipment according to claim 4, is characterized in that, further is provided with refreshing of the 2nd I/O bus of connection in logic chip and completes register, wherein, refreshes the default configuration of completing register and complete for the expression bootstrap memory effective value that refreshes; When start the monitoring logic circuit report to mainboard CPU abnormal after, refresh and complete register and be activated the monitoring logic circuit and be set to expression and do not complete the invalid value that refreshes; When mainboard CPU is successfully completed when rear to refreshing of bootstrap memory, refreshes and complete register and reverted to effective value by mainboard CPU;
And to complete register be effective value if refresh, start monitoring logic circuit triggers daughter board CPU and enter the start-up loading state, otherwise, start monitoring logic circuit triggers daughter board CPU and enter the hold reset state and report extremely to mainboard CPU.
7. electronic equipment according to claim 4, is characterized in that, further is provided with the adapter status register that connects the 2nd I/O bus in logic chip; Wherein, the default configuration of taking over status register is the invalid value that mainboard CPU does not take over, when mainboard CPU refreshes bootstrap memory, take over status register and be set to by mainboard CPU the effective value that expression mainboard CPU takes over, when mainboard CPU completes after the refreshing of bootstrap memory, take over status register and reverted to invalid value by mainboard CPU;
And, if the switch control logic circuit when taking over status register and be effective value with first interface bus and the 2nd I/O bus conducting, when the adapter status register is invalid value with first interface bus and the second interface bus conducting.
8. electronic equipment according to claim 4, it is characterized in that, further be provided with the data buffer storage and the memory address register that connect the 2nd I/O bus in logic chip, wherein, data buffer storage is used for depositing the boot that mainboard CPU refreshes to bootstrap memory, and memory address register is used for mainboard CPU and writes the address that bootstrap memory is deposited boot;
And the access control logic circuit transmit by the switch control logic circuit boot in data buffer storage and according to the address the memory address register realization indirect addressing to bootstrap memory from the first interface bus to bootstrap memory.
9. the described electronic equipment of any one according to claim 1 to 8, is characterized in that, bootstrap memory is SPI Flash, and first interface bus and the second interface bus are spi bus.
10. one kind is used for improving the method that starts reliability, it is characterized in that, the method is applied to comprise in the electronic equipment of mainboard and module daughter board, the module daughter board has daughter board CPU and bootstrap memory and logic chip, and this bootstrap memory is the nonvolatile memory of indirect addressing and the boot of depositing daughter board CPU; And the method comprises:
After the module daughter board powers on, with bootstrap memory and daughter board CPU conducting, and control that daughter board CPU enters the start-up loading state so that daughter board CPU under the start-up loading state from bootstrap memory bootload program;
After daughter board CPU enters the start-up loading state, detect daughter board CPU and whether load successfully;
After detecting daughter board CPU and loading unsuccessfully, control daughter board CPU and enter the hold reset state, and report extremely, refresh bootstrap memory with triggering mainboard CPU to mainboard CPU;
, bootstrap memory is switched to and mainboard CPU conducting, and realize indirect addressing to bootstrap memory according to extremely sending of reporting during be used to the boot that refreshes to bootstrap memory as mainboard CPU;
When mainboard CPU completes after the refreshing of bootstrap memory, bootstrap memory is switched back and daughter board CPU conducting, and control daughter board CPU and again enter the start-up loading state.
11. method according to claim 10, it is characterized in that, daughter board CPU further after loading successfully write-back represent to load successful notice, the method receives in the schedule time after daughter board CPU enters the start-up loading state that according to whether this notifies to detect daughter board CPU and whether load successfully.
12. method according to claim 10 is characterized in that, mainboard CPU further has interrupt pin, and the method reports with the interrupt pin of interrupt mode to mainboard CPU extremely.
13. method according to claim 11 is characterized in that, the method further arranges to start completes register; Wherein, the default configuration that register is completed in startup loads not successful invalid value for expression daughter board CPU, and when daughter board CPU was successfully completed loading, startup was completed register and is set to effective value by daughter board CPU;
And, in the schedule time after the start-up loading state that triggers daughter board CPU, if completing register, startup is set to effective value by daughter board CPU, and the method confirms that daughter board CPU loads successfully; Otherwise the method confirms that daughter board CPU loads unsuccessfully.
14. method according to claim 10 is characterized in that, the method further arranges to refresh completes register, wherein, refreshes the default configuration of completing register and completes for the expression bootstrap memory effective value that refreshes; When the method report to mainboard CPU abnormal after, refresh and complete register and be set to expression by the method and do not complete the invalid value that refreshes; When mainboard CPU is successfully completed when rear to refreshing of bootstrap memory, refreshes and complete register and reverted to effective value by mainboard CPU;
And to complete register be effective value if refresh, and the method triggers daughter board CPU and enters the start-up loading state, otherwise the method triggers daughter board CPU and enters the hold reset state and report extremely to mainboard CPU.
15. method according to claim 10 is characterized in that, the method further arranges the adapter status register; Wherein, the default configuration of taking over status register is the invalid value that mainboard CPU does not take over, when mainboard CPU refreshes bootstrap memory, take over status register and be set to by mainboard CPU the effective value that expression mainboard CPU takes over, when mainboard CPU completes after the refreshing of bootstrap memory, take over status register and reverted to invalid value by mainboard CPU;
And, the method when taking over status register and be effective value with bootstrap memory and mainboard CPU conducting, when the adapter status register is invalid value with bootstrap memory and daughter board CPU conducting.
16. method according to claim 10, it is characterized in that, the method further arranges data buffer storage and memory address register, wherein, data buffer storage is used for depositing the boot that mainboard CPU refreshes to bootstrap memory, and memory address register is used for mainboard CPU and writes the address that bootstrap memory is deposited boot;
And the method realizes indirect addressing to bootstrap memory with the boot in data buffer storage to bootstrap memory transmission and according to the address in memory address register.
17. according to claim 10 to the described method of any one in 16, it is characterized in that, bootstrap memory is SPI Flash.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310077356.0A CN103150224B (en) | 2013-03-11 | 2013-03-11 | For improving the electronic equipment and method that start reliability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310077356.0A CN103150224B (en) | 2013-03-11 | 2013-03-11 | For improving the electronic equipment and method that start reliability |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103150224A true CN103150224A (en) | 2013-06-12 |
| CN103150224B CN103150224B (en) | 2015-11-11 |
Family
ID=48548322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310077356.0A Active CN103150224B (en) | 2013-03-11 | 2013-03-11 | For improving the electronic equipment and method that start reliability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103150224B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105279046A (en) * | 2015-11-04 | 2016-01-27 | 研华科技(中国)有限公司 | Method for improving reliability of embedded system |
| CN105388886A (en) * | 2015-11-20 | 2016-03-09 | 康泰医学系统（秦皇岛）股份有限公司 | Instrument single-chip microcomputer work monitoring circuit and method |
| CN105867891A (en) * | 2015-09-22 | 2016-08-17 | 乐视致新电子科技（天津）有限公司 | Guide loading device and method, electronic equipment and mainboard replacement method thereof |
| CN109918135A (en) * | 2019-02-21 | 2019-06-21 | 新华三技术有限公司 | Logical code restoration methods and electronic equipment in a kind of CPLD |
| CN111694303A (en) * | 2020-05-28 | 2020-09-22 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA reliable loading method based on CPLD |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525353A (en) * | 2003-09-17 | 2004-09-01 | 中兴通讯股份有限公司 | Multiprocessor system and method for sharing bootstrap module thereof |
| CN1553338A (en) * | 2003-06-08 | 2004-12-08 | 华为技术有限公司 | Starting method and system of central processing unit |
| CN101236515A (en) * | 2007-01-31 | 2008-08-06 | 迈普（四川）通信技术有限公司 | Multi-core system single-core abnormity restoration method |
| US20090119467A1 (en) * | 2007-11-02 | 2009-05-07 | Hironori Emaru | Storage system and storage subsystem |
| US20090307526A1 (en) * | 2007-03-12 | 2009-12-10 | Fujitsu Limited | Multi-cpu failure detection/recovery system and method for the same |
-
2013
- 2013-03-11 CN CN201310077356.0A patent/CN103150224B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1553338A (en) * | 2003-06-08 | 2004-12-08 | 华为技术有限公司 | Starting method and system of central processing unit |
| CN1525353A (en) * | 2003-09-17 | 2004-09-01 | 中兴通讯股份有限公司 | Multiprocessor system and method for sharing bootstrap module thereof |
| CN101236515A (en) * | 2007-01-31 | 2008-08-06 | 迈普（四川）通信技术有限公司 | Multi-core system single-core abnormity restoration method |
| US20090307526A1 (en) * | 2007-03-12 | 2009-12-10 | Fujitsu Limited | Multi-cpu failure detection/recovery system and method for the same |
| US20090119467A1 (en) * | 2007-11-02 | 2009-05-07 | Hironori Emaru | Storage system and storage subsystem |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105867891A (en) * | 2015-09-22 | 2016-08-17 | 乐视致新电子科技（天津）有限公司 | Guide loading device and method, electronic equipment and mainboard replacement method thereof |
| CN105279046A (en) * | 2015-11-04 | 2016-01-27 | 研华科技(中国)有限公司 | Method for improving reliability of embedded system |
| CN105388886A (en) * | 2015-11-20 | 2016-03-09 | 康泰医学系统（秦皇岛）股份有限公司 | Instrument single-chip microcomputer work monitoring circuit and method |
| CN109918135A (en) * | 2019-02-21 | 2019-06-21 | 新华三技术有限公司 | Logical code restoration methods and electronic equipment in a kind of CPLD |
| CN111694303A (en) * | 2020-05-28 | 2020-09-22 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA reliable loading method based on CPLD |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103150224B (en) | 2015-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10901898B2 (en) | Cost-effective solid state disk data-protection method for power outages | |
| US8949502B2 (en) | PCIe NVRAM card based on NVDIMM | |
| US7124244B2 (en) | Storage system and a method of speeding up writing data into the storage system | |
| CN100459447C (en) | Method for realizing master and spare conversion of distributing connection equipment | |
| EP2608049B1 (en) | Control system and relay apparatus | |
| CN103150224A (en) | Electronic equipment and method for improving starting reliability | |
| CN101329632A (en) | Method and apparatus for starting CPU by BOOT | |
| RU2614569C2 (en) | Rack with automatic recovery function and method of automatic recovery for this rack | |
| US20200035299A1 (en) | Method and system for power loss protection | |
| US20200064895A1 (en) | Power supply apparatus, backup power module and method for providing backup power in computing systems | |
| JP2018116648A (en) | Information processor, control method thereof and program | |
| US20100185896A1 (en) | Method and apparatus for fully redundant control of low-speed peripherals | |
| CN101813898B (en) | Image processing apparatus | |
| CN102081526B (en) | Basic input/output system architecture | |
| CN102770851A (en) | Restoring stability to an unstable bus | |
| US11301145B2 (en) | Storage device providing disconnection from host without loss of data | |
| CN102841634A (en) | Server mainboard | |
| JP2008009794A (en) | Programmable electronic controller, and communication control method for programmable electronic apparatus | |
| CN110688263A (en) | FPGA-based hard disk automatic switching device and application method | |
| CN113704023B (en) | Firmware self-recovery device, method and server system | |
| CN111414322B (en) | Method, system, equipment and storage medium for adapting Nand flash interface working protocol | |
| JP2011154593A (en) | Memory device and self-check control method thereof | |
| US20240220385A1 (en) | Power source consumption management apparatus for four-way server | |
| JPS5917467B2 (en) | Control computer backup method | |
| JP2020194425A (en) | Control device and monitoring method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: NEW H3C TECHNOLOGIES Co.,Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: HANGZHOU H3C TECHNOLOGIES Co.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230620 Address after: 310052 11th Floor, 466 Changhe Road, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: H3C INFORMATION TECHNOLOGY Co.,Ltd. Address before: 310052 Changhe Road, Binjiang District, Hangzhou, Zhejiang Province, No. 466 Patentee before: NEW H3C TECHNOLOGIES Co.,Ltd. |
|
| TR01 | Transfer of patent right |