CN1553338A - Starting method and system of central processing unit - Google Patents
Starting method and system of central processing unit Download PDFInfo
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- CN1553338A CN1553338A CNA03137543XA CN03137543A CN1553338A CN 1553338 A CN1553338 A CN 1553338A CN A03137543X A CNA03137543X A CN A03137543XA CN 03137543 A CN03137543 A CN 03137543A CN 1553338 A CN1553338 A CN 1553338A
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Abstract
In the present invention, bootstrap program for each CPU is stored in the same flash component in CPU system and data/address bus between each CPU and flash is isolated by buffer, gate of each CPU to corresponding buffer and flash is controlled by main CPU to let each CPU carry out access early or late according to sequence to fetch data from corresponding region of flash so start up of each CPU can be realized.
Description
Technical field
The present invention relates to electric numerical data and handle, relate in particular to the method and system that a kind of CPU (central processing unit) (CPU) starts.
Background technology
CPU (central processing unit) (CPU) starts now all independent start-up system, particularly in multi-CPU system, each CPU is started by startup chip (BOOTROM) separately, the number of devices that such design is used is many, and be difficult for realizing the BOOTROM software upgrading, cause the difficulty of system maintenance and enhancement function.
As shown in Figure 1, in the prior art scheme, each cpu system (as CPU1 system among the figure and CPU2 system) all has independently BOOTROM, and system can only start from the BOOTROM of this CPU correspondence.Since in the total system, usually only based on certain CPU, other CPU assist process business, only simply communicate by letter between each CPU, in order to reduce cost, generally only realize the BOOTROM upgrading of host CPU, and each BOOTROM from CPU does not upgrade in the system design.If realize the upgrading of all BOOTROM, then need to be each BOOTROM design loaded circuit, the system design complexity increases, and cost rises.
The shortcoming of prior art scheme is:
(1) in multi-CPU system, each cpu access needs to use a plurality of BOOTROM storeies by independently BOOTROM guiding startup separately in the system, increased system cost.
When (2) system need upgrade the software of all CPU,, only realize the upgrading of host CPU, do not upgrade from CPU for reducing cost.
(3) realize needing to increase system complexity, increase system cost from the CPU upgrading.
Summary of the invention
Technical matters to be solved by this invention is: overcome each CPU of prior art and start shortcomings such as the cost height that brought, upgrading complexity by BOOTROM independently, the method and system that provides a kind of CPU to start, thereby reduction system cost, and the convenient upgrading that realizes CPU.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:
The method that this CPU (central processing unit) starts, it is characterized in that: it may further comprise the steps:
In many CPU (central processing unit) (CPU) system, utilize same storer to deposit the boot of each CPU, the data/address bus between each CPU and this storer is isolated by impact damper (buffer) respectively;
Host CPU is controlled the gating of each CPU to corresponding buffer and storer, and each CPU is successively conducted interviews to storer in order, and the respective regions reading of data from storer realizes the startup of each cpu system.
The boot of described a plurality of CPU leaves different space according to the address division with application software in same flash.
It is as follows that cpu system starts flow process:
1) power on or after total system resets, host CPU makes respectively and to be in reset mode and can't to start from CPU that host CPU provides chip selection signal gating buffer corresponding with host CPU and flash, normal startup;
2) host CPU start finish or start to certain step after, remove from the resetting of CPU, and adjust the control signal of CPU output, make and can visit flash from CPU;
3) providing the chip selection signal gating from CPU should be from the buffer and the flash of CPU correspondence, the normal startup.
From CPU normally start or start to do not need flash after, host CPU is by adjusting the control signal of its output, cancellation should prevent to visit flash from the CPU mistake from the authority of the buffer of CPU correspondence from the CPU gating.
The described information that normally starts from CPU obtains by the communication port between the CPU, also can estimate the regular hour, guarantees that this normally starts or started to the stage that does not need flash from CPU.
At each CPU normal operation period, if need visit flash, must file an application to host CPU by the communication port between the CPU from CPU, after obtaining allowing, host CPU is adjusted the control signal of its output, makes this can read flash by gating from CPU; Read the back notice host CPU that finishes, host CPU is adjusted the control signal of its output, cancels this reads flash from the CPU gating authority.
If the space of flash is bigger, when the address realm of some CPU is not enough, according to this CPU program storage addresses in flash, do the upper and lower processing of drawing before buffer, for corresponding flash address wire, it is become required fixed level from external forced, make this CPU can have access to the flash space of distribution.
With above-mentioned CPU (central processing unit) startup method corresponding C PU start-up system, it is characterized in that:
The data/address bus of master and slave CPU is connected to same reservoir after isolating by impact damper (buffer) respectively;
The chip selection signal of host CPU is directly inputted to the enable signal pin of the buffer corresponding with host CPU, simultaneously this chip selection signal with respectively from the chip selection signal of CPU and back input reservoir, the gating of control reservoir;
From the chip selection signal of CPU with the chip selection signal of described host CPU with before, draw high by pull-up resistor, and isolated from the corresponding buffer of CPU with this;
The host CPU reset signal outputs to respectively the reseting pin from CPU after pull down resistor drags down, simultaneously, this reset signal is after carrying out inverse, carry out exclusive disjunction with the control signal of the host CPU drawn high through pull-up resistor output and from the chip selection signal of CPU, the signal that is produced is imported this enable signal pin from the buffer of CPU correspondence.
Described reservoir is flash memory (flash) device.
Described flash device is the flash device with block protection function.
Can link to each other by communication port between the master and slave CPU and carry out communication.
The data/address bus of each CPU also connects synchronous dynamic random access memory (sdram) or other memory device respectively.
Beneficial effect of the present invention is: the present invention uses flash to place boot and the application software of each CPU in multi-CPU system, the shared flash of all CPU, start from same flash, for starting from different BOOTROM, prior art provides cost savings, because each CPU can visit flash, can realize easily the software of all CPU is upgraded.
Description of drawings
Fig. 1 starts principle schematic for existing C PU;
Fig. 2 starts principle schematic for CPU of the present invention;
The control circuit figure that Fig. 3 starts from same flash for a plurality of CPU of the present invention;
Fig. 4 starts process flow diagram for CPU of the present invention;
Fig. 5 is cpu address line scope of the present invention processing synoptic diagram when not enough.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
Be illustrated in figure 2 as CPU of the present invention and start principle schematic, the present invention uses read-write storer (as the flash flush memory device) as carrier, replace existing startup chip (bootrom), use the flash device to deposit CPU software, the shared same flash of all CPU starts from same flash.The time of bootrom is very short because CPU reads when starting, and program does not visit again bootrom after being transported to synchronous dynamic random access memory (sdram), so can control each cpu system to bootrom visit successively in order by host CPU, reaches shared purpose.Prevent to disturb for preventing that each CPU from arbitrarily choosing logical flash and isolating each bus, data/address bus between each cpu system and the flash, and some or all chip selection signals isolate by impact damper (buffer), (CPU1 among the figure) controls each buffer by host CPU, realizes the priority visit of each CPU to flash.Simultaneously host CPU can be when normal operation gating flash, the upgrading of carrying out each CPU software loads.
As shown in Figure 3, be that example illustrates technical scheme of the present invention with two cpu systems, CPU1 is a host CPU among the figure, CPU2 is from CPU.The digital address bus interface (date_addr_bus) of CPU1, CPU2 is joined with the digital address bus interface (date_addr_bus) of same flash after the isolation of buffer1, buffer2 respectively.Respectively during gating, corresponding C PU can visit flash at buffer and flash, from the respective regions reading of data of flash with carry out data and be transported to corresponding SDRAM, thereby starts.
Among Fig. 3, impact damper buffer1 and buffer2 /the G pin is the switching gate signal, and is effectively low.When this pin was high, the data/address bus of corresponding C PU and flash was isolated; When this pin was low, the data/address bus of corresponding C PU and flash was communicated with.
Communication port between each CPU can be different in different systems, can be serial ports such as RS232, RS485, I2C; Also can be other interfaces, as universal test and operation-interface (UTOPIA) etc.; Also can be self-defining communication interface.
Chip selection signal/CS1 of CPU1 directly imports buffer1's/the G pin, simultaneously/and CS1 forming gating signal/CS3 of flash with chip selection signal/CS2 of CPU2 and (and) back.
Chip selection signal/CS2 of CPU2 do give flash with computing before, isolate gating flash when preventing that CPU2 from not obtaining the flash control by buffer2.During the pull-up resistor of/cs2_buf guarantees to power on and buffer2 when isolating, this signal is a high state, can not falsely drop logical flash.
Reset output signal/reset_out of CPU1 links reseting pin/reset of CPU2, the reset mode of control CPU2.If have a plurality ofly from CPU, each needs a reset signal that links to each other with host CPU from CPU for each, can not be shared, and reset signal is low effective.
The contro signal of CPU1 earlier and/reset_out non-(not) carry out exclusive disjunction (or) back and produce signal CPU1_ctr, again CPU1-ctr and/cs2 are carried out output CPU2_OE signal behind the exclusive disjunction to buffer2 /the G pin, CPU2_OE is as the break-make of enable signal control buffer2, prevent the random gating buffer2 of CPU2, visit flash.Owing to drawing on the pull-up resistor, the control signal is high, does not allow CPU2 gating buffer2 at ordinary times.When allowing CPU2 gating buffer2, the control signal is low.The control signal was a high state during pull-up resistor guaranteed to power on.
Like this, when system start-up, the start-up course of each CPU following (control signal of supposing following device all is effectively low):
After back or the total system of powering on resetted, CPU1 is normal earlier to be started, CPU1 /reset_out pin output low level, make resetting of CPU2 be input as that low (this pin is dragged down simultaneously, guarantee that the CPU1 initial start stage also can be low level), CPU2 is in reset mode, can't start; Simultaneously/reset_out is through making behind the not sum exclusive disjunction that CPU2_OE is high, closes buffer2.CPU1 normally starts, provide/the CS1 low signal, / CS1 input buffer1 /G pin gating buffer1, simultaneously/CS1 and/CS2_buf with produce low signal/CS3 and send into flash, choose logical flash, obtain the access limit of flash, from the respective regions reading of data of flash with carry out data and be transported to SDRAM.
CPU1 starts and to finish or start to (according to the actual conditions decision) after certain step, / reset_out pin is drawn high, and makes CPU2 walk out reset mode, the normal startup, the control signal remains low level simultaneously, makes CPU2 can control the gating of buffer2.CPU2 normally starts, and provides/the CS2 low signal, and the signal of input/G pin is low, and buffer2 gating, output/CS2_buf are low, thereby gating flash obtains the access limit of fash, from the respective regions reading of data of flash with carry out data and be transported to SDRAM.
Between the starting period, CPU1 must guarantee not visit flash, to avoid conflict at CPU2.CPU2 starts the information that finishes and can obtain by the communication port between the CPU, also can estimate the regular hour, guarantee that CPU2 normally starts or started to stage of not needing flash that (CPU is very short usually from the time that flash starts, can finish basic startup within several seconds, no longer need reading of data) from flash.After guaranteeing that CPU2 no longer needs flash, the control pin of CPU1 is drawn high, and the authority of cancellation CPU2 gating buffer2 prevents that two CPU from visiting flash simultaneously, causes conflict, damages device.
At normal operation period, if CPU2 need visit flash, must file an application by the communication port between the CPU, obtain allowing the control pin of back while CPU1 to drag down, CPU2 can read flash by gating.Read the back notice CPU1 that finishes, the control pin of CPU1 is drawn high, the authority of cancellation CPU2 gating buffer2.If normal operation period CPU2 does not need to visit flash, there is not this operation.
Only having provided three chip selection signal :/cs1 among Fig. 3 is the chip selection signal (output) that host CPU is given flash, and/cs2 is a chip selection signal (output) of giving flash from CPU, and/cs3 is the gating signal (input) of flash.
When from CPU not only during one of CPU2, equally according to control ,/reset_out and the chip selection signal that provides from CPU as enable signal import corresponding buffer /the G pin controls the break-make of this buffer, and by this chip selection signal and host CPU chip selection signal that provides and the break-make of controlling flash that provides from CPU, thereby realize that this is from the visit of CPU to flash.For the sake of security, the control signal that also can increase host CPU is controlled accordingly from CPU, reaches host CPU and can control each buffer break-make from CPU separately.
Be illustrated in figure 4 as CPU of the present invention and start process flow diagram, start flow process and be summarized as follows:
1) power on or after total system resets, host CPU makes respectively and to be in reset mode and can't to start from CPU that host CPU provides buffer and the flash between chip selection signal gating host CPU and the flash, the normal startup;
2) host CPU start finish or start to certain step after, remove from the resetting of CPU, and the control signal dragged down, feasiblely can visit flash from CPU;
3) providing the chip selection signal gating from CPU should be from buffer and flash between CPU and the flash, the normal startup, and host CPU can not be visited flash during this period;
4) guarantee not visit again flash from CPU after, host CPU is drawn high the control signal, prevents to visit flash from the CPU mistake;
5) host CPU and finish other start-up operation from CPU;
6) host CPU and normally move from CPU.
Flash space in the native system will be divided, and divides enough address spaces for each CPU, places software and other information.Because each CPU can visit flash, can realize each software of on-line loaded very easily, the software of each CPU that upgrades.
If the space of flash is bigger, when the address realm of some CPU is not enough, can adopt and do the upper and lower processing of drawing before buffer, for high-order flash address wire, by upper and lower draw processing after, force into required fixed level from the outside with the address wire of a high position, make this CPU can have access to the flash space of distribution.As shown in Figure 5, when the cpu address line is A0-A18, totally 19, and the flash address wire is A0-A20, totally 21 the time, part adopts the upper and lower processing of drawing in Fig. 4 circle, according to this CPU address stored in flash, before buffer, A19 is forced to low level, A20 is forced to high level, thereby when the buffer gating, this CPU can have access to the flash space (the 512k allocation of space of 0x100000-0x17FFFF is given and should be used from CPU) of distribution.
If the data live width of some CPU is not enough, be the data line of 16bit such as flash, and when CPU1 was 8 data line, then this CPU can only visit the flash space of 8 correspondences.
The present invention provides cost savings, and has reduced system complexity, can realize very easily the software of all CPU is upgraded simultaneously, can both upgrade software as long as can visit the CPU of flash device.The institute that common host CPU can be visited the flash device has living space, and it can determine the rights of using of flash device simultaneously, comes the fairly simple convenience of upgrade software by it.It should be noted that optional usefulness has the flash device of block protection function, thereby can prevent maloperation making the bios software space of each CPU be in guard mode at ordinary times because Basic Input or Output System (BIOS) (BIOS) software section software is important.
Claims (11)
1, a kind of method of CPU (central processing unit) startup, it is characterized in that: it may further comprise the steps:
In many CPU (central processing unit) (CPU) system, utilize same storer to deposit the boot of each CPU, the data/address bus between each CPU and this storer is isolated by impact damper (buffer) respectively;
Host CPU is controlled the gating of each CPU to corresponding buffer and storer, and each CPU is successively conducted interviews to storer in order, and the respective regions reading of data from storer realizes the startup of each cpu system.
2, the method for CPU (central processing unit) startup according to claim 1 is characterized in that: the boot of described a plurality of CPU leaves different space according to the address division with application software in same flash.
3, the method for CPU (central processing unit) startup according to claim 2, it is characterized in that: it is as follows that cpu system starts flow process:
1) power on or after total system resets, host CPU makes respectively and to be in reset mode and can't to start from CPU that host CPU provides chip selection signal gating buffer corresponding with host CPU and flash, normal startup;
2) host CPU start finish or start to certain step after, remove from the resetting of CPU, and adjust the control signal of CPU output, make and can visit flash from CPU;
3) providing the chip selection signal gating from CPU should be from the buffer and the flash of CPU correspondence, the normal startup.
4, the method for CPU (central processing unit) startup according to claim 3, it is characterized in that: from CPU normally start or start to do not need flash after, host CPU is by adjusting the control signal of its output, cancellation is somebody's turn to do from the authority of the buffer of CPU correspondence from the CPU gating, prevents to visit flash from the CPU mistake.
5, the method for CPU (central processing unit) startup according to claim 4, it is characterized in that: the described information that normally starts from CPU obtains by the communication port between the CPU, also can estimate the regular hour, guarantee that this normally starts or started to the stage that does not need flash from CPU.
6, the method for CPU (central processing unit) startup according to claim 3, it is characterized in that: at each CPU normal operation period, if need visit flash from CPU, must file an application to host CPU by the communication port between the CPU, after obtaining allowing, host CPU is adjusted the control signal of its output, makes this can read flash by gating from CPU; Read the back notice host CPU that finishes, host CPU is adjusted the control signal of its output, cancels this reads flash from the CPU gating authority.
7, the method for CPU (central processing unit) startup according to claim 3, it is characterized in that: if the space of flash is bigger, when the address realm of some CPU is not enough, according to this CPU program storage addresses in flash, do the upper and lower processing of drawing before buffer, for high-order flash address wire, it is become required fixed level from external forced, make this CPU can have access to the flash space of distribution.
8, a kind of CPU (central processing unit) start-up system is characterized in that:
The data/address bus of master and slave CPU is connected to same reservoir after isolating by impact damper (buffer) respectively;
The chip selection signal of host CPU is directly inputted to the enable signal pin of the buffer corresponding with host CPU, simultaneously this chip selection signal with respectively from the chip selection signal of CPU and back input reservoir, the gating of control reservoir;
From the chip selection signal of CPU with the chip selection signal of described host CPU with before, draw high by pull-up resistor, and isolated from the corresponding buffer of CPU with this;
The host CPU reset signal outputs to respectively the reseting pin from CPU after pull down resistor drags down, simultaneously, this reset signal is after carrying out inverse, carry out exclusive disjunction with the control signal of the host CPU drawn high through pull-up resistor output and from the chip selection signal of CPU, the signal that is produced is imported this enable signal pin from the buffer of CPU correspondence.
9, CPU (central processing unit) start-up system according to claim 8 is characterized in that: described reservoir is flash memory (flash) device, and described flash device is the flash device with block protection function.
10, according to Claim 8 or 9 described CPU (central processing unit) start-up systems, it is characterized in that: can link to each other by communication port between the master and slave CPU and carry out communication.
11, according to Claim 8 or 9 described CPU (central processing unit) start-up systems, it is characterized in that: the data/address bus of each CPU also connects synchronous dynamic random access memory (sdram) or other memory device respectively.
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| CNB03137543XA CN1296830C (en) | 2003-06-08 | 2003-06-08 | Starting method and system of central processing unit |
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| CNB03137543XA CN1296830C (en) | 2003-06-08 | 2003-06-08 | Starting method and system of central processing unit |
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| CN100373365C (en) * | 2005-10-14 | 2008-03-05 | 威盛电子股份有限公司 | Bus assembly initialization method |
| CN101222373B (en) * | 2008-01-29 | 2010-07-28 | 杭州华三通信技术有限公司 | Multi-master control system and master control board starting method thereof |
| US7900028B2 (en) | 2005-10-07 | 2011-03-01 | Via Technologies, Inc. | Method for initializing bus device |
| CN102520778A (en) * | 2011-12-09 | 2012-06-27 | 山东大学 | One-key reset method suitable for embedded Linux operating system |
| CN102647280A (en) * | 2012-02-28 | 2012-08-22 | 山东大学 | Embedded Internet connection device for community information system and realization method of embedded Internet connection device |
| CN103150224A (en) * | 2013-03-11 | 2013-06-12 | 杭州华三通信技术有限公司 | Electronic equipment and method for improving starting reliability |
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| CN104834535A (en) * | 2014-02-07 | 2015-08-12 | 昆达电脑科技(昆山)有限公司 | SOC (System On Chip) chip system and power on method thereof |
| WO2016033941A1 (en) * | 2014-09-05 | 2016-03-10 | 中兴通讯股份有限公司 | Boot on-line upgrading apparatus and method |
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| US5497497A (en) * | 1989-11-03 | 1996-03-05 | Compaq Computer Corp. | Method and apparatus for resetting multiple processors using a common ROM |
| CA2069972A1 (en) * | 1991-08-30 | 1993-03-01 | Brigitte R. Rapatz | Power-up and initialization of a multiprocessor system |
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| CN100373365C (en) * | 2005-10-14 | 2008-03-05 | 威盛电子股份有限公司 | Bus assembly initialization method |
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| CN102520778A (en) * | 2011-12-09 | 2012-06-27 | 山东大学 | One-key reset method suitable for embedded Linux operating system |
| CN102647280A (en) * | 2012-02-28 | 2012-08-22 | 山东大学 | Embedded Internet connection device for community information system and realization method of embedded Internet connection device |
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