JPS5852343B2 - Handout Taisouchino Seizouhouhou - Google Patents

Handout Taisouchino Seizouhouhou

Info

Publication number
JPS5852343B2
JPS5852343B2 JP3110675A JP3110675A JPS5852343B2 JP S5852343 B2 JPS5852343 B2 JP S5852343B2 JP 3110675 A JP3110675 A JP 3110675A JP 3110675 A JP3110675 A JP 3110675A JP S5852343 B2 JPS5852343 B2 JP S5852343B2
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
lead frame
view
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3110675A
Other languages
Japanese (ja)
Other versions
JPS51107069A (en
Inventor
和彦 山田
基裕 小西
利一 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP3110675A priority Critical patent/JPS5852343B2/en
Publication of JPS51107069A publication Critical patent/JPS51107069A/en
Publication of JPS5852343B2 publication Critical patent/JPS5852343B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法にカへり、特にリード
フレームより形成されたリードを用いて半導体装置を製
造するにあたり、このリードと半導体素子との接続を容
易かつ確実ならしめる手段を含む半導体装置の製造方法
を提供することを目的とするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly, when manufacturing a semiconductor device using leads formed from a lead frame, it is possible to easily and reliably connect the leads to a semiconductor element. It is an object of the present invention to provide a method for manufacturing a semiconductor device including a means for tightening the semiconductor device.

従来の半導体装置の製造方法につき図面を参照して以下
に工程順fこ説明する。
The process order of a conventional method for manufacturing a semiconductor device will be explained below with reference to the drawings.

第1工程二 第1図aに上面図で、また同図すに側面図で一部を示す
リードフレーム1を用意する。
1st Step 2 A lead frame 1 is prepared, which is shown in a top view in FIG. 1a and partially shown in a side view in the same figure.

このリードフレームは橋絡支持部1aから突出したイン
ナリード1b、lc、1dがあり、このうちインナリー
ド1bとインナリード1dとは先端部が連接してなる。
This lead frame has inner leads 1b, lc, and 1d protruding from a bridging support portion 1a, and among these, the inner leads 1b and 1d have their tip ends connected to each other.

インナリード1cは第1図Cに示す如く、のちに半導体
素子2の支持体3に、また前記インナリード1bおよび
インナリード1dは夫々の先端部で(切截後に)半導体
素子の電極に接続する如くなる。
As shown in FIG. 1C, the inner lead 1c will later be connected to the support 3 of the semiconductor element 2, and the inner leads 1b and 1d will be connected to the electrodes of the semiconductor element at their respective tips (after cutting). It becomes like this.

前記接続を容易にするために予め打点を施した部位に一
例としてはんだ層を被着する。
In order to facilitate the connection, a solder layer is applied, for example, to the area where dots have been made in advance.

この被着は該部を低融点はんだ層に浸漬することによっ
て達成される。
This attachment is accomplished by dipping the part into a layer of low melting point solder.

第2工程: 第2図a ”’−cに示す如く、リードフレ1ムのイン
ナリード1bとインナリード1dとの先端部の連接部分
に切截を施して夫々に端部を形成する。
Second step: As shown in FIG. 2a''-c, the connecting portions of the tips of the inner leads 1b and 1d of the lead frame 1 are cut to form respective ends.

またインナリード10は半導体素子の支持体3に接続す
るための折曲加工を施す。
Further, the inner lead 10 is bent in order to be connected to the support 3 of the semiconductor element.

図における1eはインナリード1bの上記加工による切
截面を示し、リードフレームの材質、一例として銅また
は銅合金(板の表面にニッケルメッキを施しである)が
露出した状態である。
1e in the figure shows the cut surface of the inner lead 1b obtained by the above processing, and the material of the lead frame, for example, copper or copper alloy (the surface of the plate is nickel plated) is exposed.

第3王程: 第3図に示す如く半導体素子2(下面はコレクク電極の
ハンダ膜が、上面にはベース電極およびエミッタ電極が
形成されている)をガイドにより支持体3上にて所定の
位置ぎめをなし、インナリード1cと支持体3とが機械
的にかしめられ、同時にベース、エミッタのインナリー
ドの先端が半導体素子上面のはんだ電極4にそれぞれ接
触される。
Third step: As shown in Fig. 3, the semiconductor element 2 (the solder film of the collector electrode is formed on the bottom surface, and the base electrode and the emitter electrode are formed on the top surface) is placed at a predetermined position on the support 3 by a guide. The inner leads 1c and the support body 3 are mechanically caulked, and at the same time, the tips of the base and emitter inner leads are respectively brought into contact with the solder electrodes 4 on the upper surface of the semiconductor element.

第4王程: 第3工程の後に還元性雰囲気(たとえば水素炉)中で約
3600〜400℃に加熱することにより半導体素子は
下向のコレクタ電極のはんだで支持体に固着すると同時
に上面のベース電極、エミッタ電極はこれらに設けられ
たはんだ4(第3図)が融けて夫々が接続されるインナ
リードの先端と接続される。
Fourth Process: After the third step, the semiconductor element is fixed to the support by the solder of the downward collector electrode by heating to about 3600 to 400°C in a reducing atmosphere (for example, in a hydrogen furnace), and at the same time the semiconductor element is fixed to the support by the solder of the downward collector electrode. The electrodes and emitter electrodes are connected to the tips of the inner leads to which they are connected by melting the solder 4 (FIG. 3) provided thereon.

このとき、第4図すに示す如くインナリード1bの切截
面1eはたとえば銅または銅合金のため、他のあらかじ
めはんだ浸漬して表面にはんだ膜を形成した(図におい
て打点を施して示した)部位に比してはんだのなじみが
悪く、電極のけんだ4に融着しないで融けたはんだ4か
ら切截面1eが露出する。
At this time, as shown in FIG. 4, since the cut surface 1e of the inner lead 1b is made of copper or a copper alloy, it is pre-dipped in another solder to form a solder film on the surface (indicated by dots in the figure). The solder does not adhere well to the solder portion 4 of the electrode, and the cut surface 1e is exposed from the melted solder 4 without being fused to the solder portion 4 of the electrode.

第5工程: 上記第4工程の次に化学的にたとえばエツチングの手段
により半導体素子表面を清浄化したのち素子保護用レジ
ン5を塗布、乾燥して第5図に示す如くなる。
Fifth step: After the fourth step, the surface of the semiconductor element is chemically cleaned by, for example, etching, and then a resin 5 for protecting the element is applied and dried, resulting in the result as shown in FIG.

第6エ程: 次に一例としてシリコン樹脂6間の如きを用いてモール
ド封止を行ない第6図aに示す如くなる。
Sixth step: Next, as an example, mold sealing is performed using silicone resin 6, etc., as shown in FIG. 6a.

さらにリードフレームの橋絡支持部1aに切截を施して
第6図すに示す如き個々の半導体装置とする。
Furthermore, the bridging support portion 1a of the lead frame is cut to form individual semiconductor devices as shown in FIG.

上記従来の半導体装置の製造方法によれば、リードフレ
ームのインナリードが半導体素子の電極との接続部に一
例のはんだの如き接続体となじみの悪い面(インナリー
ドの切截面)が生ずるために、接続が機械的、電気的に
不確実となりやすい。
According to the above-mentioned conventional semiconductor device manufacturing method, a surface (cut surface of the inner lead) that is not compatible with a connecting body such as solder, for example, is created at the connection part of the inner lead of the lead frame with the electrode of the semiconductor element. , connections tend to be mechanically and electrically unstable.

このため半導体装置の使用中のオープン不良(電極とこ
の電極の導出リードとの間の導接不良)を生じやすいと
いう重大な欠点がある。
For this reason, there is a serious drawback in that open defects (defects in conduction between an electrode and a lead of the electrode) are likely to occur during use of the semiconductor device.

とくに最近の半導体装置を用いた電子機器では特にオー
プン不良、ショート不良(電気的短絡)の如き重不良は
To 0000以下の要求がなされている。
In particular, recent electronic devices using semiconductor devices are required to have a To 0000 or less for serious defects such as open defects and short circuit defects (electrical short circuits).

樹脂封止型半導体装置にあっては樹脂、半導体素子、お
よび支持体の間に熱膨張係数差があるため、使用中の熱
ストレスにより長期使用中にオープン不良が多いことは
一般に知られており、この対策が強く要望されていた。
It is generally known that in resin-encapsulated semiconductor devices, open defects often occur during long-term use due to thermal stress during use due to differences in thermal expansion coefficients between the resin, semiconductor element, and support. , this measure was strongly requested.

本発明は上記従来の欠点を改良して要望に応えるために
なされたものである。
The present invention has been made in order to improve the above-mentioned conventional drawbacks and meet the demands.

即ち本発明ζこかSる半導体装置の製造方法は、少くと
もインナリードの複数が半導体素子の電極と接続予定の
端部を連接して形成されたリードフレームを用意し、前
記連接部(こ切截を施して半導体素子の電極または他の
部材と接続する端部を形成し、次にインナリードの前記
切截面に金属層およびまたはろう層を被着したのち、前
記インナリードの端部に上記予定された接続を施すこと
を特徴とするものである。
That is, in the method of manufacturing a semiconductor device according to the present invention, a lead frame is prepared in which at least a plurality of inner leads are formed by connecting end portions to be connected to electrodes of a semiconductor element, and the connecting portion (this connecting portion) is prepared. Cutting is performed to form an end portion to be connected to an electrode or other member of a semiconductor element, and then a metal layer and/or a brazing layer is applied to the cut surface of the inner lead. It is characterized by performing the above-mentioned scheduled connections.

以下に本発明にか5る半導体装置の製造方法の一実施例
につき図面を参照して前記従来の半導体装置の製造方法
との相違点を説明する。
Hereinafter, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings, and the differences from the conventional method for manufacturing a semiconductor device will be described.

第1工程: 第7図に示す如きリードフレームを用意する。First step: A lead frame as shown in FIG. 7 is prepared.

従来の半導体装置の製造方法における第1工程とははん
だ層被着を施さない点で異なる。
This step differs from the first step in the conventional semiconductor device manufacturing method in that a solder layer is not deposited.

即ち第7図aに上面図でまた同図すに側面図で示す如く
、リードフレーム11を用意する。
That is, the lead frame 11 is prepared as shown in a top view in FIG. 7a and in a side view in the same figure.

このリードフレームは橋絡支持部11aから突出したイ
ンナリード11b、11c、11dがあり、このうちイ
ンナリード11bとインナリード11dとは先端部が連
接してなる。
This lead frame has inner leads 11b, 11c, and 11d protruding from the bridging support portion 11a, and among these, the inner leads 11b and 11d have their tip ends connected to each other.

インナリード11cは第7図Cに示す如く、のちに半導
体素子2の支持体3に、またインナリード11bおよび
インナリード11dは夫々の先端で(切截後に)半導体
素子の電極に接続する如くなる。
As shown in FIG. 7C, the inner lead 11c will later be connected to the support 3 of the semiconductor element 2, and the tips of the inner leads 11b and 11d will be connected to the electrodes of the semiconductor element (after cutting). .

第2工程: 第8図aに示す如く、リードフレームのインナリード1
1bとインナリード11aとの先端部の連接部分に切截
を施して夫々に端部を形成す赤る。
Second step: As shown in Figure 8a, the inner lead 1 of the lead frame
The connecting portions of the tips of 1b and inner lead 11a are cut to form respective ends.

またインナリードIlcは半導体素子の支持体3に接続
するための折曲加工を施す。
Further, the inner lead Ilc is bent in order to be connected to the support 3 of the semiconductor element.

第3王程: 上記第2工程の加工を施したリードフレームのインナリ
ードの先端部をたとえば低融点はんだ槽に浸漬して第9
図に打点図示した如くはんだ層を被着する。
Third step: The tip of the inner lead of the lead frame processed in the second step is immersed in, for example, a low melting point solder bath.
A solder layer is applied as indicated by dots in the figure.

この状態は従来方法の第2図Cに示すところと相似るも
、インナリード先端の切截面11e、11fにはんだ被
着のある点で異なる。
This state is similar to the conventional method shown in FIG. 2C, but differs in that the cut surfaces 11e and 11f of the inner lead tip are coated with solder.

第4工程: 第10図に示す如く半導体素子2(下面はコレクタ電極
のはんだ膜が、上面にはベース電極およびエミッタ電極
が形成されている)をガイドにより支持体3上にて所定
の位置ぎめをなし、インナリード11cと支持体とが機
械的にかしめられ、同時に−ベース、エミッタのインナ
リードの先端が半導体素子上面のはんだ電極4にそれぞ
れ接触される。
Fourth step: As shown in FIG. 10, the semiconductor element 2 (the solder film of the collector electrode is formed on the bottom surface, and the base electrode and the emitter electrode are formed on the top surface) is placed in a predetermined position on the support 3 by a guide. Then, the inner lead 11c and the support are mechanically caulked, and at the same time, the tips of the base and emitter inner leads are brought into contact with the solder electrodes 4 on the upper surface of the semiconductor element, respectively.

第5程: 第3工程の後に還元性雰囲気(たとえば水素炉)中で約
3600〜400℃に加熱することにより半導体素子は
下面のコレクタ電極のはんだで支持体に固着すると同時
に上面のベース電極エミッタ電極はこれらに設けられた
けんだ4(第10図つが融けて4“の如き形状となり、
第11図に示す如く夫々が接続されるインナリードの先
端と接続される。
Step 5: After the third step, the semiconductor element is fixed to the support by the solder of the collector electrode on the lower surface by heating to about 3600 to 400°C in a reducing atmosphere (for example, a hydrogen furnace), and at the same time the base electrode emitter on the upper surface is fixed to the support. The electrodes are formed by melting the solder 4 (see Figure 10) and forming a shape like 4"
As shown in FIG. 11, each is connected to the tip of the inner lead to which it is connected.

このときインナリードの前記切截面11e。11fには
はんだ被着があるので、インナリードの先端部側面のは
んだ層と完全一体となって強固な接続が達成される。
At this time, the cut surface 11e of the inner lead. Since 11f is coated with solder, it is completely integrated with the solder layer on the side surface of the tip of the inner lead to achieve a strong connection.

第6エ程および第7エ程: 従来の半導体装置の製造方法の第5工程および第6エ程
と異る点がないので記載を省略する。
Sixth Step and Seventh Step: Since there is no difference from the fifth step and sixth step of the conventional semiconductor device manufacturing method, the description will be omitted.

さらに本発明方法に関し、上記の他に次の如く行った。Furthermore, regarding the method of the present invention, the following was carried out in addition to the above.

即ち従来方法の第2工程と第3工程との間においてイン
ナリード先端部を低融点はんだ層に浸漬して核部に再度
はんだ層被着を施す。
That is, between the second and third steps of the conventional method, the tips of the inner leads are immersed in a low melting point solder layer, and the core portion is again coated with a solder layer.

これによってインナリードの切截面がはんだ層によって
被覆される。
As a result, the cut surfaces of the inner leads are covered with the solder layer.

本発明によればインナリードと半導体素子の電極または
他の部材との接続が機械的にも電気的にも確実なため、
半導体装置の使用中に従来上じやすかったオープン不良
、あるいはショート不良等が極減した。
According to the present invention, since the connection between the inner lead and the electrode or other member of the semiconductor element is reliable both mechanically and electrically,
Open defects, short circuit defects, etc., which were previously easy to occur during the use of semiconductor devices, have been significantly reduced.

この顕著な効果は次の試験を試みて従来方法によるもの
と明確な差異が認められた。
This remarkable effect was found to be clearly different from that achieved by conventional methods in the following tests.

半導体装置を一55℃の低温雰囲気中に12分間保持し
、次に+150℃の高温雰囲気中に12分間保持する。
The semiconductor device is held in a low temperature atmosphere of -55°C for 12 minutes, and then held in a high temperature atmosphere of +150°C for 12 minutes.

(但し温度移行時間は6分間とする)を1サイクルとし
て、これを繰返す。
(However, the temperature transition time is 6 minutes) as one cycle, and this is repeated.

下表の数値は100本につき発生不良数である。The numbers in the table below are the number of defects that occur per 100 pieces.

本発明の方法は次の如く行なっても良好な結果をみた。Good results were obtained using the method of the present invention as follows.

即ち第1王程: 上述の実施例の第1工程と同じ 第2王程: 上述の実施例の第2工程においてその後半のインナリー
ド11cの折曲加工を行なわない。
That is, the first rounding step: The second rounding step is the same as the first step of the above-described embodiment: In the second step of the above-described embodiment, the bending process of the inner lead 11c in the latter half is not performed.

第3工程: 上述の実施例の第3工程と同じ上記第3工程終了後にお
いてインナリード11cの折曲加工を施す第4工程以降
上述の実施例と同じ。
Third step: Same as the third step in the above embodiment. After the third step, the inner lead 11c is bent. The fourth step and the subsequent steps are the same as in the above embodiment.

またこの実施例による上述の実施例と同じ試験を施した
This example was also subjected to the same tests as in the previous example.

その結果は下記の如くで顕著な効果が認められた。The results are as follows, and remarkable effects were observed.

本発明方法によ る半導体装置 (キロサイクツ0 0.5 0 01
0 02
0 05
0 110
0 515
0 1420
0 51従来方法によ る半導体装置 なお本発明方法の上記実施例においてはインナリードの
先端部特に切截面にはんだ層を被着する手段を例示した
が、予めめっき等の手段により金属層(たとえばニッケ
ル)を被着形成しておき、次にろう層を重畳被着しても
よい。
Semiconductor device according to the method of the present invention (kilocycles 0 0.5 0 01
0 02
0 05
0 110
0 515
0 1420
0 51 Semiconductor device by conventional method Note that in the above embodiments of the method of the present invention, the method of applying a solder layer to the tip portion of the inner lead, particularly the cut surface, was exemplified, but a metal layer (for example, nickel) was previously applied by plating or other means. It is also possible to apply a solder layer in advance and then apply a solder layer in a superimposed manner.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第6図までは従来の半導体装置の製造方法を
工程順に説明するための図で、第1図はリードフレーム
のaは上面図、bは側面図、Cは組立後を示す断面図、
第2図aはリードフレームのaは上面図、bは側面図、
Cは斜視図、第3図は組立を示す側面図、第4図は組立
を示す図aは側面図、bは一部の斜視図、第5図は組立
を示す一部断面側面図、第6図は組立後を示す図aは一
部断面側面図、図すは斜視図である。 第7図から第11図は本発明の半導体装置の製造方法を
説明するためのもので、第1図はリードフレームのaは
上面図、bは側面図、Cは組立後を示す断面図、第8図
aはリードフレームのaは上面図、bは側面図、第9図
はリードフレームの斜視図、第10図は組立を示す一部
断面側面図、第11図は組立後を示す図aは一部断面側
面図、図すは斜視図である。 なお図中同一符号は同一または相当部分を夫々示すもの
とする。 3・・・・・・半導体素子の支持体(他の部材)、11
・・・・・リードフレーム、11a・・・・・・リード
フレームの橋絡支持部、11b、11c、11d・・・
・・・インナリード、 11e、11f・・・・・・イ
ンナリードの切截面。
Figures 1 to 6 are diagrams for explaining the conventional semiconductor device manufacturing method step by step. In Figure 1, a is a top view of the lead frame, b is a side view, and C is a cross section showing the lead frame after assembly. figure,
Figure 2 a is a top view of the lead frame, b is a side view,
C is a perspective view, FIG. 3 is a side view showing assembly, FIG. 4 is a side view showing assembly, b is a partial perspective view, FIG. 5 is a partially sectional side view showing assembly, Figure 6 shows the device after assembly, Figure a is a partially sectional side view, and Figure 6 is a perspective view. 7 to 11 are for explaining the method of manufacturing a semiconductor device according to the present invention, and in FIG. 1, a is a top view of the lead frame, b is a side view, and C is a sectional view after assembly; Fig. 8a is a top view of the lead frame, b is a side view, Fig. 9 is a perspective view of the lead frame, Fig. 10 is a partially sectional side view showing assembly, and Fig. 11 is a view after assembly. FIG. 1A is a partially sectional side view, and FIG. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 3...Semiconductor element support (other members), 11
...Lead frame, 11a...Bridging support portion of lead frame, 11b, 11c, 11d...
...Inner lead, 11e, 11f...Cut surface of inner lead.

Claims (1)

【特許請求の範囲】[Claims] 1 少くともインナリードの複数が半導体素子の電極と
の接続予定の端部を連接して形成されたリードフレーム
を用意する工程と、前記連接部に切截を施して半導体素
子の電極と接続する端部を形成する工程と、インナリー
ドの前記切截部に金属層を被着する工程と、前記インナ
リードの端部と前記半導体素子の電極とを接続すること
を特徴とする半導体装置の製造方法。
1. A step of preparing a lead frame in which at least a plurality of inner leads are formed by connecting the end portions to be connected to the electrodes of the semiconductor element, and cutting the connecting portions to connect them to the electrodes of the semiconductor element. Manufacturing a semiconductor device, comprising: forming an end portion; applying a metal layer to the cut portion of the inner lead; and connecting the end portion of the inner lead to an electrode of the semiconductor element. Method.
JP3110675A 1975-03-17 1975-03-17 Handout Taisouchino Seizouhouhou Expired JPS5852343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3110675A JPS5852343B2 (en) 1975-03-17 1975-03-17 Handout Taisouchino Seizouhouhou

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3110675A JPS5852343B2 (en) 1975-03-17 1975-03-17 Handout Taisouchino Seizouhouhou

Publications (2)

Publication Number Publication Date
JPS51107069A JPS51107069A (en) 1976-09-22
JPS5852343B2 true JPS5852343B2 (en) 1983-11-22

Family

ID=12322137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3110675A Expired JPS5852343B2 (en) 1975-03-17 1975-03-17 Handout Taisouchino Seizouhouhou

Country Status (1)

Country Link
JP (1) JPS5852343B2 (en)

Also Published As

Publication number Publication date
JPS51107069A (en) 1976-09-22

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