JPS5851555A - Semiconductor resistance unit - Google Patents
Semiconductor resistance unitInfo
- Publication number
- JPS5851555A JPS5851555A JP15113881A JP15113881A JPS5851555A JP S5851555 A JPS5851555 A JP S5851555A JP 15113881 A JP15113881 A JP 15113881A JP 15113881 A JP15113881 A JP 15113881A JP S5851555 A JPS5851555 A JP S5851555A
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistance
- regions
- semiconductor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Abstract
Description
【発明の詳細な説明】
本発明は高抵抗を必要とする集積回路等に利用できる半
導体抵抗装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor resistance device that can be used in integrated circuits and the like that require high resistance.
集積回路に内臓の従来の高抵抗は、以下の様な方法で形
成していた。即ち、■長さ方向の寸法を大きくする。■
低濃度の拡散領域を使う、■逆導電型の拡散を所望抵抗
領域の１部に行う。■半導体でない他の材料、例えば多
結晶シリコンを付着する。Conventional high resistors built into integrated circuits were formed using the following method. That is, (1) increase the dimension in the length direction; ■
Using a low-concentration diffusion region, 1. Diffusion of the opposite conductivity type is performed in a part of the desired resistance region. ■ Deposit other non-semiconductor materials, such as polycrystalline silicon.
（１） 従来構成のものには各々次のような欠点がある。(1) Each of the conventional configurations has the following drawbacks.
■抵抗のパターンが大きくなり、チップ面積が大きくな
る。■濃度の実なる抵抗は温度特性等が実なり、２ケ以
上の抵抗のベアー性が得られない。■The resistor pattern becomes larger and the chip area becomes larger. ■Resistance depends on concentration and temperature characteristics, etc., and it is not possible to obtain bare characteristics of two or more resistors.
■目標とする値が得にくり、製造ごとに値がバラつく。■It is difficult to obtain the target value, and the value varies depending on the production.
■他の材料不着の工程が必要で、しかも値とその温度特
性が一定でない。また、従来のものではいずれも設計パ
ターンなどを変えずに製造時にその処理条件を変えるよ
うにした場合には抵抗値を僅かしか変化させえないとい
う欠゛点があった。■Another material-free process is required, and the value and its temperature characteristics are not constant. Furthermore, all of the conventional products had the disadvantage that if the processing conditions were changed during manufacturing without changing the design pattern, the resistance value could only be slightly changed.
本発明は上記欠点に鑑み、離間した２ケ以上の抵抗形成
パターンを集積回路に形成し、その後の拡散によって集
積回路基板内に於て１ケの抵抗と成すように構成した半
導体抵抗装置であり、両パターンの離間部表面に窒化論
等を用いた選択酸化処理により絶縁膜を埋め込む構成と
し、両パターンはその下部において拡散によって接続さ
れることにより、高い抵抗値を有すると共に小さい面積
で高抵抗を形成できる半導体抵抗装置を得ることを目的
とする。In view of the above-mentioned drawbacks, the present invention is a semiconductor resistance device in which two or more resistor formation patterns spaced apart are formed on an integrated circuit, and then diffused to form one resistor within the integrated circuit board. , an insulating film is embedded in the surface of the separated part of both patterns by selective oxidation treatment using nitridation theory, etc., and both patterns are connected by diffusion at the bottom, so that they have a high resistance value and a small area. The object of the present invention is to obtain a semiconductor resistor device that can form a semiconductor resistor device.
（２）
以下、本発明の一実施例を図面を用いて説明する。第１
図（ａ）、（ｂ）は半導体抵抗装置の一例を示す平面図
ｉび断面図である。一般にこの半導体抵抗装置は半導体
基板内に単独に形成されるものではなく、トランジスタ
やダイオード等を含む集積回路内の一抵抗素子として形
成されるものである。半導体基板においてＰ型半導体領
域１の一部領域５の内に、Ｎ型半導体領域（抵抗形成領
域）２と３を距離Ｗだけ離して形成する。領域２のＡ点
と領域３０Ｂ点は配線中の電気接続点であり、Ａ点とＢ
点の間に所望抵抗値の抵抗を得ている。離間部４は第１
図（ｂ）に示すような公知のＬＯ，ＣＯ３構造、即ち一
般に窒化ケイ素膜を用いた選択酸化処理によって所定部
位に他の絶縁Ｍ６Ｂより厚い絶縁１１１６Ａを埋め込ん
だ構造としである。この絶縁１１１６Ａ、６Ｂは通常シ
リコン酸化膜である。(2) Hereinafter, one embodiment of the present invention will be described using the drawings. 1st
Figures (a) and (b) are a plan view and a cross-sectional view showing an example of a semiconductor resistance device. Generally, this semiconductor resistance device is not formed independently in a semiconductor substrate, but is formed as one resistance element in an integrated circuit including transistors, diodes, and the like. N-type semiconductor regions (resistance forming regions) 2 and 3 are formed at a distance W in a partial region 5 of a P-type semiconductor region 1 in a semiconductor substrate. Point A in area 2 and point B in area 30 are electrical connection points in the wiring;
The desired resistance value is obtained between the points. The separating part 4 is the first
This is a well-known LO, CO3 structure as shown in FIG. 3(b), that is, a structure in which an insulator 1116A, which is thicker than the other insulator M6B, is buried in a predetermined portion by selective oxidation treatment using a silicon nitride film. These insulators 1116A and 6B are usually silicon oxide films.
次に第１図（ａ）中の点Ｏから図示矢印方向への距離Ｘ
と、領域５の基板内に作られるＰとＮ両型半導体領域の
濃度の関係を第２図に示す。Ｎ。Next, distance X in the direction of the arrow shown from point O in Figure 1(a)
FIG. 2 shows the relationship between the concentration and the concentration of both P and N type semiconductor regions formed in the substrate in region 5. N.
（３）
は領域２と３の基板表面での濃度を表す。領域２と３は
拡散によって、形成今れ、拡散は基板内の全方位へ一進
行するから、第１図（ａ）中＋Ｘと−Ｘ方向へ進み、か
つその濃度が対数的に低下していく。従って領域２と３
からの拡散は、離間Ｗと低濃度のＮ型に変え、離間Ｗの
中間点で最低Ｎ型濃度Ｎ工となって、領域２と３を結合
する。この結果電気接続点であるＡ点とＢ点との間に１
ケの抵抗が形成され、その抵抗値は、Ｎ２の濃度の領域
２と３に、Ｎ２より熾かに低い濃度の領域Ｗが直列に加
わって、結局大きな抵抗値となる。このとき絶縁膜６Ａ
の厚みの効果により結合部は小さく形成され、高い抵抗
値の形成に寄与する。(3) represents the concentration at the substrate surface in regions 2 and 3. Regions 2 and 3 are formed by diffusion.Since diffusion advances in all directions within the substrate, it advances in the +X and -X directions in FIG. 1(a), and its concentration decreases logarithmically. go. Therefore areas 2 and 3
Diffusion from the distance W changes to a low concentration N-type, and at the midpoint of the distance W becomes the lowest N-type concentration N-type, joining regions 2 and 3. As a result, 1
2 resistors are formed, and the resistance value becomes large as a result of adding in series a region W having a concentration much lower than that of N2 to regions 2 and 3 having a concentration of N2. At this time, the insulating film 6A
Due to the thickness effect, the bonding portion is formed small, contributing to the formation of a high resistance value.
次に、第３図、第４図は他の実施例を示すものであり、
第３図では、抵抗形成領域２ａ、３ａを完全に離間せず
、その一部を接続状態にした（離間部４ａを設けて大き
な抵抗値を得るように構成している。また、離間部４ａ
の形状は図示のものに限らず凸形や斜め形など種々の形
状が適用できる。Next, FIGS. 3 and 4 show other embodiments,
In FIG. 3, the resistor formation regions 2a and 3a are not completely separated, but are partially connected (a spacing section 4a is provided to obtain a large resistance value.
The shape is not limited to the one shown in the drawings, and various shapes such as a convex shape and an oblique shape can be applied.
（４）
また、各領４２，３．５の導電型を逆にしてもよいし、
抵抗形成領域をｎＰｎ型やＰＮＰ型の２重拡散型の構造
としてもよい。(4) Also, the conductivity type of each region 42, 3.5 may be reversed,
The resistance forming region may have an nPn type or PNP type double diffusion type structure.
また、第４図では抵抗形成領域２ｂ、３ｂの一方（７）
Ｉｉ１２ｂを階段状のパターンとし離間部−４ｂの距離
を変化させるものであり、抵抗形成領域２ｂ、３ｂの拡
散深さの制御により、離間部４ｂの下部において真領域
２ｂ、３ｂ間の接続状態が変化し、パターン変更するこ
となしに製造時の処理（拡散温度、時間、不純物濃度な
ど）を変更することによって抵抗値を大巾に可変するこ
とができるようになる。なお、第３．４図中の離間部４
ａ。In addition, in FIG. 4, one (7) of the resistance formation regions 2b and 3b
Ii 12b is formed into a step-like pattern to change the distance between the separation parts -4b, and by controlling the diffusion depth of the resistance forming regions 2b and 3b, the connection state between the true regions 2b and 3b is adjusted at the lower part of the separation part 4b. By changing the manufacturing process (diffusion temperature, time, impurity concentration, etc.) without changing the pattern, the resistance value can be varied widely. In addition, the separation part 4 in Fig. 3.4
a.
４ｂの基体表面部分は第１図（ａ）、（ｂ）と同様に厚
い絶！Ｉ１ｍを形成されているものである。The surface portion of the base body 4b is thick as shown in FIGS. 1(a) and (b). I1m is formed.
以上の如く本発明によれば離間部において抵抗形成領域
は低濃度となるので、高い抵抗値が得られ、それによっ
て、同一抵抗値に必要な領域が小さくてよいため集積度
を向上でき、また同一拡散領域でもって大から小までの
抵抗値を得ることができ、特に最終の製造段階でその処
理条件を変えること（５）
により抵抗値が変えられるので実用的である。As described above, according to the present invention, since the resistance formation region has a low concentration in the separated portion, a high resistance value can be obtained.As a result, the area required for the same resistance value can be small, so that the degree of integration can be improved. It is practical because it is possible to obtain resistance values ranging from large to small with the same diffusion region, and in particular, the resistance value can be changed by changing the processing conditions (5) at the final manufacturing stage.
第１図は（ａ）、（ｂ）は本発明の一実施例を示すパタ
ーン図および断面図、第２図は第１図中の半導体基板内
の不純物濃度分布を示す図、第３図及び第４図は本発明
の他の実施例を示すｔＸｍターン図である。
２．３・・・Ｎ型半導体領域（抵抗形成領域）、４・・
・離間部、６Ａ、６Ｂ・・・絶縁膜。
代理人弁理士 岡 部 隆1A and 1B are pattern diagrams and cross-sectional views showing one embodiment of the present invention, FIG. 2 is a diagram showing the impurity concentration distribution in the semiconductor substrate in FIG. 1, and FIGS. FIG. 4 is a tXm turn diagram showing another embodiment of the present invention. 2.3... N-type semiconductor region (resistance formation region), 4...
- Separation part, 6A, 6B...insulating film. Representative Patent Attorney Takashi Okabe
Claims (1)
に形成された第１、第２の抵抗形成領域と、これら両抵
抗形成領域の一部にそれぞれ形成された電気接続点とを
有□し、こ′れら両抵抗形成領域が重なる部分を含む部
分の半導体基板表面には他の部分より肉厚の厚い絶縁膜
が形成された構造の半導体抵抗装置。The semiconductor substrate has first and second resistance formation regions formed such that their ends partially overlap on the surface of the semiconductor substrate, and electrical connection points formed respectively in parts of both resistance formation regions. , a semiconductor resistor device having a structure in which a thicker insulating film is formed on a portion of the semiconductor substrate surface including a portion where these two resistor formation regions overlap than in other portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15113881A JPS5851555A (en) | 1981-09-23 | 1981-09-23 | Semiconductor resistance unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15113881A JPS5851555A (en) | 1981-09-23 | 1981-09-23 | Semiconductor resistance unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5851555A true JPS5851555A (en) | 1983-03-26 |
Family
ID=15512194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15113881A Pending JPS5851555A (en) | 1981-09-23 | 1981-09-23 | Semiconductor resistance unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851555A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0198468A2 (en) * | 1985-04-15 | 1986-10-22 | Nec Corporation | Protective device for integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5087592A (en) * | 1973-12-05 | 1975-07-14 | ||
| JPS5553451A (en) * | 1978-10-16 | 1980-04-18 | Nec Corp | Semiconductor device |
-
1981
- 1981-09-23 JP JP15113881A patent/JPS5851555A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5087592A (en) * | 1973-12-05 | 1975-07-14 | ||
| JPS5553451A (en) * | 1978-10-16 | 1980-04-18 | Nec Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0198468A2 (en) * | 1985-04-15 | 1986-10-22 | Nec Corporation | Protective device for integrated circuit |
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