JPS5850767A - Semiconductor device - Google Patents

Abstract

PURPOSE:To offer a semiconductor device containing capacity elements wherein resistance components are greatly reduced, by forming a diffused layer with low impurity concentration and one with high impurity concentration on the surface of a semiconductor substrate resulting in one side electrode of the capacity element. CONSTITUTION:A capacity element is constituted of a conductive poly Si layer 5 as one side electrode and of the diffused layer 3 with relatively low impurity concentration formed on the surface of the semiconductor substrate 2 via an insulating film 1 thereunder as the other side electrode. Since the diffused layer 3 is relatively larger in its resistance value, a diffused layer 4 with relatively higher impurity concentration is provided in the periphery of the end part thereof. Since the resistance value the diffused layer 3 has is not sufficiently reduced by the diffused layer 4, the diffused layer 4' with relatively higher impurity concentration is formed at approximately a central part of the diffused layer 3 by selectively removing the insulating film 1 and the poly Si layer 5. The diffused layer 4 and the diffused layer 4' formed on the central part are electrically connected by an Al layer 6 formed via an inter layer insulating film 1' formed on the surface of the conductive poly Si layer 5 and thus are taken out as the other side electrode of the capacity element.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a capacitive element formed on a semiconductor substrate.

Self-line mMI8 such as conductive polysilicon gate
In a FET (insulated gate field effect transistor) circuit, when forming a -capacitance element, K is as shown in Figure 1.
, a diffusion layer 3 with a low impurity concentration is formed on the surface of the semiconductor substrate 2 under the insulating film 1 by a method such as ion implantation, and a diffusion layer 3 with a high impurity concentration is formed on the surface of the semiconductor substrate 20 at the end of the insulating film 1. A layer 4 is formed to serve as one electrode of the capacitive element. (2) A conductive polysilicon layer 5 is formed on the L upper insulating film 1 to serve as the other electrode of the capacitive element.

The above capacitive element has M
It can be formed using the ISFET manufacturing process as is. That is, the diffusion layer 3 with a low impurity concentration is a depression layer.

Techniques for forming the channel region of MI8FB'r
Therefore, Vct can be formed simultaneously, and the diffusion layer 4, the conductive polysilicon layer 5GS, the source and drain of the MISFET can be formed at the same time. - Can be formed in accordance with the process of forming electrodes.

The capacitive element with the above structure has a large resistance component, as shown in the equivalent circuit diagram of Figure 82, due to the relatively large resistance value of the diffusion layer with a low impurity concentration.
There is a drawback that the Q as a capacitive element is low.

The four objectives of this invention are to:
An object of the present invention is to provide a semiconductor device including a capacitive element whose resistance component is significantly reduced.

Other objects of the invention will become apparent from the accompanying description and drawings.

FIG. 3 is a layout pattern diagram of a capacitive element showing an embodiment of the present invention, and FIG. 4 is a sectional view taken along line AB thereof.

In FIG. 3, the parts indicated by dotted lines are diffusion layers 4, 4' with relatively high impurity concentration, and the parts indicated by dashed and dotted lines are conductive polysilicon layers constituting one electrode of the capacitive element. It is 5.

In addition, the part indicated by the solid line is the aluminum layer 6,
It is mainly used to connect the diffusion layers 4 and 4'.

The structure of the capacitive element of this embodiment will be described below with reference to FIGS. 3 and 4.

Capacity □1. ．． ,Yo. Guide, sex point IJ71J:ry, 415
A diffusion layer 3 with a relatively low impurity concentration is formed on the surface of the semiconductor substrate 10 with an insulating film 1 interposed therebetween.
is configured as the other electrode. . Since the diffusion layer 3 constituting the above-mentioned passive electrode has a relatively large resistance value, a diffusion layer 4 having a relatively high impurity concentration is provided around its end. In this embodiment, since the resistance value of the diffusion layer 8 is not sufficiently reduced by the diffusion layer 4, the queen insulating film 1 and the conductive polysilicon layer 5 are selected at approximately the center of the diffusion layer 3. By selectively removing the impurity, a diffusion layer 4' having a relatively high impurity concentration similar to that described above is formed.

The diffusion layer 4 provided around the end portion and the diffusion layer 4' formed in the central portion are connected to the conductive polysilicon layer 50 through an interlayer insulating film 1 formed on the surface of the conductive polysilicon layer 50. It is electrically connected through the layer 6 and taken out as the other electrode of the capacitive element.

In this embodiment, the 94 aluminum layers do not merely electrically connect the diffusion layers 4 and 4';
A conductive polysilicon layer 5 is formed through the interlayer insulating film 1'.
It is superimposed on the top □. As a result, the above-mentioned diffusion layer 4
It is possible to obtain such a capacitance value that more than compensates for the MI8 capacitance between the conductive polysilicon layer and the diffusion layer 3 on the surface of the semiconductor substrate, which is reduced due to the formation of the semiconductor substrate. Therefore, the area occupied by the capacitive element for obtaining a predetermined capacitance value can be reduced.

■Providing the diffusion layer 4' above the desk and electrically connecting it to the diffusion layer 4 around the edge ・Because of K, the distributed resistance value in the diffusion layer 3 becomes smaller, and the parallel type 111 *
As a result of this, the equivalent resistance value in the diffusion layer 3 can be significantly reduced.

Although not limited to IVIVC, the above-mentioned capacitive element can be used as a MI of a well-known self-line type depression cord.
Formed using SFET manufacturing process 1
There is no need to add separate manufacturing processes.

As mentioned above, the capacitor/quantitative element according to this embodiment has a small resistance component, so 2. Its Q can be increased. .

Although there are no particular restrictions, a capacitive element with a reduced resistance component can be used as a circuit element for constructing a high-frequency oscillation circuit. Furthermore, since it can be used as a line capacitive element with a large actual capacitance value, various monolithic ICKs can be used.

In this case, the capacitive element in this embodiment is a degree mode MI8. JC formation at the same time as FET!'t!
QMI81i'ET
It can be said that it is suitable for monolithic IC1c including.

The invention is not limited to the above embodiments.

A plurality of relatively high impurity concentration diffusion layers 4' may be provided by partially removing the first conductive polysilicon layer and the insulating film constituting the MI8 capacitor. Also, the end of the diffusion layer 3 with relatively low impurity concentration! fl
The relatively high impurity concentration diffusion layer 4 provided with VC is divided and provided at the peripheral end portion.

The first conductor layer constituting one electrode may be connected to each other using a first conductor layer or a second conductor layer separated from the first conductor layer.

Further, the second conductive layer may be a conductive polysilicon layer in addition to the aluminum layer.

In Ic having a multi-wire wiring structure of three or more layers, it is preferable to use a third or higher conductor layer to connect the diffusion layers 4 and 4'.

[Brief explanation of the drawing]

Fig. 1 is a structural cross-sectional view showing an example of a conventional capacitive element, Fig. 2 is its equivalent circuit diagram, Fig. 3 is a layout pattern diagram showing an embodiment of the present invention, and Fig. @4 is its equivalent circuit diagram. FIG. 1... Insulating film, 1'... Interlayer isolation jlJ[, 2...
Semiconductor substrate, 3...diffusion layer, 4,4'...diffusion layer,
5... Conductive polysilicon layer, 6... Aluminum layer. Figure 1 Figure 21'21 Figure 4

Claims (1)

[Claims] 1. A first semiconductor region of a second conductivity type formed on a semiconductor substrate made of a first conductivity and having a relatively low impurity concentration; a second conductive layer provided around the first semiconductor region and made of a second conductive material with a relatively high impurity concentration; A third semiconductor region of the second conductivity type provided on the first semiconductor region-plane and having a relatively high impurity concentration.
a semiconductor region, the conductor layer is one electrode, and the second semiconductor region is the semiconductor region. A semiconductor device comprising a capacitive element electrically connected to the 30th conductor region to serve as the other electrode extraction point. 2. The first semiconductor region is formed by an ion implantation method performed through at least an insulating film, and the second
．． 2. The semiconductor device according to claim 1, wherein the third semiconductor region is formed simultaneously using the insulating film as part of a mask.