JPS5850607A - Compressing and expanding circuit for time axis - Google Patents

Abstract

PURPOSE:To eliminate the deviation in the reproducing speed of sounds and selecting timings of switches by converting writing clocks with a frequency-voltage converter thereby obtaining a voltage for controlling selection with switches. CONSTITUTION:A frequency-voltage converter 31 is inputted with the output of a voltage controlling oscillator 24 for generating writing clocks and converts the frequency thereof to a DC voltage. A reproducing speed is controlled by a variable resistor VR1 19 for setting the reproducing speed. The change in the output frequency of the oscillator 24 corresponds as it is to the change in the reproducing speed, and the DC voltage converted from said frequency is inputted as a voltage for controlling selection with a switch 28 to a window comparator 32. The comparator 32 outputs the signal which is not subjected to processing for compressing and extending of time axis by closing the contact (a) 29 of the switch 28 when the ratio between the recording speed and the reproducing speed is around 1; otherwise the comparator outputs the signal subjected to said processing by closing the contact (b) 30 of the switch 28.

Description

[Detailed description of the invention] The present invention relates to a time axis compression/expansion circuit.

To explain in detail in W., the present invention is capable of f
The present invention relates to switching control of processing signals at a speed different from the recording speed (hereinafter referred to as time axis compression/expansion device C) used when reproducing image signals at a speed different from the recording speed.

In order to listen to the contents recorded on a tape recorder slowly or in a short period of time, the playback speed is often set to 1%. In this case, simply increasing the repopulation speed will change the NiM number band of the reproduced signal, making it impossible to obtain a reproduced sound that is less understandable. The companding operation on the time axis is performed to return to the me number band and obtain reproduced sound with good intelligibility. There are several methods for time axis companding processing, but one known method is to use an analog self-contained device such as a BBD and vary the write clock signal according to the playback speed for a constant read clock signal. ing.

FIG. 1 is a block diagram of a time-monitoring circuit of a variable speed playback tape recorder using a BED. The signal picked up by the playback head Ill is equalized and amplified by a playback equalizer (P, Eq) +21, and then transferred to four BBDs, namely BBD-1131.
,BBD-2+41,BBD-3+51- BBD-
4-6) are sequentially written with the write clock W).

Reading is done using the read clock (fr), which is also BBDI.
C3) Kara BHD -2r4) is performed in order.

The read signal is sent to analog switch A S-1f71
~As-4QQ is outputted as one serial signal by opening and closing, and applied to the amplifier αD. Time axis companding processing becomes possible by periodically writing and reading data using four BBDs. However, if this process is simply repeated periodically, when the output signals of four BBDs are combined into a serial signal, discontinuities will occur in the IJ@ waveform at most of the connections. This waveform discontinuity causes high-wave noise, which reduces the clarity of the synthesized sound.

Therefore, there is a need for a hardening method that does not cause this waveform discontinuity, and the arithmetic processing unit 0 is responsible for this process. , FIG. 2 shows the principle of this processing, and is an example when the reproduction speed is about 0.7 times the recording speed A. In Figure 2,
(TI) (7'2) . . . is a processing cycle, which is usually set to a constant value of 20 to 3QmzgC. The regenerated and amplified signal is written to each BBD, and each (tl
The signals in the interval l(tx HtMHtj) are respectively B
The signals taken into the BD are sequentially read out in processing cycles from 14 to T7 and become a composite output. Here, the period (t+)(t2)(ts)(
ta) is determined by the arithmetic processing unit (to), and a g waveform without discontinuities is synthesized. In other words, the rear end of the signal written in the BBD read in a certain processing cycle and its The correlation with the leading edge of the signal written in the BBD to be read next becomes 1 in parallel with the writing process.
The timing of stopping the write clock is determined so that the correlation is the highest. This process makes it pure lol
A composite signal waveform having one part is obtained.

Now, the purpose of this time axis companding method is to obtain a signal with poor intelligibility even when changing the playback speed.1 For example, playback speed and recording speed! The ratio, that is, the gear ratio is 1.0
If it's in the vicinity, it's OK to output a playback signal with a frequency change depending on the playback speed without time-base companding processing! Therefore, in a practical time-companding device, the f speed ratio is around 1.0 and the reproduced signal without being subjected to the time-base companding device is outputted as it is. FIG. 3 shows a time-base companding apparatus previously proposed by the applicant having such a structure. VR1α9 and VF
6 (e) is an interlocking variable resistor. vBIQ9 is a variable resistor for the reproduction art installation that is connected to the motor control circuit 2111m. Motor control circuit @ is V, R1
With the resistance value of 11g and the FG pulse from the motor,
vB2ω, which controls the rotational speed of the motor (2), generates a divided voltage νd of weC in accordance with the reproduction speed in conjunction with the reproduction speed setting VR10g.

The FG pulse is input to a phase comparator, and its phase is compared with a signal obtained by dividing the write clock from the electronically controlled oscillator (2) by a divider H4 (to). The output of the phase comparator (to) is applied to the voltage control oscillator @ through the low-pass filter ω, and as a result, a write clock corresponding to the reproduction 11 darkness can be obtained. Input to the comparator t< v −y (
Wi%dow Comparator)elh performs switching control of the switch (to) according to the value of the divided voltage Cvd). That is, the value of vd shown when the gear ratio is in the vicinity of 1.0 closes the contact a@ of the switch and outputs a signal that is not subjected to time axis companding processing, and conversely The contact h (to) of the switch (to) is closed according to the value of vd indicated when the ratio is outside the vicinity of 1.0, and a signal subjected to 2-time axis companding processing is output.

Here, the vicinity of the gear ratio 1.0 is determined empirically and experimentally, and this determines the high-level comparator voltage of the window comparator (vahH) where the gear ratio is the speed ratio, the highest speed in the vicinity of 0. [corresponding to regeneration] and a low comparator voltage tveL) corresponding to the lowest speed regeneration in the vicinity of the C speed ratio of 1.0] are determined. With the configuration shown in Figure 183, it is possible to switch the signal when the f speed ratio is around 1.0, but with this method, one of the two variable resistors is
(It is difficult to establish an accurate correspondence between the playback speed and the switch changeover control [14 pressure.) , if the motor control circuit (to) has a large ILF characteristic, the correspondence between the regeneration interval and the switch switching control voltage will break down. There were cases where the signal was output more than the other, or the opposite signal was output, which caused problems in use.

The present invention has been devised in consideration of this point, and the present invention will be described in detail below with reference to an embodiment shown in FIG.

@ In Figure 4, the frequency-to-voltage converter (hereinafter referred to as FF-V converter) 811 is the output of the voltage control oscillator (to) for writing clock generation, which is the input, and converts the ff1H number into a DC voltage. . The regeneration station is adjusted by the variable resistor V R1 (1111) for installing the regeneration station. The converted DC voltage is passed through the window comparator (2) as the switch (to).
) The operation of the window comparator (which is manually operated) is completely similar to the conventional example shown in Figure 3, and the output voltage of the FV converter is F.
Then, 'ct,':'p≦'ci・m〆The contact point a of the switch (to) is closed in the range of F, and a signal that is not subjected to time axis companding processing is output.

In the range 'F<'CL, F>CH·L2)V, contact b (to) of the switch (to) is closed and control is performed to output a signal that has been subjected to one-time axis companding process.

As described above, according to the configuration according to the present invention ζ2, it is possible to obtain the switch changeover control 4EE that accurately corresponds to the playback speed.
It is possible to realize an FF voice time axis iE device that does not cause a lag between the actual playback speed and the switch switching timing as seen in the conventional example.

[Brief explanation of drawings]

@Figure 1 is a basic configuration diagram of the time axis companding circuit, Figure 2 is a signal processing time chart in which signal processing is not performed to prevent the occurrence of a single twill part in the tethered part of a sound protection element, and Figure 3 is a time chart of signal processing. is interlocking type 1
FIG. 4 is a block circuit diagram showing the time axis IIEa expansion circuit of the present invention. '31 se 4) 1506) ,,, storage means-t7) 18
) +91Q (1-7 analog switch, I... amplifier,
Otori...J-Dze detector, U...arithmetic processing circuit, I...
・・Clock control circuit, ω・4-voltage fallback, −・・・
Phase comparison circuit, @...vco, e2B...-5tn
vessel. (To)...LP! ...(to)...off 4-way switch circuit, ui+...F/I/cross switch, (to)...window comparator.

Claims (1)

[Claims] (1) When reproducing a ** signal recorded on a recording medium in the dark, write clock generation means generates a write clock corresponding to the reproduction interval, and the output of the write clock generation means @ A frequency-voltage conversion means for converting a wave number into a voltage signal f, and 1 for monitoring the voltage signal from the frequency-voltage conversion means! The frequency-voltage converting means includes a voltage comparing means and a signal switching means controlled by the Mtj&amp; If the signal switching means is controlled by the Tatsuta comparison means so as to output a reproduction signal, and the voltage signal indicating that the ratio of the reproduction speed to the recording speed is other than around 10 is !
Time axis compression of audio, characterized in that the signal switching means is controlled by the voltage comparing means so as to output a signal obtained by subjecting the reproduced signal to time axis companding processing when outputted from the wave number and pressure converting means. extension circuit.