JP2559441B2 - PCM signal correction circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a PCM signal correction circuit suitable for use in a PCM signal transmission device.

[Conventional technology]

When D / A converting a digital audio signal converted into PCM, a digital filter as disclosed in JP-A-57-113618 is used to perform data interpolation between sample data in the digital audio signal. Many audio signal corrections are made. This digital filter uses response data (hereinafter referred to as impulse response data) when a unit impulse is passed through an ideal low-pass filter.
This will be explained briefly.

FIG. 10 is a waveform diagram showing this response data, in which the horizontal axis represents time t and the vertical axis represents the amplitude value.

This response data shows that if the cutoff frequency of the ideal filter is ¹ / 2T and the time point when the maximum amplitude value is t = 0, the amplitude value becomes zero at ± T, ± 2T, ± 3T, ... =
The amplitude decreases as it deviates from zero.

Now, assuming that the sample clock frequency of the PCM signal input to the digital filter is ¹ / T, the response data used at this time is impulse response data when the cutoff frequency is ¹ / 2T. Therefore, the waveform of this impulse response data is as shown in FIG. Further, the digital filter interpolates between the sample data of the input PCM signal with one data. In this case, the response data shown in Fig. 10 ± ¹ /
The amplitude value of 2T, ± 3T / 2, ± 5T / 2, ± 7T / 2, ..., That is, the amplitude value of the intermediate point between time t = 0 and ± T and the amplitude value of the intermediate point between each zero point are These amplitude values are normalized with the maximum amplitude value at time t = 0 set to 1. Here, the amplitude value at the intermediate point after time t = 0 is I ₁ , I ₂ , I ₃ , ....
Then, the amplitude value of the intermediate point before time t = 0 is set to I ₋₁ , I ₋₂ , I ₋₃ , ... From the time t = 0 side.

To simplify the description, the response data is the 10th
As shown in the figure, the period from -8T to + 8T is targeted.

The digital filter uses each sample data of the input PCM signal as a unit impulse, creates response data of each sample data using the impulse response data shown in Fig. 10, and interpolates the input PCM signal of these response data. All the components occurring at the intermediate point are added to obtain interpolation data at this intermediate point. Therefore, since the range of impulse response data was limited as shown in Fig. 10,
Now, the sample data of the time interval T of the input PCM signal is
As shown in FIG. 11, S _-7 , S _-6 , S _-5 , ..., S _-1,, S ₀ , S ₁ , S ₂ ,
..., and S _8, will be described for creating interpolated data S ₀₁ of sample data S _0, the midpoint of S _1.

In FIGS. 10 and 11, first, sample data S _-7
When is input, the response data of the ideal low-pass filter with this as a unit impulse has a waveform as shown in FIG. 10, and each amplitude value of the impulse response data at this time is
S _-7・ I _-8 , S _-7・ I _-7 , ..., S _-7・
I _-1 , S _-7 , S _-7・ I ₁ , ......, S _-7・ I ₈ The components of these amplitude values are the input P shown in Fig. 11, except for the component of the amplitude value S _-7 .
It is equal to the interval T between the sample data of the CM signal, and the component of this amplitude value S _-7 has the same timing as the sample data of the amplitude value S _-7 in FIG. Therefore, the timing of the component of the amplitude value S _-7 · I ₈ of the impulse response data coincides with the midpoint of the sample data of the amplitude values S ₀ and S ₁ in FIG. The component of the amplitude value S _-7 · I ₈ forms a part of the interpolation data S ₀₁ .

Next, when the sample data S _-6 is input, similarly, the amplitude value of the component of the impulse response data corresponding to this which coincides with the midpoint of the sample data S ₀ , S ₁ is S _-6 · I ₇
And this becomes a part of the interpolation data S ₀₁ . Similarly, with the input of the sample data S _-5 , S _-4 , ..., S ₈ , the amplitude value of the component of these impulse response data that coincides with the middle of the sample data S ₀ , S ₁ is S _-5・ I ₆ , S _-4
・ I ₅ , ..., S ₈・ I _-8 , and interpolation data S ₀₁ is obtained from them as follows.

S ₀₁ = S _-7・ I ₈ ＋ S _-6・ I ₇ ＋ S _-5・ I ₆ ＋ S _-4・ I ₅ ＋ …… ＋ S ₈・ I _-8 Thus, between each sample data of input PCM signal Interpolation data at the intermediate point is obtained, and the input PCM signal is interpolated by these interpolation data.

In this way, to obtain the interpolated data, each component of the normalized impulse response data obtained by supplying the unit impulse to the ideal filter is obtained, and each component is multiplied by the sample data of the input PCM signal. However, all the multiplication results that should be obtained at the same timing may be added.

Also, the number of interpolations between the sample data of the input PCM signal can be made arbitrary by determining the number of components between the zero points of the response data shown in FIG.

When the PCM signal is interpolated as described above, its sampling frequency becomes high. When the PCM signal is converted to an analog signal by the D / A converter, it is supplied to the analog low-pass filter in order to remove the sampling clock component, but the band of the analog signal component and the sampling clock component is separated. Therefore, this low-pass filter can have a gentle cut-off characteristic to simplify the configuration, and can reduce the phase distortion of the analog signal component.
In the case of audio signals, high quality audio reproduction is possible.

[Problems to be Solved by the Invention]

By the way, a discontinuous portion may occur in the PCM signal, and waveform distortion occurs in this discontinuous portion in the analog signal obtained by D / A converting the PCM signal.

For example, in a digital audio tape recorder (hereinafter referred to as DAT), one revolution of the rotary head
The reproduced digital audio signal is processed as a frame in units of one frame (for example, Japanese Patent Laid-Open No. 58-
188314). At the time of normal reproduction, assuming that one cycle corresponds to one cycle in FIG. 12 (a), the entire reproduced digital audio signal is processed in one frame unit.
As shown in FIG. 6B, a continuous original audio signal is obtained. In DAT, variable speed playback is also possible to provide functions such as cueing. For example,
In the case of double speed reproduction, the magnetic tape runs at twice the speed of normal reproduction. Therefore, the reproduced digital audio signal is every other frame. Therefore, processing is performed for every other frame,
When such processing is performed, as shown in FIG. 12 (c), every other frame is extracted and processed, which is equivalent to the splicing of these frames. Waveform discontinuity occurs at A.

Therefore, when the digital audio signal in which the discontinuity occurs in the waveform as described above is subjected to the interpolation processing by the above digital filter, the interpolation data is formed and interpolated based on the sample data of the area including the discontinuity. Part occurs. When D / A conversion is performed on such a digital audio signal, waveform distortion will occur at this portion of the obtained analog audio signal. This waveform distortion appears periodically in the frame period, and as a result, abnormal sound is mixed in the reproduction audio.

It is an object of the present invention to provide a PCM signal correction circuit which solves such a problem and can suppress the influence of the discontinuous portion of the PCM signal.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention, when processing a PCM signal with a digital filter, detects the discontinuous portion of the PCM signal by means of detecting the discontinuous portion of the PCM signal. Have different characteristics.

[Action]

The digital filter normally operates as a low-pass filter that passes the entire band of the PCM signal. The detecting means detects a certain section including the discontinuous portion of the PCM signal, and the cutoff frequency of the digital filter becomes sufficiently lower than the upper limit of the band of the PCM signal with the detection. Thereby, the PCM signal is smoothly smoothed at the discontinuity.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings by taking a DAT as an example.

FIG. 1 is a block diagram showing an embodiment of a PCM signal correction circuit according to the present invention, in which 1 is a magnetic tape, 2 is a rotary head, 3 is a reproduction amplifier, 4 is a signal processing circuit, 5 is a digital filter, and 6 is a digital filter. Is a D / A converter, 7 is an LPF (low pass filter), 8 is a timing generation circuit, 9 is a control circuit, and 10 is an output terminal.

In the figure, the digital audio signal recorded on the magnetic tape 1 is reproduced by the rotary head 2, amplified by the reproducing amplifier 3, and then processed by the signal processing circuit 4. The method of recording the digital audio signal on the magnetic tape 1, the head-tape system, and the signal processing circuit 4 are shown only as an example of a DAT, and are not a main part of the present invention, so a detailed description will be given. Although omitted, for example, JP-A-58-18
The technique disclosed in Japanese Patent No. 8314 can be used.

The digital audio signal output from the signal processing circuit 4 is interpolated with sample data by the digital filter 5 as described with reference to FIGS. 10 and 11,
It is converted into an analog audio signal by the D / A converter 6. This audio signal is output from the output terminal 10 after the unnecessary sampling clock component is removed by the LPF 7.

Here, the sampling frequency at the time of normal reproduction of the digital audio signal output from the signal processing circuit 4 is 48 kHz, the frequency band of the original audio signal is 20 kHz, and the digital filter 5 is shown in FIGS. As described above, if data is interpolated one by one between each sample data of this digital audio signal, the sampling frequency of the digital filter 5 is 96 kHz (= 4
8kHz × 2), with cutoff frequency of 20kHz and low pass filter characteristics.

In LPF7, the pass band is set so that the entire band of the audio signal is passed from the D / A converter 6 and the sampling clock component is removed, but the sampling frequency is higher than the upper limit frequency (20 kHz) of this audio signal. Is sufficiently high at 96kHz, so it is not necessary to set the cutoff frequency of LPF7 near the upper limit frequency of the audio signal. For this reason, the configuration of the LPF 7 is simplified, and the phase distortion of the audio signal by the LPF 7 can be reduced.

Here, the digital filter 5 is configured to have variable characteristics.

The control circuit 9 performs switching control of each mode such as reproduction and stop, and the signal processing circuit 4 processes the reproduction digital audio signal in units of one frame when the reproduction mode is set. This one frame unit is set by detecting the rotation of the rotary head. If the rotation speed of the rotary head is 2000 rpm, one frame will be 30 msec. When the reproduction mode is set, the timing generation circuit 8 starts its operation according to the control signal from the control circuit 9, and the output signal obtained by the processing operation for each frame of the signal processing circuit 4 at the time of variable speed reproduction. Then, a characteristic switching signal is generated. The characteristic switching signal switches the characteristic of the digital filter 5.

Now, assuming that the double speed reproduction mode is set, in the signal processing circuit 4, as described above, the digital audio signal is one in which every other frame is extracted and spliced, as shown in FIG. The digital audio signal output from the signal processing circuit 4 at the boundary A between the adjacent frames shown in () is discontinuous as shown by the solid line in FIG. 2 (c). However, in FIG. 2 (c), the digital audio signal is shown as an analog waveform in order to simplify the explanation.

Therefore, in the signal processing circuit 4, when the variable speed reproduction operation is set by the control circuit 9, a fixed period including the boundary of each frame is detected in the processing on a frame-by-frame basis, and a signal representing this period is generated in timing. Send to circuit 8. Based on this signal, the timing generation circuit 8 outputs "H" (high level) during this fixed period as shown in FIG. 2 (b).
A characteristic switching signal is generated. Digital filter 5
Then, when this "H" characteristic switching signal is supplied, the cutoff frequency is switched to a low-pass filter characteristic sufficiently lower than the upper limit frequency (20 kHz) of the digital audio signal. This gives the digital audio signal
As indicated by the broken line in FIG. 2 (c), the waveform becomes smooth in a certain period including the discontinuous time point A, and no abnormal noise is generated in the reproduced audio by the audio signal obtained at the output terminal 10.

The period of the characteristic switching signal shown in FIG.
One frame is set to about 2msec instead of 30msec.

FIG. 3 shows an example of the impulse response characteristic of the digital filter 5, the solid line shows the low-pass filter characteristic during normal reproduction, and the broken line shows the low-pass filter characteristic during variable speed reproduction. Here, assuming that the cutoff frequency during normal reproduction is 20 kHz, the cutoff frequency during variable speed reproduction is 1/4 of that.

FIG. 4 is a block diagram showing a specific example of the interpolation data forming section of the digital filter 5 in FIG.
Is a data storage circuit, 16 is a data address counter, 17 is a coefficient storage circuit, 18 is a coefficient address counter, 19 is a multiplication circuit, 20 is an addition circuit, 21 is a latch circuit, 22 is a preset circuit, 23 is an input terminal, and 24 is an input terminal. An output terminal, 25 is an input terminal, 26 is a coefficient address counter, 27 is a preset circuit, and 28 is a switch.

In the figure, the output digital audio signal of the signal processing circuit 4 (FIG. 1) is input to the input terminal 23 and is temporarily stored in the data storage circuit 15. Also, the coefficient storage circuit
17, the amplitude values I _-8 I _-7 , ..., I _-1 , I ₁ , ..., I _{8 of the} impulse response data shown by the solid line in FIG. 3 are stored as coefficients. The sample data at the address designated by the data address counter 16 is read from the data storage circuit 15, and the coefficient at the address designated by the coefficient address counter 18 or 26 is read from the coefficient storage circuit 17. Then, the sample data and the coefficient are multiplied by the multiplication circuit 19. The output data of the multiplication circuit 19 is an addition circuit
At 20 the data of the latch circuit 21 is added and the data is latched by the latch circuit 21. Every time the sample data from the data storage circuit 15 and the coefficient from the coefficient storage circuit 17 are multiplied, the output data of the multiplication circuit 19 is added to the data of the latch circuit 21 in the adder circuit 20 to generate timing in the latch circuit 21. When the latch pulse φ _R is supplied from the circuit 8, the output data of the adder circuit 20 is latched by the latch circuit 21.

Next, the operation of this specific example at a portion where the digital audio signal input to the input terminal 22 is continuous and a portion where the digital audio signal is discontinuous will be described. Note that here, the coefficient storage circuit 17
In FIG. 3, 16 coefficients I _-8 I _-7 , ..., I _{8 of} the impulse response data shown in FIG. 3 are stored. More specifically, the coefficient I ₈ is assigned to the address 0, I ₇ is at address 1, ...
..., the coefficient I _-7 is stored in the address 14, and the coefficient I _-8 is stored in the address 15. In addition, the data storage circuit 15
When 16 pieces of sample data are stored and sample data is input from the input terminal 23, this sample data is rewritten with the oldest sample data among the sample data stored in the data storage circuit 15. Input terminal 25
The signal input to is the signal from the signal processing circuit 4 (FIG. 1) shown in FIG. 2 (b).

First, the operation for a continuous portion of the digital audio signal will be described with reference to FIGS. 3 and 5, and the digital audio signal at this time is shown in FIG.

With the settings of normal playback mode and variable speed playback mode,
The preset circuit 22 and the data address counter 16 are reset (this means is omitted but controlled by the timing generation circuit 8), and at the same time, the reset pulse RS ₁ is output from the timing generation circuit 8 and the coefficient address counter 18 is also output. Reset and initial settings are made.

After that, the signal "L" shown in FIG.
Is input and the switch 28 closes to the A side. From the timing generation circuit 8, clocks φ ₀ , φ ₁ , φ ₂ , latch pulse φ _R , preset pulse PS ₁ , reset pulse RS ₁ , RS ₂
Is output, and the data storage circuit 15 writes and reads the sample data, and the coefficient storage circuit 17 reads the coefficient. Clocks φ ₁ and φ ₂ and latch pulse φ
_R has the same frequency and is 16 times the sampling frequency of the digital audio signal, and the latch pulse φ _R is 180 ° behind the clocks φ ₁ and φ ₂ . The preset pulse PS ₁ and the reset pulses RS ₁ and RS ₂ have the same frequency as this sampling frequency. Now, at time t _{0 in} FIG.
, The preset value of the preset circuit 22 is 0, the sample data S _{-7 in} FIG. 11 is stored at the address 0 of the data storage circuit 15, the sample data S _-6 is stored at the address, ...
It is assumed that the sample data S ₈ is stored at the address 15. At this time t ₀ , the timing generation circuit 8 outputs the preset pulse PS ₁ and the reset pulse RS ₁ , presets the preset value 0 to the data address counter 16 and resets the coefficient address counter 18. Shortly after that,
The timing generation circuit 8 outputs the reset pulse RS ₂ .
Reset the latch circuit 21.

By the preset value 0 of the data address counter 16, the sample data S _-7 is read from the address 0 of the data storage circuit 15, and at the same time, the coefficient storage circuit 1 is read.
The coefficient I ₈ is read from the address 0 of 7. These are multiplied by the multiplication circuit 19, and the data of S ₋₇ · I ₈ is supplied to the addition circuit 20. At this time, the latch 21 has just been reset, the data is 0, the but connexion by Ratsuchiparusu phi _R, data S _-7 · I ₈ is latched in the latch 21.

At the next rise of clocks φ ₁ and φ ₂ , the data storage circuit 15
Sample data S _-6 from the address 1 of the coefficient storage circuit 1
The coefficient I ₇ is simultaneously read from the address 1 of _{7 and} the data of S _-6 · I ₇ is supplied to the adder circuit 20 in the same manner. This data is added to the data of S _-7 · I ₈ from the latch circuit 21, and is latched in the latch circuit 21 by the latch pulse φ _R. Therefore, the latch data is (S _-7・ I ₈ ＋ S _-6・
I ₇ ).

Similarly, when the sample data is sequentially read from the data storage circuit 15 and the coefficients are read from the coefficient storage circuit 17 and the respective addresses 15 are designated, the latch data of the latch circuit 21 is S _-7 · I ₈ + S _-6・ I ₇ ＋ …… ＋ S ₀・ I ₁ ＋ …… ＋ S ₈・
It will be I _-7 . This is the interpolation data between sample data S ₀ and S _1.
This is S ₀₁ (Fig. 11).

On the other hand, although not shown, each sample data output from the signal processing circuit 4 (FIG. 1) is delayed so that the time when the interpolation data is output to the output terminal 24 is the center time between the sample data. As a result, the interpolation data S ₀₁ obtained at the output terminal 24 is added to the digital audio signal at the center point of the sample data S ₀ and S ₁ . Therefore, the sample data S ₀ and S ₁ are interpolated.

During the above operation, the next sample data S ₉ from input terminal 23
Is input, and the sample data S _-7 is rewritten to the address 0 of the data storage circuit 15. At the same time, the timing generation circuit 8 sends the clock φ ₀ to the preset circuit 22 so that the preset value of the preset circuit 22 becomes 1
Becomes

Address in data storage circuit 15 and coefficient storage circuit 17
Immediately before the rise of the next clocks φ ₁ and φ ₂ after the reading of 15 (time t ₂ ), the timing generation circuit 8 sets the preset pulse.
PS ₁ and reset pulse RS ₁ are generated, and immediately after that, reset pulse RS ₂ is generated. As a result, the data address counter 16 is preset to the value 1, and the sample data S _{-6 at the} address 1 is read from the data storage circuit 15. At the same time, the coefficient address counter 18 is reset to 0, so that the coefficient I _{8 at} address 0 is read from the coefficient storage circuit 17. Therefore, the latch data of the latch circuit 21 becomes S _-6 · I ₈ by the processing of the multiplication circuit 19 and the addition circuit 20.

Similarly, the sample data is sequentially read from the data storage circuit 15 and the coefficient is read from the coefficient storage circuit 17, and the address 15 is designated in the data storage circuit 15 and the address 14 is designated in the coefficient storage circuit 17, and the sample data S ₈ and the coefficient I _-7 are read, the data storage circuit 15 stores the sample data S ₉ at the address 0 at the rising edge of the next clocks φ ₁ and φ _2.
However, the coefficient storage circuit 17 stores the address 15 at which the coefficient I _-8 is stored.
Is specified. Thus, latch data in latch circuit 21 is a _{S -6 · I 8 + S -5} · I 7 + ... + S 8 · I -7 + S 9 · I -8. This is the interpolation data S ₁₂ between the sample data S ₁ and S ₂ , and is inserted at the center point between these sample data of the digital audio signal.

During the above operation, the next sample data S ₁₀
Is input, and the sample data S _-6 is rewritten in the address 1 of the data storage circuit 15. At the same time, the timing generation circuit 8 outputs the clock φ ₀ , and the preset circuit
The preset value of 22 is 2. Therefore, the next interpolation data
In order to create S ₂₃ , the data storage circuit 15 has the address 2
Therefore, the coefficient memory circuit 17 starts reading from address 0.

The operation proceeds as described above, and the interpolation data is sequentially created. In the preset circuit 22, the preset value of 15 is followed by the preset value of 0.

Next, the operation in the discontinuous portion of the digital audio signal will be described with reference to FIGS. 3, 6, and 7.

Here, the pass band of the digital filter 5 is set to 1/4 of that in the case of processing a continuous portion of the digital audio signal.
And Therefore, the impulse response becomes as shown by the broken line in FIG. This impulse response is the impulse response shown by the solid line in the positive and negative time directions with respect to its center.
Equal to double stretch. In this case, the same time range as the time range of the impulse response shown by the solid line is targeted. When the coefficients stored in the coefficient storage circuit 17 are used, only the impulse response coefficients I ₋₂ , I ₋₁ , I ₁ , and I ₂ shown by the broken line are used for the processing.

When the characteristic of the solid line in FIG. 3 is for interpolation processing of a PCM signal with a sampling cycle of T, the characteristic shown with a broken line is for interpolation processing of a PCM signal with a sampling cycle of 4T. Therefore, as shown in FIG. 7, looking at the discontinuous portion of the digital audio signal with the sampling period T, processing this with the impulse response data shown by the broken line in FIG. Is to obtain the interpolated data at the central point between these sample data. For example, in FIG. 7, the target sample data is S ₃ , S
₇ , S ₁₁ , S ₁₅ , ..., sample data between them
Interpolation data at the time points S ₅ , S ₉ , S ₁₃ , ... will be obtained.

The "H" signal shown in FIG. 2B is input to the input terminal 25 for a certain period of time including the discontinuity of the digital audio signal (between the sample data S ₉ and S _{10 in} FIG. 7). Switch
28 is switched to the B side, and the timing generation circuit 8 is
Preset pulses PS ₁ , PS ₂ , clocks φ ₁ , φ ₃ , latch pulse φ _R , reset pulse RS ₂ are generated at the timings shown in the figure. That is, the preset pulse PS ₁ , the clock φ ₁ , and the reset pulse RS ₂ are the same as those in the above processing for the continuous portion of the digital audio signal, but the clock φ ₃ and the latch pulse φ _R are the clocks shown in FIG. φ ₂
(Therefore, clock φ ₁ ), 1 / of the latch pulse φ _R
The frequency is 4, and the latch pulse φ _R lags the clock φ ₃ by 1/2 cycle of the clock φ ₁ . Pre excisional pulse PS ₂ is four times the period of the clock phi _3, are matched to the clock phi ₃ of every 4 cycles.

Coefficient address counter 26 counts the clock phi _3, and the pre-excisional pulse PS ₂ to Yotsute Purisetsuto circuit 2
The preset value of 7 is preset. Here, the third
Since the impulse response shown by the broken line in the figure is used, its coefficients I ₂ , I ₁ , I _-1 , I _-2 must be read from the coefficient storage circuit 17. For this purpose, the preset value of the preset circuit 27 is set to 7 and the coefficient address counter 26
Addresses 7, 8, 9, 10 in which the coefficients I ₂ , I ₁ , I _-1 , I _{-2 of the} coefficient storage circuit 17 are stored are sequentially and repeatedly specified every four cycles of the clock φ ₁ .

Below, sample data S ₃ , S ₇ , S for every 4T in FIG.
_The processing operation will be described assuming that ₁₁ , S ₁₅ , ...

Now, with respect to digital audio signal period shown in FIG. 7, the data storage circuit 15, the sample data S ₁
To address 0, sample data S ₂ to address 1, ...
It is assumed that the preset value of 0 of the preset circuit 22 is stored in the address 15 of the sample data S ₁₆ and is preset in the data address counter 16 (time t ₃ ). Immediately thereafter, the latch circuit 21 is reset by the reset pulse RS ₂ .

The coefficient I _{−2 of the} address 10 designated by the coefficient address counter 26 is read from the coefficient storage circuit 17, and during this period, the data storage circuit 15 stores the data address counter 16
Therefore, the sequential addresses 0 and 1 are designated and the sample data S ₁ and S ₂ are sequentially read out, but since the timing generation circuit 8 does not output the latch pulse φ _R , S ₁ · I ₋₂ and S ₂ · I _{− 2}
Is not latched by the latch circuit 21.

When the address 2 is designated in the data storage circuit 15, the preset value of 7 in the preset circuit 27 is preset in the coefficient address counter 26, and the address 7 is designated in the coefficient storage circuit 17. As a result, the sample data S ₃ is read from the data storage circuit 15 and the coefficient I ₂ is read from the coefficient storage circuit 17, respectively. These are multiplied by the multiplication circuit 19 and supplied to the addition circuit 20. Immediately after that, the latch pulse φ _R is supplied to the latch circuit.
The data S ₃ · I ₂ is supplied to the latch circuit 21 and is latched by the latch circuit 21.

When the sample data S ₄ , S ₅ , and S ₆ are read from the data storage circuit 15, the coefficient I ₂ is read from the coefficient storage circuit 17, but since the latch pulse φ _R is not supplied to the latch circuit 21, the latch data is S _3. It remains at I ₂ .

Next, when the coefficient address counter 26 counts up the clock φ ₃ , the coefficient I _{1 at the} address 8 is read from the coefficient memory circuit 17, and the sample data S _{7 at the} address 6 is also read from the data memory circuit 15. . These multiplication data S ₇ · I ₁ are supplied to the adder circuit 20 and added with the latch data S ₃ · I _2. Immediately after that, the timing generation circuit 8 outputs the latch pulse φ _R , so the adder circuit 20
Output data is latched by the latch circuit 21. Therefore, the latch data is (S ₃ · I ₂ + S ₇ · I ₁ ).

Similarly, when the sample data S ₁₁ and S _{15 for} every 4T of the clock φ ₁ are read from the data storage circuit 15, the coefficients I _-1 and I _-2 are read from the coefficient storage circuit 17, and these are stored. It is sequentially added with the latch data. The latch data obtained by this is S ₃ · I ₂ + S ₇ · I ₁ + S ₁₁ · I _-1 + S
₁₅ · I ₋₂ , which is the intermediate time point between the sample data S ₇ and S ₁₁ (ie sample data S ₉
Interpolated data). This is output from the output terminal 24 as sample data S ₉ to the adder circuit (not shown).

During the above operation, the next sample data S ₁₇ is input from the input terminal 23, and the address 0 of the data storage circuit 15 is rewritten with the sample data S ₁ .

Then, the latch circuit 21 is reset by the reset pulse RS ₂ , and the data storage circuit 15 reads the sample data from the address 2. After that, in the second cycle of the clock φ ₁ , the coefficient address counter 26 is preset with the preset value 7 of the preset circuit 27. At this time, the sample data S ₄ , S ₈ , S ₁₂ ,
When S ₁₆ is read, the coefficient I
₂ , I ₁ , I _-1 , I _-2 are read out, and the latch circuit 21 is similarly read.
In addition, the latch data of S ₄ · I ₂ + S ₈ · I ₁ + S ₁₂ · I _-1 + S ₁₆ · I _-2 can be obtained. This is the sample data in Figure 7.
It is output instead of S ₁₀ .

In this way, four sample data of every 4T are sequentially created as new sample data and sequentially output from the output terminal 24. That is, in the continuous portion of the digital audio signal, interpolation data is inserted between each sample data to double the sampling frequency, but in the discontinuous portion of the digital audio signal, each sample data is 4T every 4T. It is recreated with sample data of.
Therefore, the sampling frequency of the obtained digital audio signal is equal to that of the original digital audio signal, and the waveform becomes smooth at the discontinuous portion as shown in FIG. 2 (c).

In this case, since the multiplication circuit has 1/4 of the number of multiplications in the continuous portion of the digital audio signal, the accuracy of the sample data obtained is deteriorated, but the waveform is sufficiently smooth. In addition, the number of sample data stored in the data storage circuit 15 is set to 4 × 16 = 64, and the coefficient storage circuit
If all the 16 coefficients I ₈ , I ₇ , ..., I _-8 stored in 17 are used, the accuracy of the sample data obtained will be sufficiently increased,
It goes without saying that the smoothness of the waveform is further improved (however, in this case, the data storage circuit separates the continuous digital signal processing part and the discontinuous part processing part from each other). Is preferred).

FIG. 8 is a block diagram showing another specific example of the digital filter 5 in FIG. 1, in which 30 is a delay circuit, 31 is an arithmetic circuit, and 32 is a switching circuit. The same code is attached.

In the following, description will be given assuming that it has the same function as the specific example shown in FIG.

The delay circuit 30 has a capacity of storing 16 pieces of sample data, and sequentially transfers and delays the sample data input from the input terminal 23. Now, if the sample data output from the intermediate output terminal of the delay circuit 30 is S _i , this is 7T
Just being delayed. This sample data S _i is a switching circuit
Input to A side of 32. Further, the delay circuit 30 outputs the sample data S _i that precedes the sample data S _i by 2T.
_i-2 , 6T preceded by sample data S _i-6 , 2T after sample data S _{i + 2} and 6T number of sample data S _{i + 6}
Are output at the same time. These sample data are arithmetic circuits
At 31, the calculation processing of S _i-6・ I _-2 + S _{i + 2}・ I _-1 + S _i-2・ I ₁ + S _i-6・ I ₂ is performed, and the data obtained by this is sample data. It is supplied to the B side of the switching circuit 32 as S _i ′.

In the continuous portion of the digital audio signal, the "L" signal is input to the input terminal 25, so that the switching switch 32 selects the A side, and each sample data input to the input terminal 23 is delayed by the delay circuit 30. After being delayed by 7T, the signal is supplied to the output terminal 24 through the switching circuit 32. In contrast,
In the discontinuous portion of the digital audio signal, the switching circuit 32 selects the B side, and the sample data S _i ′ formed by the arithmetic circuit 31 is supplied to the output terminal 24 through the switching circuit 32.

For example, the digital audio signal as shown in FIG.
If S _i is the sample data S _{9 in} FIG. 7, the other sample data output from the delay circuit 30 are S _{i + 6} = S ₁₅ and S _{i + 2} = S
_{Since 11} , S _i-2 = S ₇ and S _i-6 = S ₃ , the sample data obtained by the arithmetic circuit 31 is S ₃ · I ₂ + S ₇ as in the specific example shown in FIG.・ I ₁ + S ₁₁・ I _-1 + S ₁₅・ I _-2 .

The embodiment of the present invention has been described above.
The present invention is not applicable only to the discontinuous portion in the case of the variable speed reproduction of No. 1, but is also applicable to the discontinuous portion caused by any other cause. For example, in the miute, as shown in FIG. 9, at the start A of the miute control signal ((a) in the figure), the digital audio signal is discontinuous as shown by the solid line in FIG. 9 (c). End, where an abnormal noise is generated. In this case, Figs. 4 and 8
In the figure, by supplying a signal of "H" (Fig. 9 (b)) to the input terminal 25 for a certain period including the start point A of the miute control signal, as shown by the broken line in Fig. 9 (c), End in.

Further, the present invention can be applied not only to DAT but also to a digital sound reproducing device such as a CD player and a video disc.

〔The invention's effect〕

As described above, according to the present invention, an excellent effect that a discontinuous portion of a PCM signal can be changed smoothly and an abnormal noise due to the discontinuity can be prevented can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PCM signal correction circuit according to the present invention, FIG. 2 is a waveform diagram showing a PCM signal correction operation according to this embodiment, and FIG. 3 is a characteristic of the digital filter in FIG. 4 and 5 are block diagrams showing a specific example of the digital filter shown in FIG. 1, and FIGS. 5 and 6 are diagrams showing pulse signals of the respective portions of FIG. 4, and FIG.
The figure is a waveform diagram showing an example of discontinuous portions of the PCM signal.
FIG. 9 is a block diagram showing another specific example of the digital filter shown in FIG. 1, and FIG. 9 is a waveform diagram showing the miute operation of the digital filter shown in FIG. 4 and FIG.
Fig. 11 is a characteristic diagram of a conventional digital filter, and Fig. 11 is PCM.
FIG. 12 is a diagram showing an example of a signal waveform, and FIG. 12 is an explanatory diagram showing an example of occurrence of a discontinuous portion in a PCM signal. 4 ... Signal processing circuit, 5 ... Digital filter, 6 ...
... D / A converter, 7 ... Low-pass filter, 8 ... Timing generation circuit.

Claims (1)

(57) [Claims] 1. A digital filter having a low-pass filter characteristic, wherein the digital filter has a period T.
In the PCM signal correction circuit adapted to process the PCM signal composed of the sample data, the digital filter sets (n + 1) predetermined coefficients for each of the (n + 1) sample data in the period nT of the PCM signal. And each time the sample data is input, a multiplication circuit that multiplies the corresponding (n + 1) sample data including the input sample data by the corresponding coefficient, and the multiplication circuit. And an adder circuit for cumulatively adding (n + 1) multiplication results from the PCM signal. The output data of the adder circuit is interpolated data between sample data of the PCM signal, thereby exhibiting the low-pass filter characteristic, In the predetermined period including the discontinuous portion of the signal, the coefficient for multiplying the sample data in the multiplication circuit is changed, and the sample data in the predetermined period is added in the addition circuit. By replacing the output data, narrowing the passband of the low-pass filter characteristics, PCM signal correction circuit, characterized by the that continuously discontinuous portion of the PCM signal.