JPS58500683A - Semiconductor memory device with variable threshold value - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Semiconductor memory device with variable threshold value Technical field This invention relates to a semiconductor substrate, a memory silicon oxide layer provided on said substrate, and a memory silicon oxide layer provided on said substrate. a silicon nitride layer on top of the memory silicon oxide layer; a silicon nitride layer on top of the silicon nitride layer; a silicon oxide layer at an interface and a date electrode on the silicon oxide layer at the interface; and the like.

Background technology Intelligent technology with features such as endless read/write cycles and high non-volatility. In the pursuit of ideal semiconductor memory devices, new forms of semiconductor structures have been developed in recent years. It's here. The most important of these are silicone goo) 5NO8 and 5O It is a multi-insulating layer structure that includes an NO8 structure and is commonly referred to as MNOS. Semiconductor metal An attractive feature of the MNO8 device used as a memory element is the Long term high flash without freshening or requiring bias voltage Ability to maintain distinguishable separation between conductance and low conductance states and the possibility of electrically changing those threshold voltages.

One of the drawbacks of the MNO8 device is the high voltage required to program the device (25 v or more).

The analytical theory of operation of these devices is based on the performance and reliability of MNOS) transistors. It has played an important role in leading to improvements in transistor design. early The theoretical model calculates the charging and discharging of MNOS devices by solving a one-dimensional continuity equation. I studied electric conduct. contain spatially distributed charge traps almost simultaneously. Tunnel theory was formulated. The original tunneling theory states that charge is trapped inside an insulator. oxidation, meaning that it is trapped only at the oxide-nitride interface, rather than at the oxide-nitride interface. The trapped charge (or charge) is a delta function centered at the material-nitride interface. J) is discussed. Mainly, the so-called thick oxide thickness was 50X or more These theories dealing with the oxide case ignore the nitride current and the Fowler-Nord Fowler-Nordheim) Oxidation due to the 7-channel effect It was thought that the physical current was dominant.

However, these theories did not predict observed consequences such as saturation of stored charge.

More recent studies have shown that the trapped charges are not confined to the oxide-nitride interface; , it has been revealed that it is also dispersed inside the nitride (bulk). . This distributed charge model is suitable for thin oxide (less than 50X) switches in MNOS devices. When trying to explain the switching and memory characteristics, we found that the direct band-to-band relationship -(dir ect band -to -band)) Channel effect and change Faulano Both Rudheim tunnel effects were used. According to this model, the oxide Due to the injection of charge that cuts the current J. There is a current J for nitride carrier transport. There is n. These current components represent a simplified energy band diagram of the 5NO8 structure. This is illustrated in FIG.

One view of these recent charge accumulation models is IEEETrar+8actions on Electron Devices (Vol, Ed-25.

A8, August 1978, pp. 1023-1030) - AnImproved M odel For Tbe Charging Characteristic sof A Dual-Dielectric (MNOS) Nonvo Beguwala et al. titled “latileMemory Device” It is explained in detail in a publication published by This model uses silicon conduction (Con duction) and from the valence band to the oxide and nitride conduction and to the valence band, respectively. Receive charge carrier injection. The current through the oxide is the charge carrier The modification is believed to be due to the Fowler-Nordheim tunnel effect. Also, this In the model, the tunneling effect through the oxide is This appears to be due to the dominant charge transfer mechanism at the interface between the nitride and the nitride. This model The dirt bias pulse is mainly used for various oxide thicknesses in the range 15-27X. given the current amplitude (write/erase), which shifts the flat-band voltage. , was considered to explain the observed MNOS memory characteristics. This model is MN The energy barrier shape of the OS structure is supplied as illustrated in Fig. 2. It teaches that it is the action of an electric field.

The three systems shown in Figure 2 are for the 5NO8 structure with high, medium and low positive bias. This is the case when a source is supplied. The top diagram of the figure shows that the charge tunnel is formed by oxide. represents the shape of the conduction band at very high electric fields when passing only through the Figure 2 The middle diagram represents the band shape for intermediate electric fields, and the bottom diagram represents the band shape for low electric fields. It is something. The electric field ranges for these three states are as follows, where 〆l and y2 are the potential barriers between silicon and oxide and between oxide and nitride, respectively. where Tox is the oxide thickness and ox is the instantaneous electric field of the oxide.

As mentioned above, it is obtained by the traditional charge storage model of the Beguwala type. Analytical oxide current changes charge carrier Fowler-Nordheim-Tonne This occurs due to the Le effect. This oxide current can be expressed by the following general formula.

In particular, Sc is the shape of the electric field that is scaled by a current smaller than 1. Depends on the situation.

G and F for the high electric field expressed in equation (1) are given by Takes a value.

G and F for the intermediate electric field expressed in equation (2) are given by .

G and F for the low electric field expressed in equation (3) are given by .

In the above explanation, h is a blank constant, Ti=h/2π, What about k? Boltzmann's constant, e is the electron charge or electric charge , T is the absolute ambient temperature of the device, m is the effective electron population, and Eni is the instantaneous electric field of the nitride. be.

The oxide current J predicted by the above equation. is generally as shown in Figure 3. . Figure 3 shows that the write and erase states of the 5NO8 device are dominated by the oxide tunneling current. memory oxide thickness (as taught by existing charge storage models) represents the expected change in saturation threshold voltage with . Starting from 0 threshold voltage, By providing a high bias, the charge tunnels across the oxide, causing large oxidation Generates physical current. Due to the tunneling effect, charge is stored near the oxide-nitride interface. At the same time, the threshold voltage becomes either a positive value or a negative value according to the polarity of the dirt. increase in that direction. Since charge accumulates near the oxide-nitride interface, the oxide and The internal electric field of the nitride is changed to decrease the oxide current and increase the nitride current.

This chain of events causes the oxide and nitride currents to equalize the saturation threshold voltage. It can be continued until Therefore, as seen in FIG. 3, the oxide thickness T. for xl , the threshold voltage is +VT1 or -vT for positive or negative polarity, respectively. The saturation value of l is reached.

According to the traditional charge storage model, if we were to increase the oxide thickness, the same given field conditions of 1, it is smaller than that obtained with thinner oxide devices. One would have expected a higher oxide current. This is illustrated by the thin dotted line in FIG.

As mentioned above, applying a positive or negative dart voltage will cause charge accumulation in the nitride. (However, the oxide current and nitride current quickly reach equilibrium values). This occurs at +vT2 or -VT2 as shown in .

The above analysis is based on the conventional electric power used to describe the memory characteristics of the 5NO3 device. According to the load accumulation model, the write and erase sides increase when the memory oxide thickness increases. This proves that the threshold voltage decreases.

This follows traditional theory and sacrifices write speed, erase speed, initial window, etc. of memory retention resulting from increasing the thickness of the memory oxide without increasing the It is not necessary to build thick oxide MNOS/5NO8 devices to take advantage of the increase It means that it is possible.

Existing theory also suggests low (approximately of thin nitride (approximately 400X thick or less) that can operate at voltages below 25V) It predicts that it will be impossible to build a 5NOS memory device.

This type of threshold changeable semiconductor memory device has been published in International Patent Application No. WO81. You can find out from No. 100790. This known device has a diameter of approximately 10-15X thickness. a silicon dioxide layer, a silicon nitride layer on the first silicon dioxide layer, and a silicon nitride layer on the first silicon dioxide layer; a second silicon dioxide layer having a thickness of about 70-100X on the silicon nitride layer; a semiconductor substrate provided with a polysilicon gate electrode on a silicon dioxide layer of 2; Including board.

Disclosure of invention According to this invention, it is said that the memory silicon oxide layer is in the range of about 25-40X , and the silicon oxide layer on the intermediate surface has a thickness in the range of 30 to 60 i. Provided is a semiconductor memory device with a variable threshold value.

The variable threshold semiconductor memory device according to the present invention has a high write speed and a large memory. It is clear that the window has the advantage of Furthermore, this invention It has the advantage of having high holding power.

In a preferred embodiment, the structure constituting the invention is such that the "oxide" on the intermediate surface is In addition to oxynitride and oxide-oxynitride structures, 5ONO8 (silicon-interface oxide-nitride) surrounding the known composition - memory oxide substrate). In particular, this invention relates to multiple dielectric dart structures. and various memory devices including transistors, capacitors, charge transfer darts, etc. Applicable.

The memory characteristics of this invention developed here are completely different under the conventional charge accumulation model. This is completely unexpected and requires a new concept of charge distribution in multiple dielectric devices. It was found that the explanation can be sufficiently explained using

This concept suggests that the charge for positive voltage is not only generated near the memory oxide-nitride interface. It is also stored near the gate electrode, and the accumulation of charges near the date electrode is due to the oxide-nitride This means that it is considerably larger than that at a compound interface. This memory oxide Charge accumulation at the nitride interface causes a Fowler charge change across the memory oxide. Conventional oxide current J resulting from Nordheim tunneling effect. This is for the sake of Game The accumulation of charge near the top electrode is called the interfacial current JINT shown in Figure 1. This is the result of a current component that could not be discovered. Is the current JINT due to nitride conduction? This occurs due to the transport of holes from the silicon valence electrons to the band. two The position of the charge center due to charge storage is a function of the number of charge traps, and the stored charge As illustrated in Fig. 4, but not generally, the quantity of Close to.

Brief description of the drawing FIG. 1 is a diagram of the energy bands of the 5NO8 structure representing the current components.

Figure 2 is a diagram illustrating the shape of the 5NQS conduction band under a given electric field. be.

Figure 3 shows the current components of the oxide and nitride layers and the 5N FIG. 6 is a diagram schematically illustrating the predicted relationship between the threshold voltage of an O8 device.

FIG. 4 shows an improved gradient according to the new charge storage concept used in the detailed description of the invention. This is a diagram illustrating the position of the center of charge.

FIGS. 5A and 5B show n+ polysilicon-nitride-oxide-semiconductor (5 NO8) Memory device and n+ polysilicon-oxide-nitride monoxide-semiconductor ( 5ONO8) is a schematic cross-sectional view of a memory device.

Figure 6 shows the observed saturation threshold voltage as a function of oxide thickness for a 5NO8 device. FIG. 3 is an exemplary graphical representation of pressure.

Figure 7 shows the observed maximum saturation threshold as a function of nitride thickness for the 5NO8 device. It is a graph diagram of value voltage.

Figure 8 shows the memory oxide thickness versus memory oxide thickness for writing and erasing a 5NO8 device. FIG. 2 is a graph showing the dependence of the initial (memory window) decay rate on .

Figure 9. Observations after 3 months as a function of oxide thickness for the 5NO8 device. FIG. 3 is a graphical illustration of a threshold window.

10 and 11 show various notes of a 5NO3 device constructed according to the present invention. A graph illustrating the change in threshold voltage depending on the pulse width with respect to the thickness of the Lie oxide. be.

FIG. 12 shows a polysilicon-oxide-nitride structure formed in accordance with the principles of the present invention. Change in threshold voltage depending on pulse width in monosilicon monoxide (5ONO8) structure It is a graph diagram illustrating.

FIGS. 13A and 13B illustrate charge traps and negative charge traps, respectively, in accordance with the present invention. and the current component for the positive gate bias of the device of FIG. 5A. FIG. 2 is a schematic diagram of a Lugi band.

Figure 14 shows a 3-dirt 5NOS memory system using memory transistors. FIG. 2 is a schematic cross-sectional view of a cell.

FIG. 15 illustrates an exemplary memory cell array using the cells of FIG. 14. This is a diagram.

FIG. 16 is a graphic diagram illustrating the effect of write/erase cycles on charge retention. It is.

BEST MODE FOR CARRYING OUT THE INVENTION The non-volatile (NV) memory device in FIG. 5A preferably has a thickness of 25 to 40 mm. It includes a 5NO8 structure 10 with a memory oxide 12. Typical Prior Art Note I J-structures use approximately 10-20X thin memory oxide to reduce retention and The writing speed is increased by putting a burden on it. The 5NO8 structure 10 according to this invention is Write speeds comparable to those provided by 10-20X memory oxide structures Not only is it great to provide, but it also provides excellent holding power.

This NV memory device uses a fairly thin W nitride 13 with a thickness of 150 to 250X. 5NO8 structure 10 having a 5NO8 structure 10 can be included. Prior art embodiments include a nitride layer Despite the fact that the increase increases the zologramming voltage, approximately ゛4 The standard is to use a nitride layer of 00X to 500X. programming Even with its drawback of increasing programming voltage, thin nitrides greatly increase the memory window. It is accepted because there is a traditional belief that it will lead to a significant decrease in there were. The 150-250X thin nitride device 10 according to the present invention has been commonly used in the past. Allows the use of a program voltage of approximately ±10 to 15V instead of the ±25V previously used. make it possible. However, there is some initial memory window reduction; A practical and useful memory win of about 5-7v, less than half of what was expected. leaving behind a dough.

The preferred embodiment NV memory device has a thin interplane oxide layer 14 (approximately 30-60X 5ON08 structure 100 of FIG. 5B with memory oxide and nitride layers including. This structure exhibits both increased maximum threshold voltage and increased writing speed.

Manufacturing The 5NO8 structure 10 shown in FIG. 5A has a conductivity of 10-20 Ω-m and a crystal orientation (1 00) based on a p-type single crystal silicon substrate 11. Board 1 1 was etched and cleaned in the conventional manner. Next, the silicon dioxide layer 12 is cleaned. Thermal growth was performed on the substrate surface.

This uses pure oxygen flowing at a flow rate of about 4 liters per minute for about 8 to 12 minutes. This is achieved by oxidizing the substrate 11 at a temperature of about 750°C using Ru.

The data for the thickness of the oxide layer 12 up to about 40, as indicated by the various openings, ta was obtained.

The silicon nitride layer 13 is then heated to a pressure in the range of 400-500 mTorr and about 75 mTorr. At a temperature of 0°C, silicon one-sided (5ilicon-bearing) Gas-dichlorosilane S r H2C70 (hereinafter referred to as DO8) and ammonia Oxide is produced by low pressure chemical vapor deposition (hereinafter referred to as LPGVD) by decomposition of NH3. was deposited on top of 12. The ratio of ammonia to DC8 is approximately 3.5:1 (or 100:1). (or higher), and the nitride deposition rate is It was 24X. The nitride thickness for an exemplary device is, for example, as shown in FIG. The range was from about 200X or less to about 400X.

After deposition of nitride 13, polysilicon layer 15 is heated to a temperature of approximately 625°C. It was formed by LPCVD using silane (5ilane). layer The thickness of the 15mm can typically be about 3,500-4,500X. Here The Sansol used was 4,000X thick.

Layers 12-15 are then etched using conventional photolithographic and etching techniques. The r-) structure 16 was formed. Next, conventional phosphorus deposition (or vapor deposition) and doping the surface area of the substrate 11 by using a diffusion process. to form a source 17 and a drain 18, and at the same time convert the polysilicon layer 15 into an n+ dope. Phosphorus deposition was accomplished at a temperature of about 900° C. for about 15 minutes. This person The final source and drain junction depth formed by the method is approximately 1 micron. The sample was subjected to a hydrogen annealing step at atmospheric pressure for approximately 30 minutes using a vacuum cleaner. Ani The cooling temperature is determined by the nature of the processing steps that follow the deposition steps described above. If nitrogen If a non-high temperature treatment is performed after the compound deposition, the hydrogen anneal will be equivalent to about 750°C. Can be achieved at low temperatures.

On the other hand, if a high temperature treatment is performed after nitride deposition (as in the case of this example) ), the hydrogen anneal must be performed at high temperature. In the current example, at 900℃ Annealed for 30 minutes. This high-temperature hydrogen annealing was caused by high-temperature heat treatment. Repairs deterioration in charge retention.

After the hydrogen anneal, a thick silicon dioxide layer is placed over the entire structure for electrical isolation of the device. A layer 19 was formed.

Contact holes are then etched through oxide 19 and source 17 and to make electrical contact with the drain 18. Therefore, aluminum Metallization is deposited on the base to form source 17 and drain 1, respectively. Contacts 21 and 22 for polysilicon 15 are formed and metal Contact 20 was formed. Dart contact 20 is schematically illustrated in FIG. 5A. ◎ Silicon-oxide-nitride monoxide-silicon (5ON08) shown in Figure 5B The process for forming the structure 100 is the process described above for forming the 5NO8 structure 10. After the nitride layer 13 is deposited, the intermediate oxide layer 14 is formed. Continue to add more. The intermediate oxide layer 14 is suitable for the decomposition of DO8 and nitrous oxide N20. Therefore, it was formed at the same temperature and pressure as the formed nitride. N20 vs D used The O8 ratio was 4:1. The flow rate of N20 is 90 CC per minute, DC8 (7) The flow rate was 22.5 CC teac per minute.

The cross-sectional structure depicted in FIGS. 5A and 5B is simply that of a typical memory device. This is only a schematic representation of the structure, presented here in its simplest form, and represents an embodiment of the invention. It should be understood that the figures are not drawn to scale for illustrative purposes. follow Therefore, you can easily think about the configuration architecture of other memory devices. Semiconductor electronic engineers can recognize that this is true. Above, 5A Although descriptions of the structures in Figures and Figure 5B have been given for various process steps, individual Neither the processing parameters nor the sequence of processing steps provided will create a memory device. They should not be construed as mandatory values or ordering, but should be understood as subject to change. You should understand.

Devices made in the manner described above were tested according to known test procedures. writing and erasing For example, the curves can be calculated by subjecting the device to various pulse forcing conditions (amplitude and width of the pulses). made by As shown in each figure, the The width was in the range of ±(10-30)■. The positive and negative ranges are typically n-chan. Applicable to writing and erasing data respectively for channel devices, and has a width of 4 was in the range of 10 microseconds to 1 second. The writing and erasing curves are was created by using the pulse amplitude and varying the pulse width by a multiple of 10.

Data to determine the charge retention capacity of the device was obtained by the following steps. (1) Initialize the device by determining initial write and erase threshold voltages.

(2) Storing the device at an elevated temperature of 100°C for a period of up to 105 seconds Create a retention force graph for a device that does not cycle, and calculate the threshold voltage during this period. Check pressure. (3) Write-erase cycle the device 105 times at 100°C. ( 4) Re-initialize the device according to step (1). (5) By step (2) A retention graph is generated for a device that has been cycled 10 times at elevated temperatures.

Initialization process (processes 1 and 4), that is, initial write and erase state threshold voltages Obtaining is +25 v no 9 of 10 ms width for each memory device dirt. This includes supplying a 23 V nozzle with a 100 msec width. source 17, The drain 18 and substrate 11 (Figure 5) are all set during this initialization stage. During.

connected to ground. The data obtained using the above method are shown in various graphs as detailed below. Reproduced in illustrative form.

Before considering in detail the characteristics of an exemplary device, we first introduce the predictions of the old two-current component model (pr It is useful to revisit the diagram. Oxide and nitride current and A prediction diagram for the threshold voltage is shown in FIG. In other words, Figure 3 shows the given orthogonal is the negative supply dart voltage, oxide and nitride currents, and the resulting maximum threshold voltage. This is what I drew. First, the initial memory oxide layer T. xl and related tons nel oxide current J. Consider xl. Increasing the positive (or negative) dart voltage will cause two The current J until the currents are equal. X decreases and the nitride current JN1 increases . This equilibrium point is T. The maximum pressure (or negative) threshold associated with xo, i.e. vT (or is −vT1). This equilibrium is due to the charge Q1 distributed near the oxide-nitride interface. It is a response to achievement. Let's look at Figure 4. This kind of oxide tunneling current Under dominance, there is no charge Q2 at the gate-nitride interface.

If the oxide thickness is T. If it increases to X□, the oxide current is J. reduced to x2 , the maximum predicted positive and negative thresholds decrease to vT□ and −■7□, respectively.

Although the nitride thickness varies, the initial electric field used for writing or erasing remains approximately constant. If the two-current component model is would have predicted the same amount as the load. According to theory, this charge is and is located near the oxide-nitride interface. If this applies here and now , the threshold can be made positive or positive by increasing the silicon nitride thickness according to the equation below: Any negative trapped charge should be increased.

Here, TNI is the nitride thickness, and Xc is the charge center of Q, which is unrelated to TNl. , Q is the amount of stored charge, KN□ is the dielectric constant of silicon nitride, and ε is the permittivity of free space ( dielectric constant).

6 and 7 show the best results obtained for the device 10 made as described above. Represents large threshold data.

The maximum threshold voltage is a function of memory oxidation physics (Figure 6) and silicon nitride thickness (Figure 7). expressed as a number. In the erasure of FIG. 6, the maximum negative threshold voltage is Decreases with increasing physics. This behavior is similar to the conventional two-current component model described above. Match the prediction. However, for writing, the data in Figure 6 is shows that the maximum pressure threshold actually increases slightly as the thickness increases. This conclusion The results do not match the predictions of the conventional two-current component model.

As seen in Figure 7, during erasing, the maximum negative threshold voltage increases with increasing nitride physics. do. This behavior is predicted from equation (4). However, during writing, the maximum pressure threshold The voltage is essentially constant, in contrast to the increasing threshold predicted by equation (4). be.

One of the most important characteristics for MNOS or other non-volatile memory devices is the This is the long-term retention power of gram data. Other features of the above devices 10 and 100 According to the characteristics display, its holding power is the best against memory oxidation physics of about 25 to 40X. In particular, it is optimal for the range of about 29 to 37λ around the optimum value of about 33. be. Look at Figures 8 and 9. 4.0　X thicker memory oxidation physics value However, the operation (erase) speed is reduced, the memory window is narrower, and the write The condition worsens. 25, the prior art characteristics of thin oxide devices Become closer to sex. For example, the rate of degradation is to undesirable prior art levels. To increase.

Traditional models have a thick memory oxide that increases retention and reduces operating speed. It was suggested that this could also be the cause of For this reason, the main effort in current technology is to This reduces the memory oxidation physics to increase the It takes place at a small sacrifice. For thicker 25-40X memory oxides The erase speed will be slower than that of a thin oxide. Look at Figure 10. However, the writing speed The degree is essentially unrelated to memory oxide. Let's look at Figure 11. Thus, the comparison An exemplary device 10 using a thick 25-40X memory oxide is shown in FIG. As shown in Figures 8 and 9, the non-volatile Give reinforcement. Such devices are especially EAROM (electrically rewritable read-only memory). Ideal for applications where write speed is important Ru.

Each bit of information is individually programmed into the EAROM K, and the write speed is therefore dependent on the This is usually critical to the performance of the entire system. But typically EAROM allows slow erasure as shown in Figure 10, so it is erased in blocks. be removed.

The holding power of the thick memory oxide 5NO8 device is further demonstrated in FIG. there is a 28X memory oxide (40 There is data for 8-nitrides). As shown, this thick memory The holding power of the oxide device is approximately 20 times (tw.) that of other comparable prior art devices.

decades) long.

Referring again to FIG. 7, by using a thin silicon nitride layer 13, the device Execution performance has also been improved. Write access in standard 5NO8/5ONOS memory devices The memory device's dart voltage is applied to the 5V signal used for control and logic functions. ±20-25V is typically required for the poles. Dimensions of transistors and interconnect lines The industrial drive to increase memory storage capacity by reducing the Leprosy is caused by dielectric breakdown between the conductive layers of the chip, especially when a 20-25V signal is used. Do not incorporate the necessary spacing to prevent damage. Problems arising from high voltage signals are those Because of their high mobility, electrons can be driven deep into insulating materials at high voltages and It is particularly acute for n-channel devices since it changes the optical characteristics.

One way to lower the programming voltage of a memory device is to reduce the nitride thickness. It's about making things easier. Considering the interaction in Figure 7, it is the program voltage It is useful to know that can be approximated according to the nitride thickness ratio. Dew. Typical prior art memory devices utilize a silicon nitride thickness of approximately 400 nm. requires a programming voltage of approximately 25V. For example, 200X silicon nitride thickness Reducing the required program is calculated by ('200/400) x 25V. This means that the system voltage can be lowered to about 12-13V. Traditional models are thin like that. Expect that a thin nitride will greatly reduce the initial memory window. I measured it.

However, Figure 71 shows that the prediction of this prior art is not necessarily correct. I'm watching. In short, nitride thicknesses below 400X, especially about 150X, are While it can be used to lower the gram voltage, the available memory You can also keep the window. Using a nitride thickness of 150 to 250 ・Non-volatile memory devices are not ±25V currently used in industry, It becomes possible to perform zolograms with a voltage of ±10 to 15V. initial memory - There is some loss of the window, which at most would be expected under conventional theory. is half of what it was and can still be used as a practical initial window . An initial win of 5 to 7 cm, as shown in Figure 7, represented by a 150 to 200X thick oxide. Dough is still useful for many applications.

Other properties not foreseen in the prior art include the thin interplane oxide layer 14 ( This is an increase in writing speed, which is an effect of 5ONO8). As shown in Figure 12, 5 Compared to NO8 devices (OX interplane layer), 5O with thin interplane oxide layer 14 NO3 devices exhibit both higher threshold voltages and increased write speeds in the write state.

The preferred thickness of the interplane oxide is in the range of 30-60X. When it becomes less than 30X , the characteristics of the device begin to approach those of the 5NO8 device. On the contrary, 60. When you exceed X, Erasing speed is reduced.

. Makes interplane oxides undesirable. For erasing, use the 5ONO8 device is slower than the conventional SNO,S device, and the magnitude of the maximum threshold voltage is smaller. mentioned above As mentioned above, erasing speed is important, and its characteristics are similar to EAROM memory. It does not pose a problem to the equipment.

5NO8/5ON using various combinations of the features of the improved structure described above. The operating characteristics of the O8 device are summarized in Table I.

(Margin below) 4 3-Current model In order to understand the new 3-current component model, the Simplified for 5NO8 structure 1o Let's look at the energy band diagram. Figure 13A shows negative dart bias -v Figure 13B illustrates the application of o (hereinafter also referred to as ``elimination''). The application of As+vG (hereinafter also referred to as "writing") is illustrated.Here, one current The component oxide tunnel current J8h is caused by the thin memory acid flowing from the accumulated p-type substrate. This is caused by hole tunneling through the oxide and into the dirt silicon nitride. Second The current component Jnh is the nitride Hall current. Jnh is -V, K is the gate arises from holes in the nitride driven by The third component Jgh is the heat against dirt. is the current. That is, leaving the nitride, the valence electrons of the n+ polysilicon date is the interfacial current for holes entering the band.

Since the oxide tunnel current Jsb is thicker than the nitride ball current Jnb, the positive charge is Negative dart bias causes build-up near the oxide-nitride interface. However, the port Since there is no energy barrier to the holes entering the silicon dart, the dart There is no appreciable charge build-up in the vicinity. As a result, the oxide-nitride interface There is a single center of charge near the surface. Charge is accumulated near the oxide-nitride interface , the electric fields inside the oxide and nitride alternate, reducing the dominant outer oxide tunneling current. to increase the nitride Hall current. This is the saturated negative threshold moxide current and nitride This continues until the currents are equalized. Increasing the oxide thickness channel current and reduce the saturated negative threshold. In short, nitride-dart Because there is no charge accumulation at the interface, this 3-current model replaces the traditional 2-current model. It is possible to predict the same erasure act as that predicted in Figure 3. I can do it. These predictions are shown in Figures 6, 7, 8, 10, and 12. This is concretely shown by behavioral data.

The situation seen in Figure 13B is due to the positive dart bias, i.e. the writing situation. Very different. Under a positive dart bias, the surface of the silicon substrate is inverted. It will be done. The tunneling current then flows from the inverted silicon surface through the oxide and into the nitride. dominated by tunneling electrons. This component is designated as J. second formation is again the hole current of silicon nitride. The third component, r-), is the interfacial current. Represents two possibilities. The first is from nitride to polysilicon dart conduction band. This is the transfer of electrons. However, the hole is the dominant charge key of silicon nitride. carrier and also for the transfer of electrons from the nitride to the silicon conduction band. Because there is an important potential barrier, the first case above is unlikely to occur. There's no way. Another possibility is hole injection into silicon nitride from dirt. be. Against Hall's transfer? The small tensile barrier and silicon nitride Considering the predominance of holes as charge carriers, this hole current Jgh is It is believed to dominate the gate interface current under positive bias. n+ polysilico Since the amount of available holes in the hole is quite small, for a given electric field, this current is much smaller than the nitride Hall current Jnh. This occurs at the oxide-nitride interface. In addition to those provided by Jse and JnhK, near the nitride-gate interface The accumulated negative charge should be taken into account. Thus, as shown in Figure 4, During loading, a double center of negative charge is established.

Charge accumulation near the nitride-polysilicon gate interface is due to the oxide-nitride interface. It lowers the electric field near the surface, thereby reducing the accumulation of negative charges at the interface.

As the electric field decreases within the nitride volume, the The electric field increases. This, in turn, increases hole injection from the dart. nitride The accumulation of charge in the injected dart current Jgh is due to This continues until the gate current Jnh and the injected gate current become equal.

In short, in Figure 4, this new 3-current component model Charge accumulation Q1 distributed adjacent to the silicon nitride interface and nitride-polysilicon The dominant (meaningfully large) charge accumulation Q2 distributed near the dart interface is Predict. This model explains the unexpected write behavior exhibited by devices 10 and 100. This is to clarify.

First, consider the write threshold vs. nitride data of FIG. Near the dirt electrode, In other words, the dominant charge at a relatively fixed distance from the electrode is independent of nitridation physics. Due to the trapped charge by the center Q2 and by the fixed distribution, the electric field is neutralized. The voltage required to cure will be the same regardless of the nitride thickness.

Next, consider the write threshold versus memory oxide data of FIG. Maximum pressure threshold pressure is As predicted in Figure 3, increasing the memory oxide layer does not reduce In reality, there has been a slight increase. dual centroid electric Although the loading model does not clearly explain this small increase in the threshold, we have observed that Actions by Ro are consistent with this model.

The unique writing speed shown in Figure 11 is also at a fixed distance from the dart, revealed by the dominant charge Q2, which is unaffected by changes in the moly oxide layer. It will be done.

Next, the effect of the intermediate oxide layer 14 will be explained. Looking at Figure 13B, we see that the correct dart Under bias, the interplane oxide provides a barrier to holes from polysilicon f- It acts as a channel barrier and reduces the hole current (Jgh) from dirt. child This causes large negative charge accumulation at the nitride-interface oxide interface, which by increasing the memory window (i.e., increasing the maximum write threshold voltage) do). Now, since Jgh is considerably smaller than the nitride Hall current Jnh, this current The large difference in enables easy writing.

As an example of an application of a memory transistor according to the invention, a series connected field effect transistor is Consider a 3-G) EAROM memory cell consisting of a transistor. exemplary EAROM is an international patent application PCP/US811017 filed by the same applicant as this applicant. There are 62 themes.

3-r-) The FAROM cell 110 has various electrical connections shown schematically. This is shown in the cross-sectional view of FIG. This cell has three transistors Q+, Consists of Q2 and Q3 connected in series. Ql to Q3 are originally field effect transfer gates or Although it is a capacitor, for convenience we will call it a transistor. n-channel ・Cell] 10 has a p- type substrate 111 with n+ doped regions 117 and 118 . Field effect gate/capacitor/transistor Q1 and Q3 are write and read respectively It has r-) electrodes 122 and 123 corresponding to electrodes vw and vR. Ql and 93 MNOS) transistor Q2 located in between is the dirt electrode 11 corresponding to the write electrode VM. 5, a silicon nitride layer 113, and a thin silicon dioxide layer 112A. whole The thick silicon dioxide region designated 112 provides electrical isolation between the various components. I can do it. As shown, the substrate 111 is connected to ground potential, and the n+ dodode region 11 7 is the bit line electrode VB+ via the contact layer 124. The n region 118 is electrically connected to the electrode v8. Model 3-ke9 - The address settings of the EAROM cells are set on the bit line VB and the word write line V. w and erasing and writing are performed by a common memory line vM. The reading is performed using the low voltage memory line signal and the read line vR command signal. It will be done.

Cell 110 has a memory oxide in the range 30-36X thick and approximately 380-400X thick. Made of silicon nitride.

For this cell, the written threshold VTI is approximately +(7-8]■, the erased threshold VTO is approximately -2v and programming voltage is +25v (write) or -25V (Delete) It was torn. Similarly, this cell is easily fabricated with a thin silicon nitride layer 113. It will be done. For example, the 200X silicon nitride layer 113 is a 10X to 20X thick memory layer. oxide] about +(6-7)V tv vTl and about -IV17)V for 12A Provide TO. The resulting program voltage is approximately 1.2V. Thickness above Program for device 110 using thin oxide 112A and nitride 200X thickness The voltage is also approximately ±12V, and vTl and VTO are within the range given above. It is within the surrounding area.

Typically, transistors Q1 and O3 have their respective dirt electrodes VW and vFL The energizer conducts when the voltage exceeds the +1 ■ dirt - source threshold voltage. mode, n-channel device. Transistor Q2 has a dirt electrode vM It operates through one zologram.

To form a conductive path through cell 110 between VB and 78, a transistor All Ql-Q3 must be turned on. Here, the logic of the cell is Defined as H state. A logic “1” state is defined as there being no conduction path between VB and vs. be justified.

FIG. 14 also represents an arithmetic circuit for programming and reading the state of the cell. of Node 8 is normally connected to system ground, and bit node vB is connected to switch SW. Depending on the position, it is either at ground potential or +5■. The resistance value of resistor R is the node If there is a conducting path between vB and 78, it is sufficient to place node vB at approximately ground potential. This is a high value.

In the following discussion of the operation of cell 110, memory transistor Q2 is Assume that it was erased to the VTO threshold before the write cycle. to erase A negative programming voltage is applied to the memory electrode vM for about 100 ms, but y −1’V, r Vwr VR+V, %D lightning voltage not forced (i.e. O V or 5v).

A high voltage signal is supplied to the vM to erase the VTO from any existing level ( Shift the threshold to the ERASE) state.

The following truth table gives various voltage combinations for writing and erasing cell 11.0. Ru.

1 0 0 VTO0 201VTOO 310VTI 1 4 1 1 VTOO *0 represents OV; 1 represents +5v **0 represents conductive; 1 represents non-conductive To illustrate writing transistor Q2 to a VTI state representing Let's think about it. A 1 ms write pulse (W RITE) is supplied to ■ya, and at the same time +5■ is supplied to vw and VB and vR. OV is supplied. ■. The 0■ level at prevents conduction through O3, causing VB and The voltage combination of Vw causes Q+ to conduct, and the n+ donode region 11 at the Ov level Connect 7 to the O2 channel. As explained in detail below, this is the erased V From the TO threshold to the VTI threshold written, i.e. the resulting O2 writing It is very important.

To illustrate programming a logic “0” to a cell, consider Example 4 in Table ■. Good morning. Here, a group of write pulses (WRITE) is again supplied to vM, and v +5V is supplied to w, and Ov is supplied to . However, in this case, bit mate V B receives the +5V signal. Both the impurity region 117 and the gate 122 are +5V. Ql is kept non-conducting. Because there is no conducting path through Ql or O3 , which effectively floats memory transistor Q2 and changes the erase threshold voltage of O2. prevent changes.

A number of short 1 millisecond pulses are used to control writing. Sunawa First, the write voltage (WRITE) is supplied to drive the substrate surface into a deep decision region. move.

Therefore, the write voltage (WRITE) is mainly supplied to the substrate, and the write voltage (WRITE) is applied to the dielectric. Sufficient voltage must be applied to the dielectric layer to provide a threshold voltage that changes the carrier voltage. Not supplied. However, unless the ie pulse is very short, electron-hole generation will occur immediately. By collapsing the deep decision region, the device is written to the VTI. In short, high duty cycles are all but 0°1. Write (or maintain) one for every VB and VW combination in the VTO. I guarantee you it will. The combination shown in Example 3 of Table ■ (VB and vw are 0°1 ), the diffusion region 117 supplies electrons to the O2 channel and instantly expands its depth. Collapse a large decision region. As a result, the r-) bias for 7M is Apply sufficient voltage across the dielectric layers to write O2 to its VTI threshold.

In the read mode, send a +5V command signal to vR, a +5V address signal to vw, and VB. Execute by supplying a high impedance +5V signal to vM and a 0■ readout question signal to vM. do. For the VTI threshold (Example 3), the read voltage (READ) in ■9 is VT Since it is less than I, Qz does not conduct. Therefore, node vB should not be grounded to node v8. stomach. This corresponds to a logic "1#" state for this cell. Conversely, the VTO threshold In contrast, the read voltage of vM is sufficient to conduct Qz. Also, Ql and +5V high impedance of bit mate VB due to conduction of Qz and Qz. The voltage is grounded through node vS. During read mode, Ov is present in node vB. The presence corresponds to a logic "0" state of the cell.

As an application example of the 3-dart memory cell 110 embodying this invention, Consider the 4-cell matrix memory array depicted in FIG.

These cells were organized into symmetrical column pairs. xx, yx and XY, like YY Each pair has a common line v8 and a common line ■8, which is also common to the adjacent column. ・Bit line vB′t? have Word line specified by vw and 7w2 are connected to transistors Q1 in each designated row of the array.

The array of FIG. 15 was designed as a VLSI integrated circuit layout. line V , is formed of a doped substrate region and the bit line VB is a metal conductor; The read word and memory lines are preferably doped polysilicon. stomach. The array of FIG. 15 can be expanded to an array of M rows by N columns. For that , M row address lines and N column address lines respectively address M rows of structural cells and and N column lines must be accessed. This array can be programmed by supplying a negative program voltage to vM as described above. , the block is erased.

The configuration of FIG. 15 has one associated VB line and two associated four cell pairs. lines to enable selective programming of the cells in those pairs. example For example, if cells XX and yx are to be written to O and 1, lines VB and VW is set to OV and normal write is performed in 41 rus is applied to line vM and +5v is added to line vw2. Change For example, when writing these cells to 1 and 1, apply +5v to VWl as well. Same as Noculus Siegenst above, except that! By applying a And it will be achieved. VB2 of this adjacent column pair XY and YY is +5V. is unaffected by this write sequence.

To read the array of FIG. 15, the read line vR is energized with +5v and the memory - line vM is set to the read voltage and the bit line signal is connected to lines VB and and VB□, and a conduction path is formed on line 8 through Qz and the cell. The bit line voltage is read indicating the presence of the ground potential generated at the time.

The above is an improved 5NO8 and 5ONOS memory device structure and use of the structure. . Described the memory system.

The exemplary device described and represented above is an n-channel n+ silicon goo. NO8/5ONO8 structure, but this invention is similar to aluminum MNO8. It is easy to see that it could also be applied to other structures, including metal dart structures. I think it can be understood.

Si SiOSi, N4 Holly S; FIG, 2 FIG.3 FIG. 6 FIG.7 FIG.8 FIG.9 Me-Nanasu-go [Iotfu’y4 (S) FIG.t.

Harima C sho) Pulse- international search report

Claims (1)

[Claims] 1 A semiconductor substrate (11) and a memory monoxide provided on the substrate (11) a silicon layer (12) and silicon nitride on the memory silicon oxide layer (12); a layer (13) and an intermediate silicon oxide layer (14) on said silicon nitride layer (13). and a dart electrode (15) on the intermediate silicon oxide layer (14), The memory silicon oxide layer (12) has a thickness in the range 25-40X and The intermediate oxidation 72937 layer (14) has a threshold variation with a thickness in the range 30-60X. Renewable semiconductor memory device. 2. The gate electrode (15) is formed of polycrystalline silicon. A semiconductor memory device with variable threshold value. 3. Claim 2, wherein the dart electrode (15) is formed of n-type polycrystalline silicon. The threshold value changeable semiconductor memory device described in . 4. According to claim 3, the substrate (11) is formed of p-type single crystal silicon. A semiconductor memory device whose threshold value can be changed. 5. The silicon nitride layer (13) has a thickness in the range of 150 to 250X. A threshold changeable semiconductor memory device according to item 1.