JPS584946A - Manufacture for buried wiring layer - Google Patents

Abstract

PURPOSE:To flatten a title device with a simplified process by a method wherein an Al.Si alloy layer is bonded on a semiconductor substrate with an intermediary of an insulation film to form a predetermined shape, enclosing the periphery thereof with an Al layer of eacy oxidizing property and converting it into an insulating layer, when a buried wiring layer is formed. CONSTITUTION:A device provided Si substrate 1 is coated with an SiO2 insulating layer B1 which in turn is covered with an Al.Si alloy made conductive layer C1 and then with Mo layer D1 that is a lift off means. Then a prescribedly shaped photoresist mask layer M1 is provided at the central portion of the surface. Next, etching is performed for the dismantling of the exposed portions of the layers D1 and C1. The mask layer M1 is then removed and the whole surface is coated with an Si3N4 layer F1. After this, stepped layers G1' and G1 are formed composed of such an easily oxidizable material as Al and then converted into insulating layers I1 and I1' by electroless chemical treatment. The layer I1 and the layers F1 and D1' situated thereunder are removed for the formation of a buried wiring layer W1 that is a part of a conductive layer C1 surrounded with the layers I1 and I1'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a buried wiring layer suitable for use in forming a multilayer wiring layer of a conductor integrated-II device.

Various single-layer tIIR methods have been proposed, but all of them require complicated processes, and even if it is possible to flatten the resulting trench wiring layer, it is difficult to planarize it. Therefore, even if you try to obtain a multi-layer embedded wiring layer, there is a limit to increasing the number of layers, and furthermore, it is difficult to obtain the embedded wiring layer by making the paper machine finer. However, there is a certain limit to the miniaturization, and for this reason, if the buried wiring layer can be made finer, the substrate on which the buried wiring layer is formed can be made much smaller. Therefore, the present invention aims to propose a new method for forming a buried wiring layer that does not have the above-mentioned drawbacks, which will become clear from the detailed description below. Probably.

1I41(6) shows an example of a paper for forming a buried wiring layer according to the present invention which is applicable when obtaining a multi-layer wiring layer of an integrated circuit device.
For example, 5io2 to improve the surface of the semiconductor substrate body 1 consisting of
A substrate 2 having an insulating layer B1 formed thereon is prepared in advance (FIG. 1A), and a conductive layer made of, for example, Aj-81 alloy is coated on the main surface of the substrate 2, that is, on the upper surface of the insulating layer B1. The chemical layer 01 and the lift-off layer D1 made of, for example, MO are formed in that order (FIG. 511B).

Next, on the upper surface of the layer D1 for 7 to 7, an i-layer M1 made of, for example, photoresist and having a required pattern IA pattern is applied.
is formed by methods known per se (si Fig. 0).

Next, using the mask layer M1 as a mask, the layer D1 for lift-off and the conductive layer 01 are etched, for example, by reactive ion etching, so that the conductive layer C1 and the layer D1 for lift-off are formed in the area under the mask layer M1. W
1 and a lift-off layer DI' (FIG. 1D).

Next, the mask layer &i1 is removed from above the lift-off layer DI' (FIG. 1g), and then the wiring layer W1 and the area other than the wiring layer W1 and the lift-off layer DI' of the substrate 2 and the insulating layer B1 are removed. An insulating layer F1 made of silicon nitride, for example, which is resistant to subsequent chemical oxidation treatment and is continuously extended on the outer surface of the lift-off layer DI' is formed by a known method such as plasma OVD ( 1st rI!J
F).

Next j (base fj2, therefore, on the upper surface of the area other than under the wiring layer W1 and the lift-off layer D1' of the insulating layer B1, and the insulating layer F
For example, A
The easily oxidizable layers G1 and G1' consisting of / are simultaneously formed, for example, by vapor deposition (FIG. 1G).

Next, chemical oxidation treatment ζ for easily oxidizable layers G1 and G1'
From this, insulating layers 1 and I1' are formed by chemically oxidizing the easily oxidizable material of the easily oxidizable layer G1 and ad (see FIG. 1H).
). In this case, the chemical conversion oxidation treatment is performed on easily oxidizable layers G1 and 0.
1'' is made of AI!, the insulating layer 11 and the I
1' may be made of boehmite (Al2O, -H,O).

Next, the lift-off layer DI' is formed by etching the insulating layer F1 using the insulating layer 11 and IIF as a mask to form a slit S1 in the insulating layer F1 to expose the lift-off layer DI' to the outside. 1' on the upper insulation layer
An insulating layer T1 consisting of 1 and 1 is formed on the other insulating layers (glWJI). In this case, the etching process may be an etching process using AP4 gas plasma when the insulating layers 11 and 11' are made of boehmite as described above and the insulating layer F1 is made of silicon nitride.

Next, the lift-off layer DI' is subjected to an elution treatment using the insulating layer T1 as a mask.
The wiring layer W1 is removed from the wiring layer W1 along with the insulating layer I1' and the insulating layer T1 from above the wiring layer W1 (Fig. 1J'). and 11 to obtain the embedded layer U1 of the first layer diagram.

next#! Ii of the first embedded wiring layer U1! That is, on the wiring layer W1 and the insulating layers 11 and 1, the wiring layer W is resistant to chemical oxidation treatment similar to the chemical oxidation treatment described above.
An insulating layer B12 made of, for example, silicon nitride and having a window H12 that exposes 1 to the outside is formed (FIG. 1K).

Next, to improve the surface of the insulating layer B12, the detailed explanation will be omitted, but let's look at the t-edge layer B12! 111 Using III, which was considered to be the insulating layer B1 on the substrate 1 described above in FIG. J (as shown, on #C on layer 1 W1, layer W12 for connection to wiring layer W1 corresponding to wiring layer W1 to be connected to this layer is formed on insulating layer 112 and layer 12 corresponding to layer 1). A JII layer with a structure of 1!!A layer for butterbur Q12 is obtained.

Next, $1 layer @v) 111 wiring layer connection layer Q12 determination, ie ki1 layer continuous connection layer 711 W 12% and insulation layer 1
Candy aI mentioned above at %m11111 in 12 and 121
An insulating layer B2 similar to layer B12, but having a layer 11H2 that externalizes the interconnecting layer W12, is designated in the first paragraph as corresponding to the absolute layer B1 on the base @1 mentioned above in -1-. As mentioned above in the example above, it is formed with the knee of the box (411
1M).

Next, a process similar to that described above is performed on the surface of the insulation 482, resulting in JIM11! As shown in iIN, insulating layer B2
A distribution layer W connected to the arrangement II layer connection layer W12 on top
1 and #Ili-like 1 layer W2 is embedded in the insulating layer 11 and the insulating layer 12 and 2 of the
A second buried wiring layer U2 having a configuration is obtained.

Hereinafter, the same process as described above is repeated, and the second, third, etc. buried wiring layer connection wQ23, G34, etc. are formed on the second buried wiring layer C2. . . . to obtain the 6th, 4th, . . . -th embedded wiring layers U3, C4, .

The above is an example of a method for forming a buried wiring layer according to the present invention, which is applicable when obtaining a multilayer wiring layer of a semiconductor integrated circuit device.
A first layer on which a wiring layer W1 is embedded with an insulating layer 11
A second layer in which a wiring layer W2 connected to the wiring layer W1 via a wiring layer connection layer W12 is buried on the buried wiring layer C1 with an insulating layer I2. Embedded wiring layer U2.・・・・・・・・・ is formed in sequence, so it is a semiconductor integrated circuit device! In this case, the embedded wiring layer U1. U2.・・・・・・
. . . can be easily obtained by flattening the steps described above in FIGS. 1 A to J and steps similar thereto, and therefore, semiconductor Even if the multi-layer wiring layer of the circuit device is obtained as having a large number of layers, the multi-layer arrangement layer can be easily formed without the habit of disconnecting.
2...... wiring layer W1゜W2...
- can be easily formed finely in a self-aligned manner using a pattern of a mask layer (Ml, M2---1...),
Therefore, the substrate can be made more compact without making the substrate unnecessarily large due to the embedded wiring layer.

In the above description, JHI-forming layers (G1 and G1', G2
and G2'......) is AI!・Although the embodiment has been described in which there is a St gold alloy, the exclusive column layer may be a metal or, for example, the Al! alloy mentioned above!・Although alloys containing St gold alloys are acceptable, as long as they are easily oxidized materials that undergo chemical oxidation and become oxidized by chemical conversion oxidation treatment, they can be used even if they are not A/・85 alloys. It will be obvious that various modifications may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIGS. 1 to 1N are line sectional views of a sequential IHc process showing an example of a method of forming a buried wiring layer according to the present invention. In the figure, 2 is the substrate, C1 is the conductive koji, Ml is the mask layer, W
l and W2 are wiring layers, W12 is a wiring layer connection layer, 11,
It', 12 and 112 are insulating layers, B1'% B12, B
2, Fl, K1, K1', K2 is an insulating layer, G1 and G1' are easily oxidizable layers, and K12 and K2 are windows, respectively. Applicant Nippon Electric Telephone Public Corporation < Agonye l -1 Qlow - (5:E:

Claims (1)

[Claims] A step of forming a conductive layer and a first lift-off layer on a substrate in that order, and forming a first mask layer having a wiring pattern on the first lift-off layer. and etching the lift-off layer of 111 and the conductive layer using the first mask layer as a master, thereby etching the conductive layer and the first lift-off layer under the mask layer. A step of forming a wiring layer and a layer for 1Ii2 glue 7 to 7, and a region other than under the wiring layer and the second lift-off layer of the substrate, and outside the wiring layer and the second lift-off layer. a step of forming a continuous insulating layer on the surface of the substrate;
The first and second layers are placed on top of the 112 lift-off layers.
a step of simultaneously forming easily oxidizable layers of the first and #! Chemical oxidation of the first and second oxidizable layers by chemical oxidation I & field of the first and second oxidizable layers
! a step of forming second and second insulating layers formed by chemical oxidation of a chemically oxidizing material; a step of forming a fourth insulating layer by forming a slit in the first insulating layer to expose the lift-off layer II2 to the outside; and a second lift-off layer using the fourth insulating layer as a master. removing the lift-off layer 1 from above the wiring layer together with the region above the second glue 7 to 7 layer of the insulating layer 3 and the insulating layer 114 by dissolving J611 to A glue formation method for embedded wiring layers characterized by: