JPS5849079A - Phase controller - Google Patents

Phase controller

Info

Publication number
JPS5849079A
JPS5849079A JP14656581A JP14656581A JPS5849079A JP S5849079 A JPS5849079 A JP S5849079A JP 14656581 A JP14656581 A JP 14656581A JP 14656581 A JP14656581 A JP 14656581A JP S5849079 A JPS5849079 A JP S5849079A
Authority
JP
Japan
Prior art keywords
pulse
circuit
voltage
time
phase control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14656581A
Other languages
Japanese (ja)
Inventor
Noriyuki Katsurayama
葛山 典幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14656581A priority Critical patent/JPS5849079A/en
Publication of JPS5849079A publication Critical patent/JPS5849079A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE:To obtain the maximum control output by delaying by the prescribed time a synchronizing signal which operates a discharging circuit which discharges a condenser and resets a blocking oscillator. CONSTITUTION:A pulse (c) having time duration of t2-t0 is formed by the first monostable multivibrator MM1 which is triggered by the fall of a synchronizing signal SY as an input signal, and a pulse (d) having time duration of t3-t2 is formed by the second monostable multivibrator MM2 which is triggered by the rise of the signal SY. The pulse width t3-t2 is the time which can sufficiently discharge completely a condenser C. When the time width of the multivibrator MM1 is suitably set to produce a pulse at 180 deg.C-alpha, a terminal voltage (e) can be obtained at the condenser C, the maximum output waveform of the controlled output reduces to affect the influence of the firing angle alpha, thereby approaching the input voltage to the maximum output voltage of a voltage controller.

Description

【発明の詳細な説明】 (1)発明の属する技術分野 本発明はサイリスタ等の半導体の点弧位相上制御するた
めの位相制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a phase control device for controlling the firing phase of a semiconductor such as a thyristor.

(2)従来技術およびその問題点 単相電源を半導体であるサイリスタ、トライアtり等を
用いて電圧制御する場合において、そのサイリスタまた
燻トライアック會点弧嘔せるグー) t4ルスを発生す
る位相制御装置の1つとして抵抗とコンデンサの時定数
回路で負性抵抗素子たとえばUJT (ユニジャンクシ
、ントランジスタ)t−作動させるし張発振回路を用い
た回路があげられる。
(2) Prior art and its problems When controlling the voltage of a single-phase power supply using a semiconductor thyristor, triac, etc., the phase control that generates the t4 pulse is difficult because the thyristor or triac is ignited. One such device is a circuit using a time constant circuit of a resistor and a capacitor, which operates a negative resistance element such as a UJT (Unijunction Transistor), and uses a tension oscillation circuit.

このよりなUJT を用いたダート/4ルス発生回路か
らなる位相制御装置の構成kl!1図に示す。
The configuration of a phase control device consisting of a dirt/4 russ generation circuit using this flexible UJT is kl! Shown in Figure 1.

仁の回路においては、位相制御用信号電圧CVで抵抗R
1を介してコンデンサCが充電されコンデンサCot位
がUJTUのピーク点電圧に達した時、UJTUがター
ンオンする。その瞬間UJTUを通して抵抗R2に電流
が流れると同時に抵抗R3にも電流が流れる。抵抗Rj
に流れた電流はトランジスタQ1に供給され、トランジ
スタQ1がオンとなる。したがって、トランジスタQ1
のコレクタにつながっているパルストランスPTの1次
側にif UJTUがターンオンする瞬間だけ電流が流
れ2次側にノヤルスを誘起させる。
In Jin's circuit, the resistance R is set at the phase control signal voltage CV.
When the capacitor C is charged through the capacitor C and reaches the peak voltage of the UJTU, the UJTU is turned on. At that moment, current flows through UJTU to resistor R2, and at the same time, current also flows to resistor R3. Resistance Rj
The current flowing through the transistor Q1 is supplied to the transistor Q1, and the transistor Q1 is turned on. Therefore, transistor Q1
A current flows through the primary side of the pulse transformer PT connected to the collector of IF UJTU only at the moment when it is turned on, inducing Noyals on the secondary side.

このノヤルスがサイリスタまたはトライア、りのダート
パルスとして利用される。なお、R4は抵抗であ)、Q
jFi同期信号syによジオンとなってコンデンサCt
放電させるトランジスタである。
This Noyalus is used as a dart pulse for a thyristor or tria. Note that R4 is a resistor), Q
jFi synchronous signal sy turns into a ion and capacitor Ct
This is a transistor that discharges electricity.

このコンデンサCの充電開始タイ建ング、つまりこのf
−)パルス発生回路の同期のとシ万として電源電圧の極
性が反転する点を基準としf:、電源同期信号を採用し
た場合の電源電圧とコンデンサCの端子電圧等の関係1
82図に示す。
When this capacitor C starts charging, that is, this f
-) Based on the point where the polarity of the power supply voltage is reversed in case of synchronization of the pulse generation circuit, f: Relationship between the power supply voltage and the terminal voltage of capacitor C when a power supply synchronization signal is adopted 1
Shown in Figure 82.

すなわち第2図(a)は電源電圧を示す番第2図(b)
は周期信号SYであシ、電源電圧の極性が反転する点に
対応してパルスがめられれる。′:1ンデンサCは第2
図(e)に端子電圧を示すように時間1.から充電がは
じt j) UJTUのピーク点電圧に達しダートパル
スが発生するまでには、UJTUの発振条件を決足する
抵抗RとコンデンサCによる時定数回路の時定数によシ
制約されるti−1oというある一定の時間がかかる。
In other words, Fig. 2(a) shows the power supply voltage, and Fig. 2(b) shows the power supply voltage.
is a periodic signal SY, and a pulse is generated corresponding to the point where the polarity of the power supply voltage is reversed. ′:1 Densa C is the second
Figure (e) shows the terminal voltage at time 1. Charging begins from t j) Until the peak point voltage of UJTU is reached and a dirt pulse is generated, ti is constrained by the time constant of the time constant circuit made of resistor R and capacitor C, which determines the oscillation conditions of UJTU. It takes a certain amount of time -1o.

このtl−1・なる時間と、同期信号SYの/中ルス幅
の半分との和に相当する角度が点弧角αとなる。
The firing angle α is an angle corresponding to the sum of this time tl-1· and half of the /intermediate pulse width of the synchronizing signal SY.

サイリスク、トライア、り等に対する位相制御装置とし
て上述のダートパルス発生回路を用いた場合、入力実効
電圧を■とすれば最大出力実効電圧はVXl(1+頷α
)となり、最大量力時の電圧制御出力波形は、第2図(
d)に示すように点弧角αに相当する電圧が欠けてしま
い入力電圧に対し最大出力電圧はUJTUの発振条件に
より制限される点弧角αに相当した分だけ低くなってし
まうという問題がある。
When the above-mentioned dart pulse generation circuit is used as a phase control device for sirisk, tria, ri, etc., if the input effective voltage is ■, the maximum output effective voltage is VXl (1 + nod α
), and the voltage control output waveform at maximum capacity is shown in Figure 2 (
As shown in d), there is a problem that the voltage corresponding to the firing angle α is missing, and the maximum output voltage is lower than the input voltage by the amount corresponding to the firing angle α, which is limited by the oscillation conditions of the UJTU. be.

(3)発明の目的 本発明はサイリスタ、トライアック等を点弧制御するた
め・抵抗とコンデンサの時定数回路で負性抵抗素子を作
動させるし張発振回路を用いて構成した位相制御装置に
おいて、最大制御出力taは入力に等しい値にまで(全
点弧近くまで)高めることを可能とすゐ位相制御装置を
提供すること上目的としている。
(3) Purpose of the Invention The present invention is for controlling the firing of thyristors, triacs, etc. - A phase control device configured using a tension oscillation circuit in which a negative resistance element is actuated by a time constant circuit of a resistor and a capacitor. The purpose is to provide a phase control device that allows the control output ta to be increased to a value equal to the input (close to full ignition).

(4)発明の構成 時定数回路のコンデンサ管放電させるし張発振回路をリ
セットさせる放電回路を作動させるための同期信号を予
定時間遅延させる遅延回路を設けたことt−%黴として
いる。
(4) Construction of the Invention A delay circuit is provided for delaying a synchronizing signal for a scheduled time to operate a discharge circuit for discharging the capacitor tube of the time constant circuit and resetting the oscillation circuit.

(5)発明の実施例 第3図は本発明の一実施例を示すものである。(5) Examples of the invention FIG. 3 shows an embodiment of the present invention.

第3図に示す構成は、第1図に示した従来の回路のコン
デンサC1−リセットするトランジスタQ2に対する同
期信号の入力路に@1 、[2の単安定マルチバイブレ
ータ(以下「モノマルチ」と称する) MHI 、 b
mlUからなる遅延回路を追加したものである。
In the configuration shown in FIG. 3, a monostable multivibrator (hereinafter referred to as "mono-multi") of @1 and ) MHI, b
A delay circuit consisting of mlU is added.

こ 楔のような構成における動作について説明する。child The operation in a wedge-like configuration will be explained.

第4図に第3図の構成における各部の波形を示す・第4
図(&)は電源電圧波形を示す。第4図(b)は第2図
(b)に示したものと同じ電源同期信号SYである。こ
の同期信号sYを入力信号としその立下シによりトリガ
される纂1のモノルマルチMMJで第4図(、)に示す
ようなtl−t・の時間幅を有するパルス波形をつくる
。さらに・このt4ルス波形出力を入力とし1その立下
りでトリガされる第2のモノマルチMM、?で第4図(
d)に示すよりなtl−4,の時間幅を有するパルスを
つくる。このパルス幅ts −tmはコンデンサcl完
全に放電させるに足シる時間であることが必要である。
Figure 4 shows the waveforms of each part in the configuration of Figure 3.
The figure (&) shows the power supply voltage waveform. FIG. 4(b) shows the same power synchronization signal SY as shown in FIG. 2(b). Using this synchronizing signal sY as an input signal, the first monaural multi-MMJ is triggered by the falling edge of the synchronizing signal sY to generate a pulse waveform having a time width of tl-t. as shown in FIG. 4(,). Furthermore, a second monomulti MM that receives this t4 pulse waveform output as input and is triggered by the falling edge of the t4 waveform output, ? Figure 4 (
Create a pulse having a time width of tl-4, as shown in d). This pulse width ts - tm needs to be long enough to completely discharge the capacitor cl.

この第4図(d)に示す第2のモノマルチMMZの出力
/4’ルスが本実施例でトランジスタQ2に供給される
リセット信号でこのリセット信号を発生させる位相を第
1のモノマルチ四1の時間幅七適宜設定して180°−
αに発生させるようにすればコンデンサCの端子電圧波
形は第4図(、)に示すようになシ、制御出力の最大出
力波形は第4図(f)のように、vK2図(d)に示し
た従来回路の場合に見られた点弧角αの影響を少なくし
、入力端子に対しサイリスタ、トライブック等による電
圧制御回路の最大出力電圧を近づけることが可能となる
・ なお、本発明は上述し且つ図面に示す実施例に限足され
ることなくその要旨會変更しない範囲内で種々変形して
冥施することかできる。
In this embodiment, the output/4' pulse of the second monomulti MMZ shown in FIG. Set the time width appropriately to 180°-
If it is generated at α, the terminal voltage waveform of capacitor C will be as shown in Figure 4(,), and the maximum output waveform of the control output will be as shown in Figure 4(f), and vK2(d) as shown in Figure 4(f). It is possible to reduce the influence of the firing angle α seen in the case of the conventional circuit shown in , and to bring the maximum output voltage of the voltage control circuit using a thyristor, trybook, etc. closer to the input terminal. The invention is not limited to the embodiments described above and shown in the drawings, and can be modified in various ways without changing the gist of the invention.

例えば、モノマルチMMJ 、 MMJの組合せの他単
に同期信号【遅延させる他の遅延回路管用いてもよく、
tたし張発振回路を構成する負性抵抗素子I UJTで
な(pnpn形スイッチング素子等としてもよい。
For example, in addition to a mono-multi MMJ or a combination of MMJs, other delay circuits that simply delay the synchronizing signal may also be used.
The negative resistance element I that constitutes the tension oscillation circuit is not a negative resistance element (IUJT) (it may also be a pnpn type switching element, etc.).

(6)  発明の効果 し張発振回路の負性抵抗素子の発振条件に対し時定数回
路の時定数設足等の電気的余裕lILを太きくし、且つ
最大制御出力をはは入力値と同値(tづけることができ
る。
(6) The effect of the invention is to increase the electrical margin lIL such as the time constant setting of the time constant circuit for the oscillation condition of the negative resistance element of the tension oscillation circuit, and to increase the maximum control output to the same value as the input value ( You can add t.

【図面の簡単な説明】[Brief explanation of the drawing]

纂1図は従来装置の構成を示す回路図、第2図(a)〜
(d)は真1図に示した従来装置の各部動作波形図、第
3図は本発明の一実施例の構成を示す回路図、第4図は
同笑施例における各部動作波形図である。 MMJ 、 M)AX・・・単安定マルチバイブレータ
(モノマルチ)、U・・・ユニジャンクショントランジ
スタ(UJT)、C・・・コンデンサ、RJ〜R4・・
・抵抗、QJ、QJ・・・トランジスタ、PT・・・パ
ルストランス。
Figure 1 is a circuit diagram showing the configuration of a conventional device, Figure 2 (a) -
(d) is an operational waveform diagram of each part of the conventional device shown in Figure 1, Figure 3 is a circuit diagram showing the configuration of an embodiment of the present invention, and Figure 4 is an operational waveform diagram of each part in the same embodiment. . MMJ, M)AX...monostable multivibrator (mono multi), U...unijunction transistor (UJT), C...capacitor, RJ~R4...
・Resistor, QJ, QJ...transistor, PT...pulse transformer.

Claims (2)

【特許請求の範囲】[Claims] (1)  抵抗とコンデンサの時定数回路で負性抵抗素
子を作動させるし張発振回路管用いた位相制御装置にお
いて、前記;ンデンサを放電させ前記し張発振回路をリ
セットさせる放電回路を作動させる次めの同期信号會予
足時間遅延させる遅延回路を備えたことtW黴とする位
相制御装置。
(1) In a phase control device that operates a negative resistance element using a time constant circuit of a resistor and a capacitor and uses a tension oscillation circuit tube, the following step is to operate the discharging circuit that discharges the capacitor and resets the tension oscillation circuit. A phase control device comprising a delay circuit for delaying the synchronization signal period.
(2)  負性抵抗素子はエニジャンクシ、ントランジ
スタであることt−特徴とする特許請求の範囲[1項記
載の位相制御装置。 (3ン  遅延回路は、同期信号でトリガされ所要遅延
時間にほぼ対応する予定時間幅の/4ルスを発生する纂
lの単安定マルチバイブレータと、仁の第1の単安定マ
ルチバイブレータの出力でトリガされし張発振回路のリ
セットに必要な〕奢ルス暢に対応する予定時間幅のパル
ス七発生する第2の単安定マルチバイブレータとで構成
されたこと1*黴とする特許請求の範囲第1項記載の位
相制御装置。
(2) The phase control device according to claim 1, characterized in that the negative resistance element is an arbitrary transistor. (3) The delay circuit consists of the output of the first monostable multivibrator, which is triggered by a synchronization signal and generates a quarter pulse with a scheduled time width approximately corresponding to the required delay time, and the first monostable multivibrator of Jin. and a second monostable multivibrator that generates seven pulses with a predetermined time width corresponding to the luxury pulse necessary for resetting the triggered oscillation circuit. The phase control device described in .
JP14656581A 1981-09-17 1981-09-17 Phase controller Pending JPS5849079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14656581A JPS5849079A (en) 1981-09-17 1981-09-17 Phase controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14656581A JPS5849079A (en) 1981-09-17 1981-09-17 Phase controller

Publications (1)

Publication Number Publication Date
JPS5849079A true JPS5849079A (en) 1983-03-23

Family

ID=15410545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14656581A Pending JPS5849079A (en) 1981-09-17 1981-09-17 Phase controller

Country Status (1)

Country Link
JP (1) JPS5849079A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60259089A (en) * 1984-06-06 1985-12-21 Yoshiro Nakamatsu Speaker equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60259089A (en) * 1984-06-06 1985-12-21 Yoshiro Nakamatsu Speaker equipment

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