RU1835598C - Slow-down generator of square-wave pulses - Google Patents

Abstract

Usage: in the field of pulsed technology for obtaining rectangular pulses in cases when the recovery device requires zero recovery time. The inventive rectangular pulse generator, consisting of a counter 1 with a potential output and a blocking generator on a pn-transistor 18 with windings of a pulse transformer 12 included in the base and emitter circuits of the indicated transistor, the counter clock input is connected to the pnp emitter -transistor blocking generator. The counter is triggered by counting the pulses of the blocking generator by cutting the pulse of the blocking generator. Due to this, at the end of the output pulse of the device, the time of the generator driving capacitor 11, the role of which is the blocking generator capacitor, is charged to the initial voltage, and transients associated with the restoration of the initial conditions are excluded. Using counter 1, while maintaining a zero recovery time, it was possible to expand the range of durations generated by a braked rectangular pulse generator. 2 ill. with/. with

Description

The invention relates to the field of pulsed technology. A device made in accordance with the proposed solution can be used to obtain rectangular pulses in cases when the recovery device requires zero recovery time. Such braked rectangular pulse generators (with zero recovery time) are used as reference sensors, independent of the start frequency, time intervals; as pulse delay devices with a constant delay value; in relaxation frequency dividers with increased values of the division coefficient.

The aim of the invention is to increase the duration of the generated pulses while ensuring zero recovery time and reducing the size of the device.

In FIG. 1 shows a circuit diagram of the proposed device; in FIG. 2 - implementation of the proposed device using an integrated pulse counter; in FIG. 3 - voltage graphs at characteristic points of the proposed device.

Before proceeding to the description of the operation of the device, we will explain some of the terms used in the description text.

00

with

00

potential exit. This is a counter whose output from each of the bits is generated in the form of a voltage level. This type includes counters on triggers made on bipolar and field effect transistors, integrated counters on universal logic elements. Counters on ferro-transistor cells have no potential output and are unsuitable for use in the proposed device. The applied counter is reset by the positive edge at the reset input.

The pulse transformer in the proposed device is included in the blocking generator circuit with windings included in the emitter and base circuits of the bipolar pnp transistor. With this inclusion, the number of turns of the secondary (base) winding should be greater than the number of turns of the primary (emitter) winding. Only in this case can the conditions for the occurrence of a blocking process be provided.

The use of the remaining elements is not required. We proceed to consider the composition and operation of the proposed device.

The proposed device consists of:

a pulse counter with potential output 1 having a setup input 2, a counting input 3, a high-order output 4, and an inverse high-order output 5;

-potentiometer 6 having one terminal 7, another terminal 8 and the output of the engine 9;

- time of the driving resistor 10;

-time master capacitor 11;

a pulse transformer 12 having one output of the base winding 13, another output of the base winding 14, one output of the emitter winding 15 and another output of the emitter winding 16;

diode 17;

a bipolar pnp transistor 18;

input terminal 19;

-output terminal 20;

terminals for supplying power to the blocking generator 21.

The installation input 2 of the pulse counter with potential output 1 is connected to the input terminal 19..Country input 3 of the pulse counter with potential output 1 is connected to one terminal 15 of the emitter winding of the pulse transformer 12, with the anode of the diode 17 and with the emitter of a bipolar solution transistor 18. The high-order output 4 of the pulse counter with potential output 1 is connected to the output terminal 20. The inverse output 5 of the pulse counter with potential output 1 is connected to one terminal 7 of potentiometer 6, the other terminal 8 of which is connected to one terminal m time of the driving capacitor 11 and with the collector of a bipolar pnp transistor 18, as well as with a common bus (housing) of the device. The terminal 9 of the slider of the potentiometer 6 is connected to one time terminal of the master resistor 10, the other terminal of which is connected to the other terminal of the master time

capacitor 11 and with one terminal 13 of the base winding of the pulse transformer 12. Another terminal 14 of the base winding of the pulse transformer 12 is connected to the base of a bipolar pnp transistor 18.

5 Another terminal 16 of the emitter winding of the pulse transformer 12 is connected to the cathode of the diode 17 and to the power terminal of the blocking generator 21.

The proposed device works

0 as follows.

In the stable state of the device, at the output 4 of the high order of the pulse counter 1 with a potential output, the logic zero voltage is set to

5 inverse output 5 high order of the specified counter - voltage of the logical unit. The voltage of the logical unit from the inverse output 5 of the high order of the counter 1 is supplied to the potentiometer 6;

0 part of this voltage is removed from slider 9 of potentiometer b. The voltage taken from the slider 9 of potentiometer 6 is numerically equal to Uc max - the maximum voltage that occurs at

5 time of the master capacitor 11 when the blocking generator is operating on the bipolar pnp transistor 18 in the self-oscillating mode, the value Uc max is greater than the supply voltage of the blocking generator supplied

0 to terminal 21. Since the voltage taken from the slider 9 of potentiometer b is greater than the supply voltage of the blocking generator, the bipolar transistor 18 is locked, the time of the capacitor 11 is charged

5 to voltage Uc max. In this state, the device can remain as long as desired - until a trigger signal arrives at input terminal 19.

The input trigger pulse is supplied to the input of setting 2 of counter 1 and sets the output of the high order bit 4 of the specified counter to a logic 1 signal. At the output terminal 20, the front of the output pulse is formed. At the same time on

5, inverse output 5 of the high order bit of counter 1, a logic zero signal is set. Accordingly, a low level of the output voltage also appears at the output of the slider 9 of the potentiometer 6. The time charged capacitor 11

it starts to discharge after a time - the resistor 10 and the output resistance of the potentiometer (from the side of the slide 9). The time voltage of the drive capacitor, and hence the base of the bipolar pnp transistor 18, is reduced. When it becomes less than the power supply to the blocking generator supplied to terminal 21, the emitter junction of the bipolar RLR transistor 18 receives a forward bias. Considering that the number of turns of the base winding of the pulse transformer 12 is greater than the number of turns of the emitter winding, it can be verified that the conditions for the blocking process are satisfied in the blocking generator formed by the bipolar pnp transistor 18 and the pulse transformer 12. The bipolar transistor 18 is turned on avalanchely, and the process of forming the top of the output pulse of the blocking generator begins. By the end of the pulse of the blocking generator, the time of the drive capacitor 11 will be charged to a voltage of Uc max. After that, the transistor 18 is turned off, and the time of the driving capacitor 11 again begins to discharge after a time, the driving resistor 10 and the output resistance of the potentiometer 6. The output pulse of the blocking generator is removed from its emitter; it arrives at the counting input 3 of counter 1. The counting input of 3-counter 1 is dynamic: the operation is performed by cutting the incoming pulse of the blocking generator.

When the time of the drive capacitor 11 is again discharged and the voltage on it becomes less than the supply voltage of the blocking generator, the latter generates a second pulse, which again emits from the emitter of the bipolar transistor 18 to the counting input 3 of counter 1 and counted by this counter.

The processes in the blocking generator are repeated, as a result of which it generates a series of pulses, from the first to the nth. The number n depends on the size of the counter, the number of its highest order.

The nth output pulse of the blocking generator, arriving at the counting input 3 of counter 1, causes the voltage to switch in its high order. At output 4 of the high order of counter 1, the voltage will switch to a logic zero level. Thus, a slice of the output pulse is formed at terminal 20 and the output pulse ends.

The voltage at the inverse output 5 of the high order of the counter 1 takes the value logical 1. At the output 9 of the engine

the potentiometer b sets the voltage equal to Uc max. Since the voltage at the time-driving capacitor 11 has also reached Uc max since the cut-off of the n-th output pulse of the blocking generator, a further voltage change for the time of the driving capacitor 11 is stopped. and there are no transients of a change in the duration of the master capacitor after the end of the output pulse at terminal 20 in the device. The device recovery time is zero.

The duration of the output pulse of the device is n times longer than the pulse repetition period of the blocking generator. As a result, it is possible to realize a longer output pulse duration even with a relatively small inductance

0 magnetization of a pulse transformer and, accordingly, a small capacitance time of the driving capacitor 11.

We emphasize in addition the features of the device that are necessary for

5 understanding of the essence of the alleged invention:

a) Switching of the counter 1, corresponding to the formation of a slice of the output pulse of the device, occurs by slice

0 (trailing edge) of the last pulse of the pulse series of the bocking generator. When triggered by the cutoff of the pulse of the blocking generator, it turns out that the timing of the master capacitor 11 has completely (

5, the voltage Uc max) is charged by the current of the base winding of the pulse transformer flowing during the pulse generation of the blocking generator. Since after switching the counter to the time

0 the resistance from the potentiometer slide receives a voltage equal to Uc max too, then with such a functioning of the device elements after forming a cut of the output pulse at terminal 20, no

5, transients of voltage variation at the time of the master capacitor do not occur, in which case, recovery processes and, accordingly, recovery time.

0b) In principle, ensure equality

voltage Uc max arising on the capacitor as a result of its charging by the pulse current of the base winding of the pulse transformer during formation

5 pulse blocking generator. and voltage removed from the potentiometer engine at the output level of the logic unit at the output 5 of the counter is always possible only with a finite degree of accuracy. But even with a small (within

accuracy) the inequality of these values, the proposed device has advantages in comparison with the prototype: ceteris paribus, for example, at the same output pulse duration, the proposed device requires up to five times shorter setpoint capacitance; because of this, the process of equalizing the voltages (Uc max and coming from the divider with a finite adjustment accuracy) is five times faster. As a result, even with a finite accuracy of providing a voltage adjustment, the recovery time will be vanishingly small.

The basic device in relation to the proposed can be considered a prototype device according to ed. USSR N 661724. Compared with the base device, the proposed device has almost the same advantages that were noted when comparing with the prototype, namely:,

- the range of durations of the output pulse that can be implemented in the device without recovery time is expanded (upward); the device is ensured in the millisecond and second ranges of the duration of the output pulse;

-reduced the dimensions of the device by eliminating the need to use a pulse transformer with a significant magnetization inductance and a large capacitive ringing capacitor;

Claims (1)

- ceteris paribus (the same duration of the output pulse, the same permissible dynamic deviation of the duration), the requirements for the accuracy of setting the voltage at the output of the potentiometer are reduced, which increases the adaptability of the device. SUMMARY OF THE INVENTION A retarded rectangular pulse generator comprising a blocking generator on a transistor connected according to a common collector circuit, with pulse transformer windings included respectively in the base and emitter transistor circuits, which defines an RC circuit whose output is connected to a free terminal the base winding of a pulse transformer, the output of the resistor sets the time. The RC circuit is connected to a movable the output of the potentiometer, one of the outputs of which is connected to the output of the capacitor by the time of the driving RC circuit and with the common bus of the device, characterized in that, in order to increase the duration of the generated pulses while maintaining the zero recovery time and reduce the dimensions of the device, a pulse counter with a potential an output whose high-order output is connected to the output bus, the high-order inverse output is with the other output of the potentiometer, the setup input is with the input bus, and the counting input is with the trans emitter stories blocking oscillator.  g Figure 1 gMftrtt t rt en tv. s g FC2 2 -Nairazhvnvyv at the exit sargsgo bit yes 4 counters 1 The voltage on the VRM task, the capacitor is P G &UGJ; Tfortgi T -M  , 5B No.m  Irfm T