JPS5848966A - Manufacture of insulated gate field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the shortening of channel length by projecting the bent section of a common mask and making the width of a reverse conduction type gate region larger than other sections when the reverse conduction type gate region and one conduction type source region are formed to one conduction type semiconductor substrate through double diffusion by using the common mask. CONSTITUTION:When the reverse conduction type gate region 2 and one conduction type source region 3 positioned into the region 2 are shaped to one conduction type semiconductor substrate 1 through double diffusion by employing the common mask 10 consisting of SiO2, etc., the mask 10 is formed as follows. That is, the rectangular projections 11 obliquely projected to the corner sections of the mask 10 are shaped previously, and the regions 2, 3 are formed through diffusion. Accordingly, since the regions 2, 3 spread under the mask 10 only by the diffusion depth, the ends of the regions 2 enter to the inside only by d from the mask 10 when the diffusion depth of the regions 2 is d. When the width l of the projections 11 is set previously to the condition of l<2d, the gate regions 2 are also generated under the projections 11, and the channel length of the regions 2 is lengthened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an insulated gate field effect semiconductor device.

Recently, a DSA MOS (MOS) run lister using the double diffusion method has been proposed. Refuse DSA MOS) As shown in Fig. 1, the lung nut consists of a semiconductor substrate (1) which becomes an N-type drain region, and a P-type gate region (jd) formed by double diffusion using the same diffusion mask (1) surface C of the substrate (1). [2+!
and the N-type source region 131, the gate 'Wl pole (51) provided on the insulator m1 (41) on the gate region (2), and the source fIi +31 (neem
It consists of an electrode 16) and a drain electrode (7) provided on the back surface of the substrate +13.

In the DSA MOS described above, the channel length is determined by the diffusion depth C of the gate region (2) 8 and the source region (3), and has the advantage that the channel length can be freely set by the self-line effect. .

However, in such a DSA MOS) run lister, more than 1,000 cells are connected in parallel to two devices T in order to achieve high output.
Ru. For this reason, the diffusion mask of each cell is extremely high 11FW
resolution! A photo-etching process is required. However, in a high-precision photoetching process, there is a drawback that it is not possible to accurately resolve the curved part C of the diffusion mask 0, such as a part of the corner corner shown in FIG. f2. For this reason, if double diffusion is performed using such a diffusion mask OQ, the diffusion end of the source region (31) with a shallow diffusion depth will be disturbed and the gate channel length at the bend will be shorter than at other parts. This leads to a deterioration in breakdown voltage as shown by the dotted line in Figure 4 (2).

The present invention has been made in view of the above-mentioned drawbacks, and is intended to realize a method for manufacturing an insulated gate field effect semiconductor device that completely eliminates the conventional drawbacks. C An embodiment of the present invention will be described in detail.

According to the present invention, after forming a diffusion mask 01ll on a semiconductor substrate (1) with a diagonal rectangular protrusion υ at a bent portion as shown in FIG. 3 as shown in FIG. The gate region (212) and the source region (3
1 is diffused by two electric currents. As a result, the gate region (2) extends below the diffusion mask 0 by its diffusion depth, and the source region (3)
) similarly spreads under the diffusion mask ae. Therefore, if the diffusion depth of the gate region (2) is d and T, the end of the gate region (2) penetrates from the diffusion 77 by a distance d from Oa.

Therefore, if the width of the protrusion 2 is l, then if T is set so that l + 2α, the area under the protrusion 011 of the diffusion mask will be completely diffused into the gate region (21, and the same diffusion shape as without the protrusion 011tl) will be created. - 10,000 source region (31 diffusion depth vs. I is set to #287r, so the source region with an edge almost similar to the pattern of diffusion mask 01 (2) 31 diffusion shapes are obtained.

Normally, the gate channel length is given by d-s, but in the protrusion aυ of the diffusion mask O(l) of the present invention, a channel length larger than d-8 can be obtained, and the gate region at the bent part (2) of the diffusion mask u(l (2) Deterioration in breakdown voltage due to short or short distances can be completely prevented.

As a specific example, the present inventor has developed dt'10. IIm,S
is set to 2 doors m, and l is set to 15 voices. As a result, there was no abnormal pressure waveform shown by the dotted line in the gJ4 diagram, and a normal pressure waveform shown by the solid line was obtained.

As detailed above, according to the present invention (2), by improving the shape of the curved portion of the diffusion mask, shortening and shortening of the length due to the disturbance of photoetching of the diffusion mask at the curved portion can be prevented. (Drain-source breakdown voltage deterioration due to two causes can be completely prevented. Therefore, high-output DI9AMO8 with over 1000 cells) If the run lister is damaged, even a single defective cell can cause the device to fail. Therefore, the effect of the present invention is significant.The object of the present invention can be achieved if the shape of the protrusion is not only rectangular but also semicircular and protrudes downward toward the saw 7 area.

[Brief explanation of drawings]

11] is a cross-sectional view to explain the DSA Mis) run lister, and Figure 2 is a top view to explain the conventional diffusion mask.
FIG. 3 is a top view illustrating the diffusion mask of the present invention, and FIG. 4 is a -VDR characteristic diagram illustrating the withstand voltage of the conventional MOS (MOS) run lister and the present invention. Explanation of the main figure numbers: (1) is the semiconductor substrate, (2) is the gate region, (31 is the source region, 01 is the diffusion mask, old) is the protrusion.

Claims (1)

[Claims] In a method for manufacturing an insulated gate field effect semiconductor device in which a gate region 8 of an opposite conductivity type and a source region of one conductivity type are double-diffused T using a common mask on a semiconductor substrate of a t-conductivity type, A method for manufacturing an insulated gate field effect semiconductor device, in which the bent portion is made to protrude and the width of the gate region formed by double diffusion is made larger than other portions.