JPS5848946A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5848946A
JPS5848946A JP14736281A JP14736281A JPS5848946A JP S5848946 A JPS5848946 A JP S5848946A JP 14736281 A JP14736281 A JP 14736281A JP 14736281 A JP14736281 A JP 14736281A JP S5848946 A JPS5848946 A JP S5848946A
Authority
JP
Japan
Prior art keywords
internal wiring
package
exposed
semiconductor device
end surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14736281A
Other languages
Japanese (ja)
Inventor
Mamoru Yanagisawa
柳沢 守
Hidehiko Akasaki
赤崎 英彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14736281A priority Critical patent/JPS5848946A/en
Publication of JPS5848946A publication Critical patent/JPS5848946A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent the electrostatic breakdown of a semiconductor element by coating the side surface of a ceramic package, the end surface of internal wiring thereof is exposed, with an insulating film. CONSTITUTION:Polyimide 7 in approximately 10-20mum is printed or applied onto the side surface of the package base body 1, the end surface of internal wiring thereof is exposed. A polyimide film is manufactured in such a manner that polyamide is diluted up to predetermined concentration by the solvent of N methyl-2 pyrrolidone, and a polyamide film is formed, cured at 80, 150 and 250 deg.C in succession and changed into imide. According to this constitution, a body having potential such as a finger and the internal wiring end are isolated by the polyimide film when the device is treated, and the electrostatic breakdown of the element is prevented.

Description

【発明の詳細な説明】 本発明は半導体装置の構造に係り、特にプラグ、イン、
タイプのパッケージに封入されてなる半導体装置の外部
構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and particularly to a plug, an in,
This invention relates to the external structure of a semiconductor device enclosed in a type of package.

高集積度の半導体集積回路(XC)K於ては、内部配線
が多層に形成され、且つ底面に多数の接続ピンが単数又
は複数列にわたって配設されてなるプラグ・イン・タイ
プのセラミック・ノくツケージが用いられる。そしてし
構造のノくツケージは、通常のセラミック・ノ(ツケー
ジと異なシ内部配線の全面がパッケージの上面に表出し
ていない、従って内部配線のボンディング・パッド部、
内部配線と電気的に接続している電極ビン、及びチップ
ステージ等に金(Au )等の電気メッキを施す際に、
通常の方法で被メツキ部に電位を附与することができな
い。そのため該パッケージに於ては多層に形成されてい
る内部配線の端面をパッケージの側面に表出させて置き
、該側面上に各内部配線の端面に接する一連のメッキ用
電極を形成しておいて、該電極からパッケージ上に露出
している被メツキ部に電位を与えてメッキがなされる。
In high-density semiconductor integrated circuits (XC), plug-in type ceramic nodes have internal wiring formed in multiple layers and a large number of connection pins arranged in one or more rows on the bottom surface. A shoe cage is used. Unlike ordinary ceramic cages, the entire internal wiring is not exposed on the top surface of the package, so the bonding pads of internal wiring,
When electroplating gold (Au) etc. on electrode bins and chip stages that are electrically connected to internal wiring,
It is not possible to apply a potential to the part to be plated using normal methods. Therefore, in this package, the end surfaces of the internal wiring formed in multiple layers are exposed on the side surface of the package, and a series of plating electrodes are formed on the side surface in contact with the end surface of each internal wiring. Plating is performed by applying a potential from the electrode to the portion to be plated exposed on the package.

そしてメッキが終った後にパッケージの側面から前記メ
ッキ用電極を削シ落として、内部配線を個々に分離する
という手段が用いられる。従ってこのようなプラグ・−
イン拳タイプのパッケージに於てはその側面に内部配線
の端面が表出した構造にならざるを得ない、そのため該
バクケージを用いて形成した半導体装置に於ては、該半
導体装置を取り扱う際にパッケージ側面に触れる指先等
から内部配@に電位が負荷されて、半導体素子が静電気
破壊を起こすことがままある@ 本発明は上記プラグ・イン・タイプのノくステージによ
って形成された半導体装置に於ける、半導体素子の静電
気破壊を防止する構造を提供するものである。
After plating is completed, the plating electrode is scraped off from the side surface of the package to separate the internal wirings individually. Therefore, such a plug -
The inside-type package has a structure in which the end surface of internal wiring is exposed on the side surface, so when handling a semiconductor device formed using the back cage, it is difficult to handle the semiconductor device. A potential is applied to the internal wiring from a fingertip touching the side surface of the package, which often causes electrostatic damage to the semiconductor element. The present invention provides a structure that prevents electrostatic damage to semiconductor devices.

即ち本発甲は、但11面に内部配線の端面が表出したセ
ラミック・パッケージに半導体素子が搭載されてなる半
導体装置に於て、該セラミック・ノ(ステージの側面上
に該側面を覆う絶縁膜が設けられてなることを特徴とす
る。
In other words, this patent provides that in a semiconductor device in which a semiconductor element is mounted on a ceramic package with the end surface of internal wiring exposed on the 11th side, the ceramic It is characterized by being provided with a membrane.

以下本発BAを一実施例について、図を用いて詳細に5
明する。なお第1図はセラミック・)くステージの側面
模式図、第2図は本発明の一実施例に於ける斜視図であ
る。
The following is a detailed explanation of one example of this BA using diagrams.
I will clarify. Note that FIG. 1 is a schematic side view of a ceramic stage, and FIG. 2 is a perspective view of an embodiment of the present invention.

本発明の半導体装置を構成するセラミックψノくステー
ジの構造を概念的に示したのが第1図の側面模式図で、
図に於て1は積層セラミック基板、(パッケージ基板)
、2は内部配線、3はスルーホール、4は電極ピンを表
わしている。即ち該パッケージに於ては、図に示すよう
に各層の内部配線2の端面はパッケージの基体である積
層セラミック基板1の側面VC5出している。そして積
層セラミック基板1の下面に配設されているIF極ビン
4は、それぞれスルーホール3を介して内部配1II2
に電気的に接続これている。
The schematic side view of FIG. 1 conceptually shows the structure of the ceramic φ stage that constitutes the semiconductor device of the present invention.
In the figure, 1 is a multilayer ceramic board (package board)
, 2 represents internal wiring, 3 represents a through hole, and 4 represents an electrode pin. That is, in this package, as shown in the figure, the end surface of the internal wiring 2 of each layer is exposed to the side surface VC5 of the laminated ceramic substrate 1, which is the base of the package. The IF pole bins 4 arranged on the lower surface of the laminated ceramic substrate 1 are connected to the internal wiring 1II2 through the through holes 3, respectively.
This is electrically connected to this.

又図示されていないが、内部配線の一部であるボンディ
ング・バッド領域及び特定の内部配線に接続するチップ
・ステージは、積層セラミック基板1上に表出している
。そして積層セラミック基板面lに表出していない内部
配線、スルーホール内の導電膜等は、通常タングステン
(W)、モリブデン(Me)  等のメタライズ層で形
成されておシ、基板から表出した領域即ちボンティング
・パッド部(図示せず)、チップ・ステージ(図示せず
)及び前記電極ピン4上にはAuメッキが施されている
Although not shown, a bonding pad region that is part of the internal wiring and a chip stage connected to a specific internal wiring are exposed on the multilayer ceramic substrate 1. Internal wiring, conductive films in through holes, etc. that are not exposed on the surface of the laminated ceramic substrate are usually formed of a metallized layer of tungsten (W), molybdenum (Me), etc., and the areas that are exposed from the substrate. That is, the bonding pad portion (not shown), the chip stage (not shown), and the electrode pins 4 are plated with Au.

本発明を適用しようとする半導体装置は、上記のような
セラミック・パッケージのチップ・ステージ上に半導体
IC等のチップをダイス付けし、該半導体チップの配線
パッドと前記内部配線のボンディング・パッドとの間を
ワイヤ・ボンディングで接続して形成する。従って前述
したような素子の靜寥気破壊が生ずるわけであるe 第2図は上記静電気破壊を防止する本発明の造に於ける
一実施例の斜視図を示したもので、図に於て1は積層セ
ラミック基板(パッケージ基体)、4は電極ピン、5は
キャップ、6はシール・パターン、7は絶縁膜を表わし
ている。
In a semiconductor device to which the present invention is applied, a chip such as a semiconductor IC is diced onto a chip stage of a ceramic package as described above, and wiring pads of the semiconductor chip and bonding pads of the internal wiring are bonded together. These are formed by connecting them with wire bonding. Therefore, static electricity breakdown of the element as described above occurs. Figure 2 shows a perspective view of an embodiment of the structure of the present invention for preventing the above-mentioned electrostatic breakdown. Reference numeral 1 represents a laminated ceramic substrate (package base), 4 an electrode pin, 5 a cap, 6 a seal pattern, and 7 an insulating film.

即ち本発明の構造に於ては第2図に示すように内部配線
の端面(図示せず)の表出しているパッケージ基体1の
側面上に、該側面を覆う例えば厚さ10〜20〔μm〕
程度の高ll!縁性を有するポリイミド、エポキシ等有
機高分子系のP縁膜7が設けられてなっている6そして
該絶縁膜7は印刷式るいは塗布等の方法で形成されるが
、該絶I#膜7を、半導体素子搭載前のパッケージに形
成する際には、半導体装置が完成するまでに、チップの
ダイス付けに於て400〜430(℃)程度及びキャッ
プ付けに於て330(℃)程度の加熱がなされるので、
該P縁膜7として耐熱性に優れたボリイオド膜が用いら
れる。なお核ポリイミドMはポリアミドをNメチル−2
ピロリドン等の溶剤により所望の11度を希釈し、印刷
式るいは塗布等の方法によシ所望厚言のポリアミド膜を
形成した後例えば80(℃)、I 50(℃)、250
〔℃)程度の所望のステップ・キュアを行って前記ポリ
アミド膜をイミド化して形成する。
That is, in the structure of the present invention, as shown in FIG. 2, on the side surface of the package base 1 where the end surface (not shown) of the internal wiring is exposed, a layer with a thickness of, for example, 10 to 20 [μm] is placed to cover the side surface. ]
Very high level! A P-edge film 7 made of organic polymer such as polyimide or epoxy is provided6 and the insulating film 7 is formed by a method such as printing or coating. When forming 7 into a package before mounting a semiconductor element, the temperature is about 400 to 430 (℃) for chip dicing and about 330 (℃) for capping until the semiconductor device is completed. Because heating is done,
A polyiodide film having excellent heat resistance is used as the P edge film 7. In addition, core polyimide M is polyamide N-methyl-2
After diluting the desired 11% with a solvent such as pyrrolidone and forming a polyamide film of the desired thickness by printing or coating, for example, 80 (℃), I 50 (℃), 250
The polyamide film is imidized and formed by performing a desired step curing at about [° C.].

又該絶縁膜をチップ搭載、キャップ付けの完了したパッ
ケージ基体の側面上に形成する際には、該絶縁膜は使用
状1i!!lK於て半導体装置に負荷される温度に充分
に耐える有機高分子船縁膜で秦く、エポキシ樹脂等が多
用される。
Furthermore, when forming the insulating film on the side surface of the package base on which the chip has been mounted and the cap has been attached, the insulating film is used in the usage condition 1i! ! Epoxy resin or the like is often used as an organic polymer membrane that can sufficiently withstand the temperature applied to semiconductor devices at 1K.

以上説明したように1本発明の構造を有するプラグ・イ
ン構造のパッケージを用い次半導体装置に於ては、パッ
ケージ側面に表出している内部配線の端面上が、高給縁
性を有する絶縁膜で橿われている。従って該半導体装置
を取り扱う際に、指先等電位を有する物体と内部配線の
端面との間が該絶縁膜により隔?ばれるので半導体素子
の静電気破壊が完全に防止される。
As explained above, in a semiconductor device using a plug-in structure package having the structure of the present invention, the end surface of the internal wiring exposed on the side surface of the package is covered with an insulating film having a high supply voltage. Being kidnapped. Therefore, when handling the semiconductor device, the insulating film may be used to separate the end surface of the internal wiring from the object having the same potential as the fingertip. Therefore, electrostatic damage to semiconductor devices is completely prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はプラグ書インeタイプφセラミック・パッケー
ジの伸直模式図で、第2図は本発明の半導体装置に於け
る一実施例の斜視図である。 図に於て、1は積層セラミック基板(パッケージ基体)
、2は内部配線、3はスルーホール、4は電極ピン、5
はキャップ、6はシール・パターン、7は給線膜を示す
。 枦 / 斤 策 、2− 后
FIG. 1 is a schematic diagram of a plug-in e-type φ ceramic package, and FIG. 2 is a perspective view of an embodiment of the semiconductor device of the present invention. In the figure, 1 is a multilayer ceramic substrate (package base)
, 2 is internal wiring, 3 is through hole, 4 is electrode pin, 5
6 indicates a cap, 6 indicates a seal pattern, and 7 indicates a feed line membrane.枦/斤法, 2-after

Claims (1)

【特許請求の範囲】[Claims] 側面に内部配線の端面が表出したセラミック・パッケー
ジに半導体素子が搭載されてなる牛導体装置に於て、該
セラミック・ノくツケージの側ffi上VC該側面を覆
う絶縁間が設けられてなることを特命とする半導体装置
In a conductor device in which a semiconductor element is mounted on a ceramic package with the end surface of internal wiring exposed on the side surface, an insulating gap is provided on the side ffi of the ceramic socket cage to cover the side surface of the VC. Semiconductor equipment with special mission.
JP14736281A 1981-09-18 1981-09-18 Semiconductor device Pending JPS5848946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14736281A JPS5848946A (en) 1981-09-18 1981-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14736281A JPS5848946A (en) 1981-09-18 1981-09-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5848946A true JPS5848946A (en) 1983-03-23

Family

ID=15428480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14736281A Pending JPS5848946A (en) 1981-09-18 1981-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848946A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869473A (en) * 1971-12-22 1973-09-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869473A (en) * 1971-12-22 1973-09-20

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